| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.81 | 99.36 | 92.13 | 97.68 | 100.00 | 98.55 | 97.91 | 99.06 |
| T305 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_max_throughput_chk.2365470513 | Oct 12 02:31:45 AM UTC 24 | Oct 12 02:31:58 AM UTC 24 | 477409247 ps | ||
| T306 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all.1076710505 | Oct 12 02:31:19 AM UTC 24 | Oct 12 02:31:59 AM UTC 24 | 1658198532 ps | ||
| T307 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all.1961771485 | Oct 12 02:30:57 AM UTC 24 | Oct 12 02:32:00 AM UTC 24 | 842246254 ps | ||
| T308 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.945192160 | Oct 12 02:28:34 AM UTC 24 | Oct 12 02:32:01 AM UTC 24 | 3622376810 ps | ||
| T309 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2772539369 | Oct 12 02:27:49 AM UTC 24 | Oct 12 02:32:01 AM UTC 24 | 2991585012 ps | ||
| T310 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.581122190 | Oct 12 02:27:01 AM UTC 24 | Oct 12 02:32:03 AM UTC 24 | 5292790428 ps | ||
| T311 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_alert_test.946642299 | Oct 12 02:31:52 AM UTC 24 | Oct 12 02:32:05 AM UTC 24 | 1536506494 ps | ||
| T312 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_kmac_err_chk.2756797437 | Oct 12 02:31:35 AM UTC 24 | Oct 12 02:32:06 AM UTC 24 | 553741994 ps | ||
| T313 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3445579610 | Oct 12 02:29:53 AM UTC 24 | Oct 12 02:32:09 AM UTC 24 | 6322636302 ps | ||
| T314 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_kmac_err_chk.2370782718 | Oct 12 02:31:47 AM UTC 24 | Oct 12 02:32:11 AM UTC 24 | 370169842 ps | ||
| T315 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.1581614599 | Oct 12 02:31:21 AM UTC 24 | Oct 12 02:32:13 AM UTC 24 | 6745779251 ps | ||
| T316 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_max_throughput_chk.1565382167 | Oct 12 02:31:53 AM UTC 24 | Oct 12 02:32:13 AM UTC 24 | 558386348 ps | ||
| T317 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_alert_test.1304817103 | Oct 12 02:31:59 AM UTC 24 | Oct 12 02:32:13 AM UTC 24 | 351903045 ps | ||
| T318 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all.971113491 | Oct 12 02:31:31 AM UTC 24 | Oct 12 02:32:14 AM UTC 24 | 2074294982 ps | ||
| T319 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_kmac_err_chk.3534440998 | Oct 12 02:31:56 AM UTC 24 | Oct 12 02:32:17 AM UTC 24 | 1415700502 ps | ||
| T320 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_max_throughput_chk.4116172952 | Oct 12 02:32:00 AM UTC 24 | Oct 12 02:32:19 AM UTC 24 | 2027358004 ps | ||
| T321 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_alert_test.457457494 | Oct 12 02:32:06 AM UTC 24 | Oct 12 02:32:20 AM UTC 24 | 699718631 ps | ||
| T322 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_max_throughput_chk.1010058162 | Oct 12 02:32:10 AM UTC 24 | Oct 12 02:32:24 AM UTC 24 | 766259336 ps | ||
| T323 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.736088596 | Oct 12 02:28:06 AM UTC 24 | Oct 12 02:32:25 AM UTC 24 | 18203836866 ps | ||
| T324 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all.1443424326 | Oct 12 02:32:00 AM UTC 24 | Oct 12 02:32:27 AM UTC 24 | 241567739 ps | ||
| T325 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.2767304813 | Oct 12 02:30:45 AM UTC 24 | Oct 12 02:32:29 AM UTC 24 | 9413408098 ps | ||
| T326 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_kmac_err_chk.1554406088 | Oct 12 02:32:02 AM UTC 24 | Oct 12 02:32:29 AM UTC 24 | 1943034462 ps | ||
| T327 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_alert_test.3937160460 | Oct 12 02:32:14 AM UTC 24 | Oct 12 02:32:30 AM UTC 24 | 1069757879 ps | ||
| T328 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all.617218959 | Oct 12 02:31:42 AM UTC 24 | Oct 12 02:32:36 AM UTC 24 | 5850909554 ps | ||
| T329 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_kmac_err_chk.269551318 | Oct 12 02:32:14 AM UTC 24 | Oct 12 02:32:40 AM UTC 24 | 385061793 ps | ||
| T330 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.3729744098 | Oct 12 02:31:07 AM UTC 24 | Oct 12 02:32:41 AM UTC 24 | 7886168295 ps | ||
| T331 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1022950068 | Oct 12 02:27:53 AM UTC 24 | Oct 12 02:32:51 AM UTC 24 | 15172388186 ps | ||
| T332 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.835470953 | Oct 12 02:29:14 AM UTC 24 | Oct 12 02:32:54 AM UTC 24 | 3285535493 ps | ||
| T333 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all.2513495452 | Oct 12 02:31:52 AM UTC 24 | Oct 12 02:32:54 AM UTC 24 | 779817392 ps | ||
| T334 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all.4071147054 | Oct 12 02:32:06 AM UTC 24 | Oct 12 02:32:57 AM UTC 24 | 802612721 ps | ||
| T335 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.1606714828 | Oct 12 02:28:20 AM UTC 24 | Oct 12 02:33:01 AM UTC 24 | 4433789818 ps | ||
| T336 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.3059455235 | Oct 12 02:28:50 AM UTC 24 | Oct 12 02:33:02 AM UTC 24 | 3288045249 ps | ||
| T337 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.1179349626 | Oct 12 02:28:19 AM UTC 24 | Oct 12 02:33:07 AM UTC 24 | 17718663419 ps | ||
| T338 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.1263418648 | Oct 12 02:30:37 AM UTC 24 | Oct 12 02:33:08 AM UTC 24 | 5557311854 ps | ||
| T339 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.2459225727 | Oct 12 02:31:59 AM UTC 24 | Oct 12 02:33:16 AM UTC 24 | 5996701721 ps | ||
| T340 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.2809588060 | Oct 12 02:32:14 AM UTC 24 | Oct 12 02:33:18 AM UTC 24 | 1482702198 ps | ||
| T341 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.489402517 | Oct 12 02:31:12 AM UTC 24 | Oct 12 02:33:19 AM UTC 24 | 13709475518 ps | ||
| T342 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2054985557 | Oct 12 02:30:43 AM UTC 24 | Oct 12 02:33:26 AM UTC 24 | 6686087717 ps | ||
| T343 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.3824604191 | Oct 12 02:31:39 AM UTC 24 | Oct 12 02:33:28 AM UTC 24 | 2118590958 ps | ||
| T344 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.2469619231 | Oct 12 02:31:30 AM UTC 24 | Oct 12 02:33:40 AM UTC 24 | 26586247086 ps | ||
| T345 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.250850493 | Oct 12 02:28:41 AM UTC 24 | Oct 12 02:33:52 AM UTC 24 | 15629398670 ps | ||
| T346 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3701634704 | Oct 12 02:30:09 AM UTC 24 | Oct 12 02:33:53 AM UTC 24 | 3445493999 ps | ||
| T347 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1403175223 | Oct 12 02:26:45 AM UTC 24 | Oct 12 02:34:01 AM UTC 24 | 27128547640 ps | ||
| T348 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.1931151907 | Oct 12 02:30:25 AM UTC 24 | Oct 12 02:34:14 AM UTC 24 | 74771163948 ps | ||
| T349 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.1765876713 | Oct 12 02:30:49 AM UTC 24 | Oct 12 02:34:17 AM UTC 24 | 12326799147 ps | ||
| T132 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.2362882937 | Oct 12 02:32:04 AM UTC 24 | Oct 12 02:34:19 AM UTC 24 | 3386183965 ps | ||
| T350 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.4019801696 | Oct 12 02:31:12 AM UTC 24 | Oct 12 02:34:19 AM UTC 24 | 26965136040 ps | ||
| T351 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.4015793192 | Oct 12 02:30:22 AM UTC 24 | Oct 12 02:34:20 AM UTC 24 | 6710925457 ps | ||
| T352 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.586194536 | Oct 12 02:30:32 AM UTC 24 | Oct 12 02:34:32 AM UTC 24 | 4364265986 ps | ||
| T353 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.937987181 | Oct 12 02:28:30 AM UTC 24 | Oct 12 02:34:37 AM UTC 24 | 6161528914 ps | ||
| T354 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.76104496 | Oct 12 02:29:35 AM UTC 24 | Oct 12 02:34:39 AM UTC 24 | 20573509946 ps | ||
| T355 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.47692275 | Oct 12 02:29:29 AM UTC 24 | Oct 12 02:34:47 AM UTC 24 | 7934692863 ps | ||
| T356 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.1708668688 | Oct 12 02:31:48 AM UTC 24 | Oct 12 02:34:48 AM UTC 24 | 3887854665 ps | ||
| T357 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.889485507 | Oct 12 02:29:00 AM UTC 24 | Oct 12 02:34:51 AM UTC 24 | 21665576854 ps | ||
| T358 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1742279113 | Oct 12 02:31:19 AM UTC 24 | Oct 12 02:34:59 AM UTC 24 | 9443572143 ps | ||
| T359 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.479041581 | Oct 12 02:31:46 AM UTC 24 | Oct 12 02:35:01 AM UTC 24 | 6907025357 ps | ||
| T360 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2647625331 | Oct 12 02:31:54 AM UTC 24 | Oct 12 02:35:06 AM UTC 24 | 2565401986 ps | ||
| T361 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.2841224533 | Oct 12 02:32:12 AM UTC 24 | Oct 12 02:35:10 AM UTC 24 | 7020020333 ps | ||
| T362 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3627159201 | Oct 12 02:31:02 AM UTC 24 | Oct 12 02:35:38 AM UTC 24 | 6011447651 ps | ||
| T363 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1718134251 | Oct 12 02:32:02 AM UTC 24 | Oct 12 02:35:39 AM UTC 24 | 3875006260 ps | ||
| T364 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1112307365 | Oct 12 02:31:35 AM UTC 24 | Oct 12 02:35:42 AM UTC 24 | 3821347333 ps | ||
| T365 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.2184487002 | Oct 12 02:30:53 AM UTC 24 | Oct 12 02:35:46 AM UTC 24 | 5318527578 ps | ||
| T366 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.173026623 | Oct 12 02:31:26 AM UTC 24 | Oct 12 02:36:33 AM UTC 24 | 10219089429 ps | ||
| T71 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2952420424 | Oct 12 12:44:48 AM UTC 24 | Oct 12 12:44:58 AM UTC 24 | 1067509469 ps | ||
| T72 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.304899325 | Oct 12 12:44:48 AM UTC 24 | Oct 12 12:44:59 AM UTC 24 | 1068333752 ps | ||
| T73 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1757019950 | Oct 12 12:44:48 AM UTC 24 | Oct 12 12:44:59 AM UTC 24 | 296927353 ps | ||
| T367 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2158798377 | Oct 12 12:44:48 AM UTC 24 | Oct 12 12:44:59 AM UTC 24 | 299882239 ps | ||
| T110 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2458935686 | Oct 12 12:44:48 AM UTC 24 | Oct 12 12:44:59 AM UTC 24 | 1026493283 ps | ||
| T77 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.4262449448 | Oct 12 12:44:49 AM UTC 24 | Oct 12 12:44:59 AM UTC 24 | 727169112 ps | ||
| T368 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3535898670 | Oct 12 12:44:48 AM UTC 24 | Oct 12 12:45:00 AM UTC 24 | 294396229 ps | ||
| T111 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.439856517 | Oct 12 12:44:48 AM UTC 24 | Oct 12 12:45:00 AM UTC 24 | 389877930 ps | ||
| T369 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.923885827 | Oct 12 12:44:49 AM UTC 24 | Oct 12 12:45:01 AM UTC 24 | 728290536 ps | ||
| T370 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1430248233 | Oct 12 12:44:48 AM UTC 24 | Oct 12 12:45:01 AM UTC 24 | 1163919192 ps | ||
| T371 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1291983280 | Oct 12 12:44:49 AM UTC 24 | Oct 12 12:45:01 AM UTC 24 | 294350968 ps | ||
| T372 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1470574664 | Oct 12 12:44:48 AM UTC 24 | Oct 12 12:45:02 AM UTC 24 | 589819710 ps | ||
| T373 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1969828561 | Oct 12 12:44:49 AM UTC 24 | Oct 12 12:45:02 AM UTC 24 | 1069866135 ps | ||
| T374 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_errors.192706438 | Oct 12 12:44:48 AM UTC 24 | Oct 12 12:45:02 AM UTC 24 | 286925485 ps | ||
| T78 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1485675464 | Oct 12 12:44:49 AM UTC 24 | Oct 12 12:45:02 AM UTC 24 | 210407053 ps | ||
| T79 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2507691093 | Oct 12 12:44:49 AM UTC 24 | Oct 12 12:45:02 AM UTC 24 | 726555840 ps | ||
| T375 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1126307526 | Oct 12 12:44:48 AM UTC 24 | Oct 12 12:45:02 AM UTC 24 | 2100319547 ps | ||
| T376 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2172832478 | Oct 12 12:44:49 AM UTC 24 | Oct 12 12:45:03 AM UTC 24 | 2356564627 ps | ||
| T80 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3007757583 | Oct 12 12:44:48 AM UTC 24 | Oct 12 12:45:03 AM UTC 24 | 546866847 ps | ||
| T377 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3522378814 | Oct 12 12:44:49 AM UTC 24 | Oct 12 12:45:03 AM UTC 24 | 2919734214 ps | ||
| T378 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2831113372 | Oct 12 12:44:48 AM UTC 24 | Oct 12 12:45:04 AM UTC 24 | 302463874 ps | ||
| T379 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2233213722 | Oct 12 12:44:48 AM UTC 24 | Oct 12 12:45:04 AM UTC 24 | 891560465 ps | ||
| T103 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1540319686 | Oct 12 12:44:49 AM UTC 24 | Oct 12 12:45:05 AM UTC 24 | 287992051 ps | ||
| T104 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2463208706 | Oct 12 12:44:48 AM UTC 24 | Oct 12 12:45:05 AM UTC 24 | 1059896972 ps | ||
| T112 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1340213068 | Oct 12 12:44:48 AM UTC 24 | Oct 12 12:45:05 AM UTC 24 | 456737961 ps | ||
| T380 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.320887267 | Oct 12 12:44:49 AM UTC 24 | Oct 12 12:45:06 AM UTC 24 | 1076610260 ps | ||
| T81 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.117540334 | Oct 12 12:44:49 AM UTC 24 | Oct 12 12:45:11 AM UTC 24 | 297848653 ps | ||
| T381 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2222732505 | Oct 12 12:45:05 AM UTC 24 | Oct 12 12:45:15 AM UTC 24 | 1869964328 ps | ||
| T82 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3507885447 | Oct 12 12:45:05 AM UTC 24 | Oct 12 12:45:16 AM UTC 24 | 552232937 ps | ||
| T382 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3562488842 | Oct 12 12:45:06 AM UTC 24 | Oct 12 12:45:16 AM UTC 24 | 699876601 ps | ||
| T105 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3505012670 | Oct 12 12:45:05 AM UTC 24 | Oct 12 12:45:17 AM UTC 24 | 287300728 ps | ||
| T383 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2164065143 | Oct 12 12:45:05 AM UTC 24 | Oct 12 12:45:17 AM UTC 24 | 210724164 ps | ||
| T384 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.4085753202 | Oct 12 12:45:05 AM UTC 24 | Oct 12 12:45:18 AM UTC 24 | 376957979 ps | ||
| T83 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3583718411 | Oct 12 12:45:08 AM UTC 24 | Oct 12 12:45:19 AM UTC 24 | 488684178 ps | ||
| T385 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3059068918 | Oct 12 12:45:06 AM UTC 24 | Oct 12 12:45:19 AM UTC 24 | 220728582 ps | ||
| T386 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1746601767 | Oct 12 12:44:33 AM UTC 24 | Oct 12 12:45:19 AM UTC 24 | 4116089304 ps | ||
| T387 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.856025923 | Oct 12 12:45:05 AM UTC 24 | Oct 12 12:45:19 AM UTC 24 | 1161949370 ps | ||
| T388 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3046321480 | Oct 12 12:45:05 AM UTC 24 | Oct 12 12:45:20 AM UTC 24 | 208851936 ps | ||
| T106 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1934407076 | Oct 12 12:45:06 AM UTC 24 | Oct 12 12:45:20 AM UTC 24 | 678589441 ps | ||
| T389 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3456380231 | Oct 12 12:45:05 AM UTC 24 | Oct 12 12:45:20 AM UTC 24 | 224998631 ps | ||
| T107 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2822142299 | Oct 12 12:45:06 AM UTC 24 | Oct 12 12:45:20 AM UTC 24 | 555674221 ps | ||
| T390 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.4122166967 | Oct 12 12:45:06 AM UTC 24 | Oct 12 12:45:21 AM UTC 24 | 4994243842 ps | ||
| T391 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2852829451 | Oct 12 12:45:05 AM UTC 24 | Oct 12 12:45:21 AM UTC 24 | 2276814540 ps | ||
| T108 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1049452360 | Oct 12 12:45:08 AM UTC 24 | Oct 12 12:45:21 AM UTC 24 | 208782133 ps | ||
| T392 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3358927601 | Oct 12 12:45:05 AM UTC 24 | Oct 12 12:45:22 AM UTC 24 | 406645783 ps | ||
| T393 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1388238777 | Oct 12 12:45:05 AM UTC 24 | Oct 12 12:45:23 AM UTC 24 | 212462497 ps | ||
| T394 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2123969176 | Oct 12 12:45:11 AM UTC 24 | Oct 12 12:45:26 AM UTC 24 | 552665991 ps | ||
| T395 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1483060191 | Oct 12 12:45:08 AM UTC 24 | Oct 12 12:45:27 AM UTC 24 | 1690073971 ps | ||
| T396 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3562769711 | Oct 12 12:45:05 AM UTC 24 | Oct 12 12:45:28 AM UTC 24 | 302826080 ps | ||
| T84 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.618710163 | Oct 12 12:45:05 AM UTC 24 | Oct 12 12:45:29 AM UTC 24 | 1067757411 ps | ||
| T397 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3512419637 | Oct 12 12:45:15 AM UTC 24 | Oct 12 12:45:29 AM UTC 24 | 571149300 ps | ||
| T398 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2100081213 | Oct 12 12:45:16 AM UTC 24 | Oct 12 12:45:30 AM UTC 24 | 376791193 ps | ||
| T109 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1288998318 | Oct 12 12:45:18 AM UTC 24 | Oct 12 12:45:31 AM UTC 24 | 1067791724 ps | ||
| T399 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.296757629 | Oct 12 12:45:19 AM UTC 24 | Oct 12 12:45:31 AM UTC 24 | 723694557 ps | ||
| T400 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2231712699 | Oct 12 12:45:22 AM UTC 24 | Oct 12 12:45:33 AM UTC 24 | 1165871198 ps | ||
| T401 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_rw.232800340 | Oct 12 12:45:20 AM UTC 24 | Oct 12 12:45:33 AM UTC 24 | 524000290 ps | ||
| T402 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.447258045 | Oct 12 12:45:20 AM UTC 24 | Oct 12 12:45:34 AM UTC 24 | 218295212 ps | ||
| T403 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2526478483 | Oct 12 12:45:21 AM UTC 24 | Oct 12 12:45:35 AM UTC 24 | 725622716 ps | ||
| T404 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3574907774 | Oct 12 12:45:20 AM UTC 24 | Oct 12 12:45:35 AM UTC 24 | 212437330 ps | ||
| T405 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1078451486 | Oct 12 12:45:21 AM UTC 24 | Oct 12 12:45:36 AM UTC 24 | 1305526850 ps | ||
| T406 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3169469631 | Oct 12 12:45:21 AM UTC 24 | Oct 12 12:45:39 AM UTC 24 | 307868598 ps | ||
| T407 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_errors.357653436 | Oct 12 12:45:25 AM UTC 24 | Oct 12 12:45:39 AM UTC 24 | 212664738 ps | ||
| T408 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3338618829 | Oct 12 12:45:29 AM UTC 24 | Oct 12 12:45:40 AM UTC 24 | 2786621824 ps | ||
| T409 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1646371984 | Oct 12 12:45:22 AM UTC 24 | Oct 12 12:45:40 AM UTC 24 | 573413404 ps | ||
| T410 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_rw.4134056403 | Oct 12 12:45:29 AM UTC 24 | Oct 12 12:45:42 AM UTC 24 | 1031907126 ps | ||
| T89 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1213096564 | Oct 12 12:44:49 AM UTC 24 | Oct 12 12:45:43 AM UTC 24 | 4504919107 ps | ||
| T411 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.108999343 | Oct 12 12:45:30 AM UTC 24 | Oct 12 12:45:46 AM UTC 24 | 304463204 ps | ||
| T412 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.542211103 | Oct 12 12:45:37 AM UTC 24 | Oct 12 12:45:47 AM UTC 24 | 1539577256 ps | ||
| T413 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3934805555 | Oct 12 12:45:36 AM UTC 24 | Oct 12 12:45:47 AM UTC 24 | 215921555 ps | ||
| T414 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2840879202 | Oct 12 12:45:36 AM UTC 24 | Oct 12 12:45:47 AM UTC 24 | 205673804 ps | ||
| T90 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3520200274 | Oct 12 12:45:36 AM UTC 24 | Oct 12 12:45:51 AM UTC 24 | 541193469 ps | ||
| T415 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3993833910 | Oct 12 12:45:36 AM UTC 24 | Oct 12 12:45:51 AM UTC 24 | 391200928 ps | ||
| T133 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.991576865 | Oct 12 12:45:06 AM UTC 24 | Oct 12 12:45:52 AM UTC 24 | 2071521876 ps | ||
| T416 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1845858032 | Oct 12 12:45:35 AM UTC 24 | Oct 12 12:45:53 AM UTC 24 | 205704816 ps | ||
| T417 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2772839676 | Oct 12 12:45:41 AM UTC 24 | Oct 12 12:45:55 AM UTC 24 | 384129143 ps | ||
| T418 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_errors.593106565 | Oct 12 12:45:36 AM UTC 24 | Oct 12 12:45:55 AM UTC 24 | 1027144777 ps | ||
| T91 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1747711576 | Oct 12 12:44:48 AM UTC 24 | Oct 12 12:45:56 AM UTC 24 | 2820611819 ps | ||
| T419 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.4178531293 | Oct 12 12:45:39 AM UTC 24 | Oct 12 12:45:55 AM UTC 24 | 1030846584 ps | ||
| T420 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_rw.778837606 | Oct 12 12:45:43 AM UTC 24 | Oct 12 12:45:56 AM UTC 24 | 1026609065 ps | ||
| T421 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3958995734 | Oct 12 12:45:47 AM UTC 24 | Oct 12 12:46:02 AM UTC 24 | 304580157 ps | ||
| T422 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3928202250 | Oct 12 12:45:51 AM UTC 24 | Oct 12 12:46:04 AM UTC 24 | 377140663 ps | ||
| T423 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1937458879 | Oct 12 12:45:53 AM UTC 24 | Oct 12 12:46:05 AM UTC 24 | 793772486 ps | ||
| T424 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2065829222 | Oct 12 12:45:44 AM UTC 24 | Oct 12 12:46:05 AM UTC 24 | 4344069108 ps | ||
| T92 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3213109418 | Oct 12 12:45:03 AM UTC 24 | Oct 12 12:46:06 AM UTC 24 | 5479012720 ps | ||
| T425 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3993135090 | Oct 12 12:45:48 AM UTC 24 | Oct 12 12:46:06 AM UTC 24 | 589749505 ps | ||
| T67 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2415683069 | Oct 12 12:44:48 AM UTC 24 | Oct 12 12:46:07 AM UTC 24 | 951890440 ps | ||
| T93 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3463589074 | Oct 12 12:45:19 AM UTC 24 | Oct 12 12:46:07 AM UTC 24 | 1993707803 ps | ||
| T426 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2270962482 | Oct 12 12:45:57 AM UTC 24 | Oct 12 12:46:07 AM UTC 24 | 327836141 ps | ||
| T427 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1615264067 | Oct 12 12:45:57 AM UTC 24 | Oct 12 12:46:09 AM UTC 24 | 212185006 ps | ||
| T428 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.327964649 | Oct 12 12:45:51 AM UTC 24 | Oct 12 12:46:11 AM UTC 24 | 219222601 ps | ||
| T99 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3123484636 | Oct 12 12:45:56 AM UTC 24 | Oct 12 12:46:11 AM UTC 24 | 1074136620 ps | ||
| T429 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3490395820 | Oct 12 12:45:55 AM UTC 24 | Oct 12 12:46:11 AM UTC 24 | 212590062 ps | ||
| T100 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3220740813 | Oct 12 12:45:05 AM UTC 24 | Oct 12 12:46:18 AM UTC 24 | 6374656855 ps | ||
| T430 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.162084918 | Oct 12 12:46:09 AM UTC 24 | Oct 12 12:46:20 AM UTC 24 | 955433359 ps | ||
| T94 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1822385286 | Oct 12 12:45:36 AM UTC 24 | Oct 12 12:46:22 AM UTC 24 | 1055663358 ps | ||
| T431 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2130522794 | Oct 12 12:46:10 AM UTC 24 | Oct 12 12:46:22 AM UTC 24 | 727356934 ps | ||
| T432 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2818897308 | Oct 12 12:46:09 AM UTC 24 | Oct 12 12:46:24 AM UTC 24 | 311772411 ps | ||
| T433 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2020619929 | Oct 12 12:46:10 AM UTC 24 | Oct 12 12:46:25 AM UTC 24 | 365223424 ps | ||
| T434 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2217386242 | Oct 12 12:46:09 AM UTC 24 | Oct 12 12:46:25 AM UTC 24 | 1164494646 ps | ||
| T435 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1588517578 | Oct 12 12:45:21 AM UTC 24 | Oct 12 12:46:25 AM UTC 24 | 3953246370 ps | ||
| T436 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3242764459 | Oct 12 12:46:12 AM UTC 24 | Oct 12 12:46:26 AM UTC 24 | 297157395 ps | ||
| T68 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3110518317 | Oct 12 12:45:05 AM UTC 24 | Oct 12 12:46:28 AM UTC 24 | 1046379086 ps | ||
| T437 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2278364179 | Oct 12 12:45:30 AM UTC 24 | Oct 12 12:46:31 AM UTC 24 | 1342994602 ps | ||
| T438 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3691964579 | Oct 12 12:46:09 AM UTC 24 | Oct 12 12:46:31 AM UTC 24 | 534554919 ps | ||
| T439 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2412438975 | Oct 12 12:46:20 AM UTC 24 | Oct 12 12:46:32 AM UTC 24 | 205766287 ps | ||
| T440 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3978860852 | Oct 12 12:46:12 AM UTC 24 | Oct 12 12:46:32 AM UTC 24 | 342304336 ps | ||
| T441 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1674949873 | Oct 12 12:46:10 AM UTC 24 | Oct 12 12:46:33 AM UTC 24 | 290489432 ps | ||
| T442 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1158577563 | Oct 12 12:46:22 AM UTC 24 | Oct 12 12:46:40 AM UTC 24 | 1080190505 ps | ||
| T443 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2820827884 | Oct 12 12:46:23 AM UTC 24 | Oct 12 12:46:40 AM UTC 24 | 1166591954 ps | ||
| T101 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2162098440 | Oct 12 12:46:25 AM UTC 24 | Oct 12 12:46:41 AM UTC 24 | 293341232 ps | ||
| T102 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.231174691 | Oct 12 12:45:14 AM UTC 24 | Oct 12 12:46:42 AM UTC 24 | 6046284690 ps | ||
| T444 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1032408858 | Oct 12 12:46:27 AM UTC 24 | Oct 12 12:46:42 AM UTC 24 | 212390004 ps | ||
| T445 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.73990192 | Oct 12 12:46:34 AM UTC 24 | Oct 12 12:46:43 AM UTC 24 | 306264259 ps | ||
| T95 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_rw.4011631710 | Oct 12 12:46:33 AM UTC 24 | Oct 12 12:46:44 AM UTC 24 | 2098285017 ps | ||
| T446 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1623989870 | Oct 12 12:45:39 AM UTC 24 | Oct 12 12:46:47 AM UTC 24 | 6405504082 ps | ||
| T447 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1673846509 | Oct 12 12:46:25 AM UTC 24 | Oct 12 12:46:48 AM UTC 24 | 554970247 ps | ||
| T448 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_errors.375703297 | Oct 12 12:46:32 AM UTC 24 | Oct 12 12:46:51 AM UTC 24 | 536208066 ps | ||
| T449 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3759951485 | Oct 12 12:46:30 AM UTC 24 | Oct 12 12:46:51 AM UTC 24 | 1095784914 ps | ||
| T96 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3034358767 | Oct 12 12:45:23 AM UTC 24 | Oct 12 12:46:55 AM UTC 24 | 21321746274 ps | ||
| T450 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1733115009 | Oct 12 12:46:08 AM UTC 24 | Oct 12 12:46:56 AM UTC 24 | 2102836804 ps | ||
| T451 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1035373457 | Oct 12 12:45:48 AM UTC 24 | Oct 12 12:47:03 AM UTC 24 | 1625839898 ps | ||
| T69 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1523567646 | Oct 12 12:45:05 AM UTC 24 | Oct 12 12:47:04 AM UTC 24 | 402998923 ps | ||
| T452 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1789136060 | Oct 12 12:46:50 AM UTC 24 | Oct 12 12:47:05 AM UTC 24 | 664196362 ps | ||
| T117 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1802651958 | Oct 12 12:45:35 AM UTC 24 | Oct 12 12:47:05 AM UTC 24 | 965612273 ps | ||
| T453 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3448965730 | Oct 12 12:45:53 AM UTC 24 | Oct 12 12:47:09 AM UTC 24 | 6377116597 ps | ||
| T119 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.327808752 | Oct 12 12:45:36 AM UTC 24 | Oct 12 12:47:09 AM UTC 24 | 522493492 ps | ||
| T127 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2713684403 | Oct 12 12:45:41 AM UTC 24 | Oct 12 12:47:12 AM UTC 24 | 345628299 ps | ||
| T454 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.4229222575 | Oct 12 12:46:12 AM UTC 24 | Oct 12 12:47:12 AM UTC 24 | 2106246516 ps | ||
| T455 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1782221029 | Oct 12 12:44:48 AM UTC 24 | Oct 12 12:47:26 AM UTC 24 | 734902792 ps | ||
| T97 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.935091970 | Oct 12 12:46:10 AM UTC 24 | Oct 12 12:47:26 AM UTC 24 | 11468708087 ps | ||
| T98 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.4027576199 | Oct 12 12:46:32 AM UTC 24 | Oct 12 12:47:28 AM UTC 24 | 2488414321 ps | ||
| T456 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2155988912 | Oct 12 12:46:24 AM UTC 24 | Oct 12 12:47:29 AM UTC 24 | 1116647613 ps | ||
| T118 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3043552508 | Oct 12 12:44:49 AM UTC 24 | Oct 12 12:47:39 AM UTC 24 | 377681306 ps | ||
| T121 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.62250661 | Oct 12 12:45:20 AM UTC 24 | Oct 12 12:47:58 AM UTC 24 | 581990897 ps | ||
| T124 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1199936468 | Oct 12 12:46:19 AM UTC 24 | Oct 12 12:48:00 AM UTC 24 | 351689911 ps | ||
| T120 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3987215260 | Oct 12 12:45:21 AM UTC 24 | Oct 12 12:48:17 AM UTC 24 | 1216197265 ps | ||
| T457 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3582273283 | Oct 12 12:45:16 AM UTC 24 | Oct 12 12:48:22 AM UTC 24 | 434105604 ps | ||
| T128 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2070909288 | Oct 12 12:45:27 AM UTC 24 | Oct 12 12:48:28 AM UTC 24 | 837919168 ps | ||
| T458 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2199099279 | Oct 12 12:45:08 AM UTC 24 | Oct 12 12:48:29 AM UTC 24 | 329646639 ps | ||
| T129 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3323208354 | Oct 12 12:46:10 AM UTC 24 | Oct 12 12:48:35 AM UTC 24 | 1672210370 ps | ||
| T125 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2202844972 | Oct 12 12:45:55 AM UTC 24 | Oct 12 12:48:43 AM UTC 24 | 498678057 ps | ||
| T122 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.332364673 | Oct 12 12:46:09 AM UTC 24 | Oct 12 12:48:53 AM UTC 24 | 1627217105 ps | ||
| T130 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2088871442 | Oct 12 12:45:48 AM UTC 24 | Oct 12 12:48:56 AM UTC 24 | 463967276 ps | ||
| T123 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.66251535 | Oct 12 12:46:33 AM UTC 24 | Oct 12 12:49:15 AM UTC 24 | 1135830690 ps | ||
| T126 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2426293506 | Oct 12 12:46:25 AM UTC 24 | Oct 12 12:49:19 AM UTC 24 | 1216917975 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all.2455817625 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 425225368 ps |
| CPU time | 29.85 seconds |
| Started | Oct 12 02:22:37 AM UTC 24 |
| Finished | Oct 12 02:23:08 AM UTC 24 |
| Peak memory | 230588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245581762 5 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all.2455817625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.65822563 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 7809217736 ps |
| CPU time | 102.2 seconds |
| Started | Oct 12 02:23:09 AM UTC 24 |
| Finished | Oct 12 02:24:54 AM UTC 24 |
| Peak memory | 237168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=65822563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.65822563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1867988382 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 2529221798 ps |
| CPU time | 171.97 seconds |
| Started | Oct 12 02:25:03 AM UTC 24 |
| Finished | Oct 12 02:27:58 AM UTC 24 |
| Peak memory | 260412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1867988382 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_corrupt_sig_fatal_chk.1867988382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_kmac_err_chk.2204266141 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 1414584870 ps |
| CPU time | 19.98 seconds |
| Started | Oct 12 02:23:25 AM UTC 24 |
| Finished | Oct 12 02:23:46 AM UTC 24 |
| Peak memory | 230328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204266141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.2204266141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.2786064339 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 3950562805 ps |
| CPU time | 66.19 seconds |
| Started | Oct 12 02:22:39 AM UTC 24 |
| Finished | Oct 12 02:23:47 AM UTC 24 |
| Peak memory | 234936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2786064339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.rom_ctrl_stress_all_with_rand_reset.2786064339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2415683069 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 951890440 ps |
| CPU time | 77.1 seconds |
| Started | Oct 12 12:44:48 AM UTC 24 |
| Finished | Oct 12 12:46:07 AM UTC 24 |
| Peak memory | 221928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2415683069 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_intg_err.2415683069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all.1886497342 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 804137960 ps |
| CPU time | 40.28 seconds |
| Started | Oct 12 02:22:38 AM UTC 24 |
| Finished | Oct 12 02:23:20 AM UTC 24 |
| Peak memory | 230812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=188649734 2 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all.1886497342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1247117905 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 28353142878 ps |
| CPU time | 199.24 seconds |
| Started | Oct 12 02:22:38 AM UTC 24 |
| Finished | Oct 12 02:26:00 AM UTC 24 |
| Peak memory | 261144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247117905 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_corrupt_sig_fatal_chk.1247117905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_sec_cm.4289540011 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 375732184 ps |
| CPU time | 109.48 seconds |
| Started | Oct 12 02:23:12 AM UTC 24 |
| Finished | Oct 12 02:25:04 AM UTC 24 |
| Peak memory | 261340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289540011 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.4289540011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3987215260 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 1216197265 ps |
| CPU time | 172.26 seconds |
| Started | Oct 12 12:45:21 AM UTC 24 |
| Finished | Oct 12 12:48:17 AM UTC 24 |
| Peak memory | 224164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3987215260 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_intg_err.3987215260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3213109418 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 5479012720 ps |
| CPU time | 60.74 seconds |
| Started | Oct 12 12:45:03 AM UTC 24 |
| Finished | Oct 12 12:46:06 AM UTC 24 |
| Peak memory | 224308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213109418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_passthru_mem_tl_intg_err.3213109418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_alert_test.1574948882 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 727470649 ps |
| CPU time | 12.48 seconds |
| Started | Oct 12 02:22:58 AM UTC 24 |
| Finished | Oct 12 02:23:12 AM UTC 24 |
| Peak memory | 229864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574948882 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.1574948882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_kmac_err_chk.1367714089 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 1415218903 ps |
| CPU time | 29.42 seconds |
| Started | Oct 12 02:22:53 AM UTC 24 |
| Finished | Oct 12 02:23:24 AM UTC 24 |
| Peak memory | 230240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367714089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.1367714089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_max_throughput_chk.728543046 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 1070392590 ps |
| CPU time | 18.94 seconds |
| Started | Oct 12 02:25:42 AM UTC 24 |
| Finished | Oct 12 02:26:02 AM UTC 24 |
| Peak memory | 230696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=728543046 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.728543046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1485675464 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 210407053 ps |
| CPU time | 11.93 seconds |
| Started | Oct 12 12:44:49 AM UTC 24 |
| Finished | Oct 12 12:45:02 AM UTC 24 |
| Peak memory | 222088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485675464 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_same_csr_outstanding.1485675464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_kmac_err_chk.2192169008 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 1071539230 ps |
| CPU time | 32.11 seconds |
| Started | Oct 12 02:26:23 AM UTC 24 |
| Finished | Oct 12 02:26:56 AM UTC 24 |
| Peak memory | 229944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192169008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.2192169008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2202844972 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 498678057 ps |
| CPU time | 165.09 seconds |
| Started | Oct 12 12:45:55 AM UTC 24 |
| Finished | Oct 12 12:48:43 AM UTC 24 |
| Peak memory | 222120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2202844972 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_intg_err.2202844972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.66251535 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 1135830690 ps |
| CPU time | 159.47 seconds |
| Started | Oct 12 12:46:33 AM UTC 24 |
| Finished | Oct 12 12:49:15 AM UTC 24 |
| Peak memory | 224428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=66251535 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_intg_err.66251535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all.1731215048 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 575033023 ps |
| CPU time | 31.59 seconds |
| Started | Oct 12 02:22:39 AM UTC 24 |
| Finished | Oct 12 02:23:13 AM UTC 24 |
| Peak memory | 230684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=173121504 8 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all.1731215048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1747711576 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 2820611819 ps |
| CPU time | 65.67 seconds |
| Started | Oct 12 12:44:48 AM UTC 24 |
| Finished | Oct 12 12:45:56 AM UTC 24 |
| Peak memory | 224308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747711576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_passthru_mem_tl_intg_err.1747711576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2952420424 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 1067509469 ps |
| CPU time | 8.69 seconds |
| Started | Oct 12 12:44:48 AM UTC 24 |
| Finished | Oct 12 12:44:58 AM UTC 24 |
| Peak memory | 219804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952420424 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_aliasing.2952420424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2158798377 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 299882239 ps |
| CPU time | 9.69 seconds |
| Started | Oct 12 12:44:48 AM UTC 24 |
| Finished | Oct 12 12:44:59 AM UTC 24 |
| Peak memory | 219600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2158798377 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_bash.2158798377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.439856517 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 389877930 ps |
| CPU time | 11.15 seconds |
| Started | Oct 12 12:44:48 AM UTC 24 |
| Finished | Oct 12 12:45:00 AM UTC 24 |
| Peak memory | 220068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=439856517 -assert nopostproc +UVM_TE STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_reset.439856517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2831113372 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 302463874 ps |
| CPU time | 14.13 seconds |
| Started | Oct 12 12:44:48 AM UTC 24 |
| Finished | Oct 12 12:45:04 AM UTC 24 |
| Peak memory | 227560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2831113372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.r om_ctrl_csr_mem_rw_with_rand_reset.2831113372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1757019950 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 296927353 ps |
| CPU time | 9.58 seconds |
| Started | Oct 12 12:44:48 AM UTC 24 |
| Finished | Oct 12 12:44:59 AM UTC 24 |
| Peak memory | 220064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757019950 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.1757019950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1126307526 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 2100319547 ps |
| CPU time | 12.74 seconds |
| Started | Oct 12 12:44:48 AM UTC 24 |
| Finished | Oct 12 12:45:02 AM UTC 24 |
| Peak memory | 220004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126307526 -assert nopostp roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_partial_access.1126307526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1470574664 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 589819710 ps |
| CPU time | 12.42 seconds |
| Started | Oct 12 12:44:48 AM UTC 24 |
| Finished | Oct 12 12:45:02 AM UTC 24 |
| Peak memory | 220324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1470574664 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.1470574664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1746601767 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 4116089304 ps |
| CPU time | 44.76 seconds |
| Started | Oct 12 12:44:33 AM UTC 24 |
| Finished | Oct 12 12:45:19 AM UTC 24 |
| Peak memory | 224564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746601767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_passthru_mem_tl_intg_err.1746601767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2463208706 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 1059896972 ps |
| CPU time | 15.64 seconds |
| Started | Oct 12 12:44:48 AM UTC 24 |
| Finished | Oct 12 12:45:05 AM UTC 24 |
| Peak memory | 222180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463208706 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_same_csr_outstanding.2463208706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2233213722 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 891560465 ps |
| CPU time | 15.27 seconds |
| Started | Oct 12 12:44:48 AM UTC 24 |
| Finished | Oct 12 12:45:04 AM UTC 24 |
| Peak memory | 226476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233213722 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.2233213722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1782221029 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 734902792 ps |
| CPU time | 155.41 seconds |
| Started | Oct 12 12:44:48 AM UTC 24 |
| Finished | Oct 12 12:47:26 AM UTC 24 |
| Peak memory | 224164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1782221029 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_intg_err.1782221029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2458935686 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 1026493283 ps |
| CPU time | 9.39 seconds |
| Started | Oct 12 12:44:48 AM UTC 24 |
| Finished | Oct 12 12:44:59 AM UTC 24 |
| Peak memory | 220288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2458935686 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_aliasing.2458935686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.304899325 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 1068333752 ps |
| CPU time | 9.01 seconds |
| Started | Oct 12 12:44:48 AM UTC 24 |
| Finished | Oct 12 12:44:59 AM UTC 24 |
| Peak memory | 220324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304899325 -assert nopostproc +UVM_TE STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_bash.304899325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1340213068 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 456737961 ps |
| CPU time | 15.7 seconds |
| Started | Oct 12 12:44:48 AM UTC 24 |
| Finished | Oct 12 12:45:05 AM UTC 24 |
| Peak memory | 220188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1340213068 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_reset.1340213068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3522378814 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 2919734214 ps |
| CPU time | 13.62 seconds |
| Started | Oct 12 12:44:49 AM UTC 24 |
| Finished | Oct 12 12:45:03 AM UTC 24 |
| Peak memory | 227624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3522378814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.r om_ctrl_csr_mem_rw_with_rand_reset.3522378814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3007757583 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 546866847 ps |
| CPU time | 13.56 seconds |
| Started | Oct 12 12:44:48 AM UTC 24 |
| Finished | Oct 12 12:45:03 AM UTC 24 |
| Peak memory | 220320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3007757583 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.3007757583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1430248233 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 1163919192 ps |
| CPU time | 11.5 seconds |
| Started | Oct 12 12:44:48 AM UTC 24 |
| Finished | Oct 12 12:45:01 AM UTC 24 |
| Peak memory | 219672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430248233 -assert nopostp roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_partial_access.1430248233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3535898670 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 294396229 ps |
| CPU time | 10.63 seconds |
| Started | Oct 12 12:44:48 AM UTC 24 |
| Finished | Oct 12 12:45:00 AM UTC 24 |
| Peak memory | 220004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3535898670 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.3535898670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_errors.192706438 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 286925485 ps |
| CPU time | 12.27 seconds |
| Started | Oct 12 12:44:48 AM UTC 24 |
| Finished | Oct 12 12:45:02 AM UTC 24 |
| Peak memory | 226292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192706438 -assert nopostproc +UVM_TESTNAME=ro m_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.192706438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3934805555 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 215921555 ps |
| CPU time | 10.08 seconds |
| Started | Oct 12 12:45:36 AM UTC 24 |
| Finished | Oct 12 12:45:47 AM UTC 24 |
| Peak memory | 227492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3934805555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10. rom_ctrl_csr_mem_rw_with_rand_reset.3934805555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3520200274 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 541193469 ps |
| CPU time | 13.51 seconds |
| Started | Oct 12 12:45:36 AM UTC 24 |
| Finished | Oct 12 12:45:51 AM UTC 24 |
| Peak memory | 220128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520200274 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.3520200274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2278364179 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 1342994602 ps |
| CPU time | 59.38 seconds |
| Started | Oct 12 12:45:30 AM UTC 24 |
| Finished | Oct 12 12:46:31 AM UTC 24 |
| Peak memory | 224440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278364179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_passthru_mem_tl_intg_err.2278364179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2840879202 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 205673804 ps |
| CPU time | 10.25 seconds |
| Started | Oct 12 12:45:36 AM UTC 24 |
| Finished | Oct 12 12:45:47 AM UTC 24 |
| Peak memory | 220068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840879202 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_same_csr_outstanding.2840879202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1845858032 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 205704816 ps |
| CPU time | 16.5 seconds |
| Started | Oct 12 12:45:35 AM UTC 24 |
| Finished | Oct 12 12:45:53 AM UTC 24 |
| Peak memory | 226620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845858032 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.1845858032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1802651958 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 965612273 ps |
| CPU time | 88.21 seconds |
| Started | Oct 12 12:45:35 AM UTC 24 |
| Finished | Oct 12 12:47:05 AM UTC 24 |
| Peak memory | 224364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802651958 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_intg_err.1802651958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.4178531293 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 1030846584 ps |
| CPU time | 14.34 seconds |
| Started | Oct 12 12:45:39 AM UTC 24 |
| Finished | Oct 12 12:45:55 AM UTC 24 |
| Peak memory | 224196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=4178531293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11. rom_ctrl_csr_mem_rw_with_rand_reset.4178531293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3993833910 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 391200928 ps |
| CPU time | 13.23 seconds |
| Started | Oct 12 12:45:36 AM UTC 24 |
| Finished | Oct 12 12:45:51 AM UTC 24 |
| Peak memory | 220064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993833910 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.3993833910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1822385286 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 1055663358 ps |
| CPU time | 44.18 seconds |
| Started | Oct 12 12:45:36 AM UTC 24 |
| Finished | Oct 12 12:46:22 AM UTC 24 |
| Peak memory | 224312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1822385286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_passthru_mem_tl_intg_err.1822385286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.542211103 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 1539577256 ps |
| CPU time | 8.43 seconds |
| Started | Oct 12 12:45:37 AM UTC 24 |
| Finished | Oct 12 12:45:47 AM UTC 24 |
| Peak memory | 220392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=542211103 -assert nopost proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_same_csr_outstanding.542211103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_errors.593106565 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 1027144777 ps |
| CPU time | 17.67 seconds |
| Started | Oct 12 12:45:36 AM UTC 24 |
| Finished | Oct 12 12:45:55 AM UTC 24 |
| Peak memory | 227324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593106565 -assert nopostproc +UVM_TESTNAME=ro m_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.593106565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.327808752 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 522493492 ps |
| CPU time | 90.82 seconds |
| Started | Oct 12 12:45:36 AM UTC 24 |
| Finished | Oct 12 12:47:09 AM UTC 24 |
| Peak memory | 227504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327808752 -assert nopostproc +UVM _TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_intg_err.327808752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3958995734 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 304580157 ps |
| CPU time | 13.72 seconds |
| Started | Oct 12 12:45:47 AM UTC 24 |
| Finished | Oct 12 12:46:02 AM UTC 24 |
| Peak memory | 226328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3958995734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12. rom_ctrl_csr_mem_rw_with_rand_reset.3958995734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_rw.778837606 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 1026609065 ps |
| CPU time | 12.14 seconds |
| Started | Oct 12 12:45:43 AM UTC 24 |
| Finished | Oct 12 12:45:56 AM UTC 24 |
| Peak memory | 220056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778837606 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.778837606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1623989870 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 6405504082 ps |
| CPU time | 65.78 seconds |
| Started | Oct 12 12:45:39 AM UTC 24 |
| Finished | Oct 12 12:46:47 AM UTC 24 |
| Peak memory | 224072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623989870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_passthru_mem_tl_intg_err.1623989870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2065829222 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 4344069108 ps |
| CPU time | 20.29 seconds |
| Started | Oct 12 12:45:44 AM UTC 24 |
| Finished | Oct 12 12:46:05 AM UTC 24 |
| Peak memory | 222244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065829222 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_same_csr_outstanding.2065829222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2772839676 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 384129143 ps |
| CPU time | 12.81 seconds |
| Started | Oct 12 12:45:41 AM UTC 24 |
| Finished | Oct 12 12:45:55 AM UTC 24 |
| Peak memory | 226300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772839676 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.2772839676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2713684403 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 345628299 ps |
| CPU time | 89.63 seconds |
| Started | Oct 12 12:45:41 AM UTC 24 |
| Finished | Oct 12 12:47:12 AM UTC 24 |
| Peak memory | 224172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713684403 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_intg_err.2713684403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1937458879 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 793772486 ps |
| CPU time | 10.8 seconds |
| Started | Oct 12 12:45:53 AM UTC 24 |
| Finished | Oct 12 12:46:05 AM UTC 24 |
| Peak memory | 227748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1937458879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13. rom_ctrl_csr_mem_rw_with_rand_reset.1937458879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3928202250 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 377140663 ps |
| CPU time | 12.17 seconds |
| Started | Oct 12 12:45:51 AM UTC 24 |
| Finished | Oct 12 12:46:04 AM UTC 24 |
| Peak memory | 220192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928202250 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.3928202250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1035373457 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 1625839898 ps |
| CPU time | 73.15 seconds |
| Started | Oct 12 12:45:48 AM UTC 24 |
| Finished | Oct 12 12:47:03 AM UTC 24 |
| Peak memory | 224440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035373457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_passthru_mem_tl_intg_err.1035373457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.327964649 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 219222601 ps |
| CPU time | 18.24 seconds |
| Started | Oct 12 12:45:51 AM UTC 24 |
| Finished | Oct 12 12:46:11 AM UTC 24 |
| Peak memory | 222120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327964649 -assert nopost proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_same_csr_outstanding.327964649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3993135090 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 589749505 ps |
| CPU time | 16.8 seconds |
| Started | Oct 12 12:45:48 AM UTC 24 |
| Finished | Oct 12 12:46:06 AM UTC 24 |
| Peak memory | 227104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993135090 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.3993135090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2088871442 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 463967276 ps |
| CPU time | 185.26 seconds |
| Started | Oct 12 12:45:48 AM UTC 24 |
| Finished | Oct 12 12:48:56 AM UTC 24 |
| Peak memory | 227444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088871442 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_intg_err.2088871442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1615264067 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 212185006 ps |
| CPU time | 11.08 seconds |
| Started | Oct 12 12:45:57 AM UTC 24 |
| Finished | Oct 12 12:46:09 AM UTC 24 |
| Peak memory | 227492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1615264067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14. rom_ctrl_csr_mem_rw_with_rand_reset.1615264067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3123484636 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 1074136620 ps |
| CPU time | 14.33 seconds |
| Started | Oct 12 12:45:56 AM UTC 24 |
| Finished | Oct 12 12:46:11 AM UTC 24 |
| Peak memory | 220064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3123484636 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.3123484636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3448965730 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 6377116597 ps |
| CPU time | 73.66 seconds |
| Started | Oct 12 12:45:53 AM UTC 24 |
| Finished | Oct 12 12:47:09 AM UTC 24 |
| Peak memory | 226360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448965730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_passthru_mem_tl_intg_err.3448965730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2270962482 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 327836141 ps |
| CPU time | 9.61 seconds |
| Started | Oct 12 12:45:57 AM UTC 24 |
| Finished | Oct 12 12:46:07 AM UTC 24 |
| Peak memory | 220324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270962482 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_same_csr_outstanding.2270962482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3490395820 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 212590062 ps |
| CPU time | 14.59 seconds |
| Started | Oct 12 12:45:55 AM UTC 24 |
| Finished | Oct 12 12:46:11 AM UTC 24 |
| Peak memory | 226300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490395820 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.3490395820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2818897308 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 311772411 ps |
| CPU time | 12.95 seconds |
| Started | Oct 12 12:46:09 AM UTC 24 |
| Finished | Oct 12 12:46:24 AM UTC 24 |
| Peak memory | 224216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2818897308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15. rom_ctrl_csr_mem_rw_with_rand_reset.2818897308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2217386242 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 1164494646 ps |
| CPU time | 14.02 seconds |
| Started | Oct 12 12:46:09 AM UTC 24 |
| Finished | Oct 12 12:46:25 AM UTC 24 |
| Peak memory | 220060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217386242 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.2217386242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1733115009 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 2102836804 ps |
| CPU time | 46.7 seconds |
| Started | Oct 12 12:46:08 AM UTC 24 |
| Finished | Oct 12 12:46:56 AM UTC 24 |
| Peak memory | 224440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733115009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_passthru_mem_tl_intg_err.1733115009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.162084918 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 955433359 ps |
| CPU time | 9.2 seconds |
| Started | Oct 12 12:46:09 AM UTC 24 |
| Finished | Oct 12 12:46:20 AM UTC 24 |
| Peak memory | 220328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162084918 -assert nopost proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_same_csr_outstanding.162084918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3691964579 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 534554919 ps |
| CPU time | 20.67 seconds |
| Started | Oct 12 12:46:09 AM UTC 24 |
| Finished | Oct 12 12:46:31 AM UTC 24 |
| Peak memory | 226556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691964579 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.3691964579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.332364673 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 1627217105 ps |
| CPU time | 161.37 seconds |
| Started | Oct 12 12:46:09 AM UTC 24 |
| Finished | Oct 12 12:48:53 AM UTC 24 |
| Peak memory | 224164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332364673 -assert nopostproc +UVM _TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_intg_err.332364673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3242764459 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 297157395 ps |
| CPU time | 12.83 seconds |
| Started | Oct 12 12:46:12 AM UTC 24 |
| Finished | Oct 12 12:46:26 AM UTC 24 |
| Peak memory | 226644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3242764459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16. rom_ctrl_csr_mem_rw_with_rand_reset.3242764459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2020619929 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 365223424 ps |
| CPU time | 13.66 seconds |
| Started | Oct 12 12:46:10 AM UTC 24 |
| Finished | Oct 12 12:46:25 AM UTC 24 |
| Peak memory | 220064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2020619929 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.2020619929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.935091970 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 11468708087 ps |
| CPU time | 74.87 seconds |
| Started | Oct 12 12:46:10 AM UTC 24 |
| Finished | Oct 12 12:47:26 AM UTC 24 |
| Peak memory | 226612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935091970 -assert nopostproc + UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_passthru_mem_tl_intg_err.935091970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2130522794 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 727356934 ps |
| CPU time | 11.2 seconds |
| Started | Oct 12 12:46:10 AM UTC 24 |
| Finished | Oct 12 12:46:22 AM UTC 24 |
| Peak memory | 220324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130522794 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_same_csr_outstanding.2130522794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1674949873 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 290489432 ps |
| CPU time | 21.92 seconds |
| Started | Oct 12 12:46:10 AM UTC 24 |
| Finished | Oct 12 12:46:33 AM UTC 24 |
| Peak memory | 226300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1674949873 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.1674949873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3323208354 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 1672210370 ps |
| CPU time | 143.26 seconds |
| Started | Oct 12 12:46:10 AM UTC 24 |
| Finished | Oct 12 12:48:35 AM UTC 24 |
| Peak memory | 227768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3323208354 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_intg_err.3323208354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2820827884 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 1166591954 ps |
| CPU time | 15.75 seconds |
| Started | Oct 12 12:46:23 AM UTC 24 |
| Finished | Oct 12 12:46:40 AM UTC 24 |
| Peak memory | 227748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2820827884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17. rom_ctrl_csr_mem_rw_with_rand_reset.2820827884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2412438975 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 205766287 ps |
| CPU time | 10.5 seconds |
| Started | Oct 12 12:46:20 AM UTC 24 |
| Finished | Oct 12 12:46:32 AM UTC 24 |
| Peak memory | 220060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412438975 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.2412438975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.4229222575 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 2106246516 ps |
| CPU time | 58.85 seconds |
| Started | Oct 12 12:46:12 AM UTC 24 |
| Finished | Oct 12 12:47:12 AM UTC 24 |
| Peak memory | 224248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229222575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_passthru_mem_tl_intg_err.4229222575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1158577563 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 1080190505 ps |
| CPU time | 16.62 seconds |
| Started | Oct 12 12:46:22 AM UTC 24 |
| Finished | Oct 12 12:46:40 AM UTC 24 |
| Peak memory | 222116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158577563 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_same_csr_outstanding.1158577563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3978860852 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 342304336 ps |
| CPU time | 19.21 seconds |
| Started | Oct 12 12:46:12 AM UTC 24 |
| Finished | Oct 12 12:46:32 AM UTC 24 |
| Peak memory | 226556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978860852 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.3978860852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1199936468 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 351689911 ps |
| CPU time | 98.34 seconds |
| Started | Oct 12 12:46:19 AM UTC 24 |
| Finished | Oct 12 12:48:00 AM UTC 24 |
| Peak memory | 222120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199936468 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_intg_err.1199936468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3759951485 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 1095784914 ps |
| CPU time | 19.93 seconds |
| Started | Oct 12 12:46:30 AM UTC 24 |
| Finished | Oct 12 12:46:51 AM UTC 24 |
| Peak memory | 226264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3759951485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18. rom_ctrl_csr_mem_rw_with_rand_reset.3759951485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2162098440 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 293341232 ps |
| CPU time | 14.82 seconds |
| Started | Oct 12 12:46:25 AM UTC 24 |
| Finished | Oct 12 12:46:41 AM UTC 24 |
| Peak memory | 220320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2162098440 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.2162098440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2155988912 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 1116647613 ps |
| CPU time | 62.8 seconds |
| Started | Oct 12 12:46:24 AM UTC 24 |
| Finished | Oct 12 12:47:29 AM UTC 24 |
| Peak memory | 224184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2155988912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_passthru_mem_tl_intg_err.2155988912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1032408858 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 212390004 ps |
| CPU time | 14.13 seconds |
| Started | Oct 12 12:46:27 AM UTC 24 |
| Finished | Oct 12 12:46:42 AM UTC 24 |
| Peak memory | 222116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032408858 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_same_csr_outstanding.1032408858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1673846509 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 554970247 ps |
| CPU time | 21.06 seconds |
| Started | Oct 12 12:46:25 AM UTC 24 |
| Finished | Oct 12 12:46:48 AM UTC 24 |
| Peak memory | 226528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673846509 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.1673846509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2426293506 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 1216917975 ps |
| CPU time | 170.44 seconds |
| Started | Oct 12 12:46:25 AM UTC 24 |
| Finished | Oct 12 12:49:19 AM UTC 24 |
| Peak memory | 227704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426293506 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_intg_err.2426293506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1789136060 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 664196362 ps |
| CPU time | 13.73 seconds |
| Started | Oct 12 12:46:50 AM UTC 24 |
| Finished | Oct 12 12:47:05 AM UTC 24 |
| Peak memory | 226584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1789136060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19. rom_ctrl_csr_mem_rw_with_rand_reset.1789136060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_rw.4011631710 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 2098285017 ps |
| CPU time | 10.22 seconds |
| Started | Oct 12 12:46:33 AM UTC 24 |
| Finished | Oct 12 12:46:44 AM UTC 24 |
| Peak memory | 220060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011631710 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.4011631710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.4027576199 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 2488414321 ps |
| CPU time | 54.52 seconds |
| Started | Oct 12 12:46:32 AM UTC 24 |
| Finished | Oct 12 12:47:28 AM UTC 24 |
| Peak memory | 224240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4027576199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_passthru_mem_tl_intg_err.4027576199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.73990192 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 306264259 ps |
| CPU time | 8.08 seconds |
| Started | Oct 12 12:46:34 AM UTC 24 |
| Finished | Oct 12 12:46:43 AM UTC 24 |
| Peak memory | 222372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=73990192 -assert nopostp roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_same_csr_outstanding.73990192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_errors.375703297 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 536208066 ps |
| CPU time | 17.77 seconds |
| Started | Oct 12 12:46:32 AM UTC 24 |
| Finished | Oct 12 12:46:51 AM UTC 24 |
| Peak memory | 226616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375703297 -assert nopostproc +UVM_TESTNAME=ro m_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.375703297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.4262449448 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 727169112 ps |
| CPU time | 9.19 seconds |
| Started | Oct 12 12:44:49 AM UTC 24 |
| Finished | Oct 12 12:44:59 AM UTC 24 |
| Peak memory | 220124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4262449448 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_aliasing.4262449448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.923885827 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 728290536 ps |
| CPU time | 10.67 seconds |
| Started | Oct 12 12:44:49 AM UTC 24 |
| Finished | Oct 12 12:45:01 AM UTC 24 |
| Peak memory | 220068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923885827 -assert nopostproc +UVM_TE STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_bash.923885827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.117540334 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 297848653 ps |
| CPU time | 20.47 seconds |
| Started | Oct 12 12:44:49 AM UTC 24 |
| Finished | Oct 12 12:45:11 AM UTC 24 |
| Peak memory | 222372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117540334 -assert nopostproc +UVM_TE STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_reset.117540334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2172832478 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 2356564627 ps |
| CPU time | 12.9 seconds |
| Started | Oct 12 12:44:49 AM UTC 24 |
| Finished | Oct 12 12:45:03 AM UTC 24 |
| Peak memory | 226396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2172832478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.r om_ctrl_csr_mem_rw_with_rand_reset.2172832478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2507691093 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 726555840 ps |
| CPU time | 11.61 seconds |
| Started | Oct 12 12:44:49 AM UTC 24 |
| Finished | Oct 12 12:45:02 AM UTC 24 |
| Peak memory | 220128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2507691093 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.2507691093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.320887267 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 1076610260 ps |
| CPU time | 16.38 seconds |
| Started | Oct 12 12:44:49 AM UTC 24 |
| Finished | Oct 12 12:45:06 AM UTC 24 |
| Peak memory | 220008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320887267 -assert nopostpr oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_partial_access.320887267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1291983280 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 294350968 ps |
| CPU time | 11.29 seconds |
| Started | Oct 12 12:44:49 AM UTC 24 |
| Finished | Oct 12 12:45:01 AM UTC 24 |
| Peak memory | 220260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1291983280 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk.1291983280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1213096564 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 4504919107 ps |
| CPU time | 52.38 seconds |
| Started | Oct 12 12:44:49 AM UTC 24 |
| Finished | Oct 12 12:45:43 AM UTC 24 |
| Peak memory | 226676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1213096564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_passthru_mem_tl_intg_err.1213096564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1540319686 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 287992051 ps |
| CPU time | 14.73 seconds |
| Started | Oct 12 12:44:49 AM UTC 24 |
| Finished | Oct 12 12:45:05 AM UTC 24 |
| Peak memory | 220068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540319686 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_same_csr_outstanding.1540319686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1969828561 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 1069866135 ps |
| CPU time | 11.69 seconds |
| Started | Oct 12 12:44:49 AM UTC 24 |
| Finished | Oct 12 12:45:02 AM UTC 24 |
| Peak memory | 226284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969828561 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.1969828561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3043552508 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 377681306 ps |
| CPU time | 167.3 seconds |
| Started | Oct 12 12:44:49 AM UTC 24 |
| Finished | Oct 12 12:47:39 AM UTC 24 |
| Peak memory | 224160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3043552508 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_intg_err.3043552508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2852829451 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 2276814540 ps |
| CPU time | 14.05 seconds |
| Started | Oct 12 12:45:05 AM UTC 24 |
| Finished | Oct 12 12:45:21 AM UTC 24 |
| Peak memory | 220444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852829451 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_aliasing.2852829451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.4085753202 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 376957979 ps |
| CPU time | 11.22 seconds |
| Started | Oct 12 12:45:05 AM UTC 24 |
| Finished | Oct 12 12:45:18 AM UTC 24 |
| Peak memory | 220316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085753202 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_bash.4085753202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3562769711 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 302826080 ps |
| CPU time | 21.2 seconds |
| Started | Oct 12 12:45:05 AM UTC 24 |
| Finished | Oct 12 12:45:28 AM UTC 24 |
| Peak memory | 222152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3562769711 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_reset.3562769711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3456380231 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 224998631 ps |
| CPU time | 13.3 seconds |
| Started | Oct 12 12:45:05 AM UTC 24 |
| Finished | Oct 12 12:45:20 AM UTC 24 |
| Peak memory | 226268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3456380231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.r om_ctrl_csr_mem_rw_with_rand_reset.3456380231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3507885447 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 552232937 ps |
| CPU time | 8.99 seconds |
| Started | Oct 12 12:45:05 AM UTC 24 |
| Finished | Oct 12 12:45:16 AM UTC 24 |
| Peak memory | 220060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507885447 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.3507885447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2222732505 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 1869964328 ps |
| CPU time | 8.25 seconds |
| Started | Oct 12 12:45:05 AM UTC 24 |
| Finished | Oct 12 12:45:15 AM UTC 24 |
| Peak memory | 219984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2222732505 -assert nopostp roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_partial_access.2222732505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2164065143 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 210724164 ps |
| CPU time | 11.13 seconds |
| Started | Oct 12 12:45:05 AM UTC 24 |
| Finished | Oct 12 12:45:17 AM UTC 24 |
| Peak memory | 219992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164065143 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.2164065143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3505012670 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 287300728 ps |
| CPU time | 9.91 seconds |
| Started | Oct 12 12:45:05 AM UTC 24 |
| Finished | Oct 12 12:45:17 AM UTC 24 |
| Peak memory | 220324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505012670 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_same_csr_outstanding.3505012670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3358927601 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 406645783 ps |
| CPU time | 15.79 seconds |
| Started | Oct 12 12:45:05 AM UTC 24 |
| Finished | Oct 12 12:45:22 AM UTC 24 |
| Peak memory | 226284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3358927601 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.3358927601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3110518317 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 1046379086 ps |
| CPU time | 81.19 seconds |
| Started | Oct 12 12:45:05 AM UTC 24 |
| Finished | Oct 12 12:46:28 AM UTC 24 |
| Peak memory | 224124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110518317 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_intg_err.3110518317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3562488842 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 699876601 ps |
| CPU time | 8.64 seconds |
| Started | Oct 12 12:45:06 AM UTC 24 |
| Finished | Oct 12 12:45:16 AM UTC 24 |
| Peak memory | 220008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3562488842 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_aliasing.3562488842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.4122166967 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 4994243842 ps |
| CPU time | 13.36 seconds |
| Started | Oct 12 12:45:06 AM UTC 24 |
| Finished | Oct 12 12:45:21 AM UTC 24 |
| Peak memory | 220116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122166967 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_bash.4122166967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.618710163 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 1067757411 ps |
| CPU time | 21.52 seconds |
| Started | Oct 12 12:45:05 AM UTC 24 |
| Finished | Oct 12 12:45:29 AM UTC 24 |
| Peak memory | 222232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618710163 -assert nopostproc +UVM_TE STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_reset.618710163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3059068918 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 220728582 ps |
| CPU time | 12.09 seconds |
| Started | Oct 12 12:45:06 AM UTC 24 |
| Finished | Oct 12 12:45:19 AM UTC 24 |
| Peak memory | 226152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3059068918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.r om_ctrl_csr_mem_rw_with_rand_reset.3059068918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2822142299 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 555674221 ps |
| CPU time | 13.14 seconds |
| Started | Oct 12 12:45:06 AM UTC 24 |
| Finished | Oct 12 12:45:20 AM UTC 24 |
| Peak memory | 220320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822142299 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.2822142299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.856025923 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 1161949370 ps |
| CPU time | 12.38 seconds |
| Started | Oct 12 12:45:05 AM UTC 24 |
| Finished | Oct 12 12:45:19 AM UTC 24 |
| Peak memory | 220008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=856025923 -assert nopostpr oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_partial_access.856025923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3046321480 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 208851936 ps |
| CPU time | 12.57 seconds |
| Started | Oct 12 12:45:05 AM UTC 24 |
| Finished | Oct 12 12:45:20 AM UTC 24 |
| Peak memory | 219892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046321480 -assert nopostproc +UVM_T ESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.3046321480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3220740813 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 6374656855 ps |
| CPU time | 70.59 seconds |
| Started | Oct 12 12:45:05 AM UTC 24 |
| Finished | Oct 12 12:46:18 AM UTC 24 |
| Peak memory | 226420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220740813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_passthru_mem_tl_intg_err.3220740813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1934407076 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 678589441 ps |
| CPU time | 12.77 seconds |
| Started | Oct 12 12:45:06 AM UTC 24 |
| Finished | Oct 12 12:45:20 AM UTC 24 |
| Peak memory | 222180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934407076 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_same_csr_outstanding.1934407076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1388238777 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 212462497 ps |
| CPU time | 16.23 seconds |
| Started | Oct 12 12:45:05 AM UTC 24 |
| Finished | Oct 12 12:45:23 AM UTC 24 |
| Peak memory | 226472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1388238777 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.1388238777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1523567646 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 402998923 ps |
| CPU time | 116.25 seconds |
| Started | Oct 12 12:45:05 AM UTC 24 |
| Finished | Oct 12 12:47:04 AM UTC 24 |
| Peak memory | 222116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523567646 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_intg_err.1523567646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2123969176 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 552665991 ps |
| CPU time | 13.69 seconds |
| Started | Oct 12 12:45:11 AM UTC 24 |
| Finished | Oct 12 12:45:26 AM UTC 24 |
| Peak memory | 226268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2123969176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.r om_ctrl_csr_mem_rw_with_rand_reset.2123969176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3583718411 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 488684178 ps |
| CPU time | 9.75 seconds |
| Started | Oct 12 12:45:08 AM UTC 24 |
| Finished | Oct 12 12:45:19 AM UTC 24 |
| Peak memory | 220000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3583718411 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.3583718411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.991576865 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 2071521876 ps |
| CPU time | 44.67 seconds |
| Started | Oct 12 12:45:06 AM UTC 24 |
| Finished | Oct 12 12:45:52 AM UTC 24 |
| Peak memory | 224188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=991576865 -assert nopostproc + UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_passthru_mem_tl_intg_err.991576865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1049452360 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 208782133 ps |
| CPU time | 11.87 seconds |
| Started | Oct 12 12:45:08 AM UTC 24 |
| Finished | Oct 12 12:45:21 AM UTC 24 |
| Peak memory | 220068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1049452360 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_same_csr_outstanding.1049452360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1483060191 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 1690073971 ps |
| CPU time | 17.96 seconds |
| Started | Oct 12 12:45:08 AM UTC 24 |
| Finished | Oct 12 12:45:27 AM UTC 24 |
| Peak memory | 226508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483060191 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.1483060191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2199099279 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 329646639 ps |
| CPU time | 197.57 seconds |
| Started | Oct 12 12:45:08 AM UTC 24 |
| Finished | Oct 12 12:48:29 AM UTC 24 |
| Peak memory | 224484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2199099279 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_intg_err.2199099279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.296757629 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 723694557 ps |
| CPU time | 11.23 seconds |
| Started | Oct 12 12:45:19 AM UTC 24 |
| Finished | Oct 12 12:45:31 AM UTC 24 |
| Peak memory | 227500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=296757629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.ro m_ctrl_csr_mem_rw_with_rand_reset.296757629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2100081213 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 376791193 ps |
| CPU time | 12.36 seconds |
| Started | Oct 12 12:45:16 AM UTC 24 |
| Finished | Oct 12 12:45:30 AM UTC 24 |
| Peak memory | 220064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2100081213 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.2100081213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.231174691 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 6046284690 ps |
| CPU time | 85.12 seconds |
| Started | Oct 12 12:45:14 AM UTC 24 |
| Finished | Oct 12 12:46:42 AM UTC 24 |
| Peak memory | 226684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231174691 -assert nopostproc + UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_passthru_mem_tl_intg_err.231174691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1288998318 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 1067791724 ps |
| CPU time | 12.29 seconds |
| Started | Oct 12 12:45:18 AM UTC 24 |
| Finished | Oct 12 12:45:31 AM UTC 24 |
| Peak memory | 220324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288998318 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_same_csr_outstanding.1288998318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3512419637 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 571149300 ps |
| CPU time | 12.7 seconds |
| Started | Oct 12 12:45:15 AM UTC 24 |
| Finished | Oct 12 12:45:29 AM UTC 24 |
| Peak memory | 226284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3512419637 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.3512419637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3582273283 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 434105604 ps |
| CPU time | 182.86 seconds |
| Started | Oct 12 12:45:16 AM UTC 24 |
| Finished | Oct 12 12:48:22 AM UTC 24 |
| Peak memory | 224164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3582273283 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_intg_err.3582273283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3169469631 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 307868598 ps |
| CPU time | 16.18 seconds |
| Started | Oct 12 12:45:21 AM UTC 24 |
| Finished | Oct 12 12:45:39 AM UTC 24 |
| Peak memory | 227308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3169469631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.r om_ctrl_csr_mem_rw_with_rand_reset.3169469631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_csr_rw.232800340 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 524000290 ps |
| CPU time | 12.13 seconds |
| Started | Oct 12 12:45:20 AM UTC 24 |
| Finished | Oct 12 12:45:33 AM UTC 24 |
| Peak memory | 220072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232800340 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.232800340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3463589074 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 1993707803 ps |
| CPU time | 46.63 seconds |
| Started | Oct 12 12:45:19 AM UTC 24 |
| Finished | Oct 12 12:46:07 AM UTC 24 |
| Peak memory | 224244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463589074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_passthru_mem_tl_intg_err.3463589074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.447258045 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 218295212 ps |
| CPU time | 12.79 seconds |
| Started | Oct 12 12:45:20 AM UTC 24 |
| Finished | Oct 12 12:45:34 AM UTC 24 |
| Peak memory | 222180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=447258045 -assert nopost proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_same_csr_outstanding.447258045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3574907774 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 212437330 ps |
| CPU time | 13.64 seconds |
| Started | Oct 12 12:45:20 AM UTC 24 |
| Finished | Oct 12 12:45:35 AM UTC 24 |
| Peak memory | 226284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574907774 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.3574907774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.62250661 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 581990897 ps |
| CPU time | 154.82 seconds |
| Started | Oct 12 12:45:20 AM UTC 24 |
| Finished | Oct 12 12:47:58 AM UTC 24 |
| Peak memory | 227704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62250661 -assert nopostproc +UVM_ TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_intg_err.62250661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1646371984 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 573413404 ps |
| CPU time | 16.32 seconds |
| Started | Oct 12 12:45:22 AM UTC 24 |
| Finished | Oct 12 12:45:40 AM UTC 24 |
| Peak memory | 226332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1646371984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.r om_ctrl_csr_mem_rw_with_rand_reset.1646371984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2526478483 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 725622716 ps |
| CPU time | 11.84 seconds |
| Started | Oct 12 12:45:21 AM UTC 24 |
| Finished | Oct 12 12:45:35 AM UTC 24 |
| Peak memory | 220320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2526478483 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.2526478483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1588517578 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 3953246370 ps |
| CPU time | 62.01 seconds |
| Started | Oct 12 12:45:21 AM UTC 24 |
| Finished | Oct 12 12:46:25 AM UTC 24 |
| Peak memory | 222364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1588517578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_passthru_mem_tl_intg_err.1588517578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2231712699 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 1165871198 ps |
| CPU time | 9.09 seconds |
| Started | Oct 12 12:45:22 AM UTC 24 |
| Finished | Oct 12 12:45:33 AM UTC 24 |
| Peak memory | 220324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231712699 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_same_csr_outstanding.2231712699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1078451486 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 1305526850 ps |
| CPU time | 13.7 seconds |
| Started | Oct 12 12:45:21 AM UTC 24 |
| Finished | Oct 12 12:45:36 AM UTC 24 |
| Peak memory | 226284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078451486 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.1078451486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.108999343 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 304463204 ps |
| CPU time | 14.69 seconds |
| Started | Oct 12 12:45:30 AM UTC 24 |
| Finished | Oct 12 12:45:46 AM UTC 24 |
| Peak memory | 226272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=108999343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.ro m_ctrl_csr_mem_rw_with_rand_reset.108999343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_csr_rw.4134056403 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 1031907126 ps |
| CPU time | 12.17 seconds |
| Started | Oct 12 12:45:29 AM UTC 24 |
| Finished | Oct 12 12:45:42 AM UTC 24 |
| Peak memory | 220060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4134056403 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.4134056403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3034358767 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 21321746274 ps |
| CPU time | 89.29 seconds |
| Started | Oct 12 12:45:23 AM UTC 24 |
| Finished | Oct 12 12:46:55 AM UTC 24 |
| Peak memory | 224308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3034358767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_passthru_mem_tl_intg_err.3034358767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3338618829 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 2786621824 ps |
| CPU time | 10.08 seconds |
| Started | Oct 12 12:45:29 AM UTC 24 |
| Finished | Oct 12 12:45:40 AM UTC 24 |
| Peak memory | 222500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338618829 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_same_csr_outstanding.3338618829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_errors.357653436 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 212664738 ps |
| CPU time | 13.34 seconds |
| Started | Oct 12 12:45:25 AM UTC 24 |
| Finished | Oct 12 12:45:39 AM UTC 24 |
| Peak memory | 226292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357653436 -assert nopostproc +UVM_TESTNAME=ro m_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.357653436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2070909288 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 837919168 ps |
| CPU time | 178.63 seconds |
| Started | Oct 12 12:45:27 AM UTC 24 |
| Finished | Oct 12 12:48:28 AM UTC 24 |
| Peak memory | 227696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070909288 -assert nopostproc +UV M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_intg_err.2070909288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_alert_test.3106358943 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 212438824 ps |
| CPU time | 8.83 seconds |
| Started | Oct 12 02:22:38 AM UTC 24 |
| Finished | Oct 12 02:22:48 AM UTC 24 |
| Peak memory | 229836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106358943 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.3106358943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_kmac_err_chk.1031212695 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 380576108 ps |
| CPU time | 29.27 seconds |
| Started | Oct 12 02:22:38 AM UTC 24 |
| Finished | Oct 12 02:23:09 AM UTC 24 |
| Peak memory | 229944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031212695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.1031212695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_max_throughput_chk.4171761494 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 1107455809 ps |
| CPU time | 12.65 seconds |
| Started | Oct 12 02:22:38 AM UTC 24 |
| Finished | Oct 12 02:22:52 AM UTC 24 |
| Peak memory | 230628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4171761494 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.4171761494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_sec_cm.924588776 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 2030278624 ps |
| CPU time | 268.44 seconds |
| Started | Oct 12 02:22:38 AM UTC 24 |
| Finished | Oct 12 02:27:11 AM UTC 24 |
| Peak memory | 261268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=924588776 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.924588776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_smoke.1083260634 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 770281242 ps |
| CPU time | 14.3 seconds |
| Started | Oct 12 02:22:37 AM UTC 24 |
| Finished | Oct 12 02:22:52 AM UTC 24 |
| Peak memory | 230816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1083260634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64 kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.1083260634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.4265430815 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 8945171220 ps |
| CPU time | 204.47 seconds |
| Started | Oct 12 02:22:38 AM UTC 24 |
| Finished | Oct 12 02:26:06 AM UTC 24 |
| Peak memory | 248240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=4265430815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.rom_ctrl_stress_all_with_rand_reset.4265430815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_alert_test.3047654188 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 1026020747 ps |
| CPU time | 14.31 seconds |
| Started | Oct 12 02:22:39 AM UTC 24 |
| Finished | Oct 12 02:22:55 AM UTC 24 |
| Peak memory | 229780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3047654188 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.3047654188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1736944937 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 16818015014 ps |
| CPU time | 334.66 seconds |
| Started | Oct 12 02:22:39 AM UTC 24 |
| Finished | Oct 12 02:28:19 AM UTC 24 |
| Peak memory | 252240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736944937 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_corrupt_sig_fatal_chk.1736944937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_kmac_err_chk.1737370575 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 370739644 ps |
| CPU time | 30.96 seconds |
| Started | Oct 12 02:22:39 AM UTC 24 |
| Finished | Oct 12 02:23:12 AM UTC 24 |
| Peak memory | 230040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1737370575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.1737370575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_max_throughput_chk.3912130398 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 3234418500 ps |
| CPU time | 17.7 seconds |
| Started | Oct 12 02:22:38 AM UTC 24 |
| Finished | Oct 12 02:22:57 AM UTC 24 |
| Peak memory | 230428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912130398 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.3912130398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_sec_cm.205725838 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 619847514 ps |
| CPU time | 227.45 seconds |
| Started | Oct 12 02:22:39 AM UTC 24 |
| Finished | Oct 12 02:26:30 AM UTC 24 |
| Peak memory | 259272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205725838 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.205725838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_smoke.3488953027 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 914087258 ps |
| CPU time | 17.97 seconds |
| Started | Oct 12 02:22:38 AM UTC 24 |
| Finished | Oct 12 02:22:57 AM UTC 24 |
| Peak memory | 230688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488953027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64 kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.3488953027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_alert_test.2236614846 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 377381518 ps |
| CPU time | 11.91 seconds |
| Started | Oct 12 02:25:08 AM UTC 24 |
| Finished | Oct 12 02:25:21 AM UTC 24 |
| Peak memory | 229876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236614846 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.2236614846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_kmac_err_chk.1790115049 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 2143227153 ps |
| CPU time | 26.31 seconds |
| Started | Oct 12 02:25:03 AM UTC 24 |
| Finished | Oct 12 02:25:31 AM UTC 24 |
| Peak memory | 230512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1790115049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.1790115049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_max_throughput_chk.3982314743 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 19933464258 ps |
| CPU time | 24.85 seconds |
| Started | Oct 12 02:25:02 AM UTC 24 |
| Finished | Oct 12 02:25:28 AM UTC 24 |
| Peak memory | 230760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982314743 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.3982314743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all.3650800732 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 400092144 ps |
| CPU time | 37.31 seconds |
| Started | Oct 12 02:25:00 AM UTC 24 |
| Finished | Oct 12 02:25:39 AM UTC 24 |
| Peak memory | 230684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=365080073 2 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all.3650800732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.761851820 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 16897085989 ps |
| CPU time | 171.01 seconds |
| Started | Oct 12 02:25:05 AM UTC 24 |
| Finished | Oct 12 02:27:59 AM UTC 24 |
| Peak memory | 248368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=761851820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 10.rom_ctrl_stress_all_with_rand_reset.761851820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/10.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_alert_test.219127633 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 370178335 ps |
| CPU time | 13.22 seconds |
| Started | Oct 12 02:25:26 AM UTC 24 |
| Finished | Oct 12 02:25:40 AM UTC 24 |
| Peak memory | 230128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=219127633 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.219127633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.786584151 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 5949917916 ps |
| CPU time | 247.64 seconds |
| Started | Oct 12 02:25:19 AM UTC 24 |
| Finished | Oct 12 02:29:31 AM UTC 24 |
| Peak memory | 261300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786584151 -assert nopostproc +UVM_TEST NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_corrupt_sig_fatal_chk.786584151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_kmac_err_chk.2839993408 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 2013667954 ps |
| CPU time | 23.29 seconds |
| Started | Oct 12 02:25:22 AM UTC 24 |
| Finished | Oct 12 02:25:47 AM UTC 24 |
| Peak memory | 230440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839993408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.2839993408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_max_throughput_chk.315433241 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 807179314 ps |
| CPU time | 13.73 seconds |
| Started | Oct 12 02:25:19 AM UTC 24 |
| Finished | Oct 12 02:25:34 AM UTC 24 |
| Peak memory | 230116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315433241 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.315433241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all.3271669885 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 407995018 ps |
| CPU time | 27.8 seconds |
| Started | Oct 12 02:25:19 AM UTC 24 |
| Finished | Oct 12 02:25:48 AM UTC 24 |
| Peak memory | 230684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327166988 5 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all.3271669885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.3593188019 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 2816856616 ps |
| CPU time | 24.91 seconds |
| Started | Oct 12 02:25:25 AM UTC 24 |
| Finished | Oct 12 02:25:51 AM UTC 24 |
| Peak memory | 232884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=3593188019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 11.rom_ctrl_stress_all_with_rand_reset.3593188019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_alert_test.3336872386 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 288491899 ps |
| CPU time | 13.02 seconds |
| Started | Oct 12 02:25:39 AM UTC 24 |
| Finished | Oct 12 02:25:53 AM UTC 24 |
| Peak memory | 229964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336872386 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.3336872386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1319928772 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 5412559242 ps |
| CPU time | 164.31 seconds |
| Started | Oct 12 02:25:32 AM UTC 24 |
| Finished | Oct 12 02:28:19 AM UTC 24 |
| Peak memory | 248124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1319928772 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_corrupt_sig_fatal_chk.1319928772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_kmac_err_chk.3499659468 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 539807374 ps |
| CPU time | 34.81 seconds |
| Started | Oct 12 02:25:35 AM UTC 24 |
| Finished | Oct 12 02:26:11 AM UTC 24 |
| Peak memory | 230316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499659468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.3499659468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_max_throughput_chk.239414703 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 218317083 ps |
| CPU time | 13.6 seconds |
| Started | Oct 12 02:25:29 AM UTC 24 |
| Finished | Oct 12 02:25:44 AM UTC 24 |
| Peak memory | 230060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239414703 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.239414703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all.4103205554 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 3319738018 ps |
| CPU time | 43.64 seconds |
| Started | Oct 12 02:25:27 AM UTC 24 |
| Finished | Oct 12 02:26:12 AM UTC 24 |
| Peak memory | 231008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410320555 4 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all.4103205554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.2564349982 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 2650304876 ps |
| CPU time | 123.4 seconds |
| Started | Oct 12 02:25:35 AM UTC 24 |
| Finished | Oct 12 02:27:41 AM UTC 24 |
| Peak memory | 237040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2564349982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 12.rom_ctrl_stress_all_with_rand_reset.2564349982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/12.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_alert_test.1606235627 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 212732497 ps |
| CPU time | 13.28 seconds |
| Started | Oct 12 02:25:50 AM UTC 24 |
| Finished | Oct 12 02:26:04 AM UTC 24 |
| Peak memory | 229996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606235627 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.1606235627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2769018219 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 5353404197 ps |
| CPU time | 322.31 seconds |
| Started | Oct 12 02:25:44 AM UTC 24 |
| Finished | Oct 12 02:31:11 AM UTC 24 |
| Peak memory | 260752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769018219 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_corrupt_sig_fatal_chk.2769018219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_kmac_err_chk.317993379 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 700119964 ps |
| CPU time | 20.41 seconds |
| Started | Oct 12 02:25:47 AM UTC 24 |
| Finished | Oct 12 02:26:09 AM UTC 24 |
| Peak memory | 230440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317993379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM _TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_c trl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.317993379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all.37992538 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 749050026 ps |
| CPU time | 32.7 seconds |
| Started | Oct 12 02:25:41 AM UTC 24 |
| Finished | Oct 12 02:26:15 AM UTC 24 |
| Peak memory | 230688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37992538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all.37992538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.950987817 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 2178896021 ps |
| CPU time | 115.41 seconds |
| Started | Oct 12 02:25:47 AM UTC 24 |
| Finished | Oct 12 02:27:45 AM UTC 24 |
| Peak memory | 241144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=950987817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 13.rom_ctrl_stress_all_with_rand_reset.950987817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_alert_test.1650884696 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 5485687194 ps |
| CPU time | 21.73 seconds |
| Started | Oct 12 02:26:05 AM UTC 24 |
| Finished | Oct 12 02:26:28 AM UTC 24 |
| Peak memory | 229852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650884696 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.1650884696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3424684646 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 4530940373 ps |
| CPU time | 356.02 seconds |
| Started | Oct 12 02:25:54 AM UTC 24 |
| Finished | Oct 12 02:31:54 AM UTC 24 |
| Peak memory | 261300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424684646 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_corrupt_sig_fatal_chk.3424684646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_kmac_err_chk.4004341756 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 1261446553 ps |
| CPU time | 19.82 seconds |
| Started | Oct 12 02:26:01 AM UTC 24 |
| Finished | Oct 12 02:26:22 AM UTC 24 |
| Peak memory | 230320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004341756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.4004341756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_max_throughput_chk.597783027 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 405957434 ps |
| CPU time | 16.65 seconds |
| Started | Oct 12 02:25:54 AM UTC 24 |
| Finished | Oct 12 02:26:12 AM UTC 24 |
| Peak memory | 230100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=597783027 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.597783027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all.3949917034 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 392342961 ps |
| CPU time | 26.29 seconds |
| Started | Oct 12 02:25:52 AM UTC 24 |
| Finished | Oct 12 02:26:19 AM UTC 24 |
| Peak memory | 230748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394991703 4 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all.3949917034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.1734057823 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 3220965966 ps |
| CPU time | 163.52 seconds |
| Started | Oct 12 02:26:03 AM UTC 24 |
| Finished | Oct 12 02:28:49 AM UTC 24 |
| Peak memory | 247408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1734057823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 14.rom_ctrl_stress_all_with_rand_reset.1734057823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/14.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_alert_test.3020018165 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 2092337888 ps |
| CPU time | 10.15 seconds |
| Started | Oct 12 02:26:13 AM UTC 24 |
| Finished | Oct 12 02:26:25 AM UTC 24 |
| Peak memory | 229812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020018165 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.3020018165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1697774084 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 9255682428 ps |
| CPU time | 193.92 seconds |
| Started | Oct 12 02:26:10 AM UTC 24 |
| Finished | Oct 12 02:29:28 AM UTC 24 |
| Peak memory | 247952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697774084 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_corrupt_sig_fatal_chk.1697774084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_kmac_err_chk.3691324200 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 1357890768 ps |
| CPU time | 29.86 seconds |
| Started | Oct 12 02:26:12 AM UTC 24 |
| Finished | Oct 12 02:26:44 AM UTC 24 |
| Peak memory | 230144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691324200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.3691324200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_max_throughput_chk.3513112618 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 811761031 ps |
| CPU time | 16.68 seconds |
| Started | Oct 12 02:26:06 AM UTC 24 |
| Finished | Oct 12 02:26:24 AM UTC 24 |
| Peak memory | 230380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3513112618 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.3513112618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all.2743061723 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 2137457599 ps |
| CPU time | 24.89 seconds |
| Started | Oct 12 02:26:05 AM UTC 24 |
| Finished | Oct 12 02:26:31 AM UTC 24 |
| Peak memory | 230700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274306172 3 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all.2743061723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.1556999759 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 5939961883 ps |
| CPU time | 164.79 seconds |
| Started | Oct 12 02:26:12 AM UTC 24 |
| Finished | Oct 12 02:29:00 AM UTC 24 |
| Peak memory | 241072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1556999759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 15.rom_ctrl_stress_all_with_rand_reset.1556999759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/15.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_alert_test.28548941 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 1009362981 ps |
| CPU time | 12.63 seconds |
| Started | Oct 12 02:26:25 AM UTC 24 |
| Finished | Oct 12 02:26:39 AM UTC 24 |
| Peak memory | 230164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28548941 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.28548941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2832343636 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 1654795696 ps |
| CPU time | 189.21 seconds |
| Started | Oct 12 02:26:20 AM UTC 24 |
| Finished | Oct 12 02:29:32 AM UTC 24 |
| Peak memory | 258408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832343636 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_corrupt_sig_fatal_chk.2832343636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_max_throughput_chk.1356916231 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 4172533089 ps |
| CPU time | 22.76 seconds |
| Started | Oct 12 02:26:19 AM UTC 24 |
| Finished | Oct 12 02:26:43 AM UTC 24 |
| Peak memory | 230952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356916231 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.1356916231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all.294444419 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 837876198 ps |
| CPU time | 52.97 seconds |
| Started | Oct 12 02:26:17 AM UTC 24 |
| Finished | Oct 12 02:27:11 AM UTC 24 |
| Peak memory | 230700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294444419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all.294444419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.2265654767 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 5110656177 ps |
| CPU time | 38.43 seconds |
| Started | Oct 12 02:26:24 AM UTC 24 |
| Finished | Oct 12 02:27:04 AM UTC 24 |
| Peak memory | 234928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2265654767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 16.rom_ctrl_stress_all_with_rand_reset.2265654767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/16.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_alert_test.1719189462 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 1336865684 ps |
| CPU time | 14.1 seconds |
| Started | Oct 12 02:26:41 AM UTC 24 |
| Finished | Oct 12 02:26:57 AM UTC 24 |
| Peak memory | 230076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719189462 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.1719189462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2859024470 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 55874869066 ps |
| CPU time | 209.89 seconds |
| Started | Oct 12 02:26:31 AM UTC 24 |
| Finished | Oct 12 02:30:04 AM UTC 24 |
| Peak memory | 247692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2859024470 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_corrupt_sig_fatal_chk.2859024470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_kmac_err_chk.4128219598 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 371144010 ps |
| CPU time | 27.65 seconds |
| Started | Oct 12 02:26:32 AM UTC 24 |
| Finished | Oct 12 02:27:01 AM UTC 24 |
| Peak memory | 230032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128219598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.4128219598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_max_throughput_chk.4069011627 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 1216585067 ps |
| CPU time | 15.17 seconds |
| Started | Oct 12 02:26:29 AM UTC 24 |
| Finished | Oct 12 02:26:46 AM UTC 24 |
| Peak memory | 230380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4069011627 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.4069011627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all.1670431552 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 406367460 ps |
| CPU time | 25.93 seconds |
| Started | Oct 12 02:26:26 AM UTC 24 |
| Finished | Oct 12 02:26:53 AM UTC 24 |
| Peak memory | 230896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=167043155 2 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all.1670431552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.2515655901 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 2169136442 ps |
| CPU time | 66.86 seconds |
| Started | Oct 12 02:26:39 AM UTC 24 |
| Finished | Oct 12 02:27:48 AM UTC 24 |
| Peak memory | 234992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2515655901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 17.rom_ctrl_stress_all_with_rand_reset.2515655901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/17.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_alert_test.2332606206 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 1138104317 ps |
| CPU time | 12.41 seconds |
| Started | Oct 12 02:26:54 AM UTC 24 |
| Finished | Oct 12 02:27:07 AM UTC 24 |
| Peak memory | 229584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2332606206 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.2332606206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1403175223 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 27128547640 ps |
| CPU time | 429.74 seconds |
| Started | Oct 12 02:26:45 AM UTC 24 |
| Finished | Oct 12 02:34:01 AM UTC 24 |
| Peak memory | 263488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403175223 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_corrupt_sig_fatal_chk.1403175223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_kmac_err_chk.438579956 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 2096697105 ps |
| CPU time | 32.78 seconds |
| Started | Oct 12 02:26:47 AM UTC 24 |
| Finished | Oct 12 02:27:21 AM UTC 24 |
| Peak memory | 230536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=438579956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM _TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_c trl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.438579956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_max_throughput_chk.2489514013 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 4038016727 ps |
| CPU time | 14.51 seconds |
| Started | Oct 12 02:26:45 AM UTC 24 |
| Finished | Oct 12 02:27:00 AM UTC 24 |
| Peak memory | 230760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2489514013 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.2489514013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all.3224309350 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 934857839 ps |
| CPU time | 26.29 seconds |
| Started | Oct 12 02:26:43 AM UTC 24 |
| Finished | Oct 12 02:27:11 AM UTC 24 |
| Peak memory | 230700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322430935 0 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all.3224309350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.2959765998 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 5097092783 ps |
| CPU time | 190.77 seconds |
| Started | Oct 12 02:26:50 AM UTC 24 |
| Finished | Oct 12 02:30:04 AM UTC 24 |
| Peak memory | 248424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2959765998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 18.rom_ctrl_stress_all_with_rand_reset.2959765998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/18.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_alert_test.975940633 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 376974841 ps |
| CPU time | 9.14 seconds |
| Started | Oct 12 02:27:04 AM UTC 24 |
| Finished | Oct 12 02:27:15 AM UTC 24 |
| Peak memory | 229864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975940633 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.975940633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.581122190 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 5292790428 ps |
| CPU time | 297.96 seconds |
| Started | Oct 12 02:27:01 AM UTC 24 |
| Finished | Oct 12 02:32:03 AM UTC 24 |
| Peak memory | 259100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=581122190 -assert nopostproc +UVM_TEST NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_corrupt_sig_fatal_chk.581122190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_kmac_err_chk.2907017737 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 2012600404 ps |
| CPU time | 31.74 seconds |
| Started | Oct 12 02:27:02 AM UTC 24 |
| Finished | Oct 12 02:27:35 AM UTC 24 |
| Peak memory | 230316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907017737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.2907017737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_max_throughput_chk.3245490085 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 215305801 ps |
| CPU time | 14.71 seconds |
| Started | Oct 12 02:26:58 AM UTC 24 |
| Finished | Oct 12 02:27:14 AM UTC 24 |
| Peak memory | 230196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3245490085 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.3245490085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all.3031666014 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 348366560 ps |
| CPU time | 25.32 seconds |
| Started | Oct 12 02:26:57 AM UTC 24 |
| Finished | Oct 12 02:27:24 AM UTC 24 |
| Peak memory | 230684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303166601 4 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all.3031666014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.2513058422 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 27647627360 ps |
| CPU time | 97.79 seconds |
| Started | Oct 12 02:27:03 AM UTC 24 |
| Finished | Oct 12 02:28:43 AM UTC 24 |
| Peak memory | 248232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2513058422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 19.rom_ctrl_stress_all_with_rand_reset.2513058422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/19.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3087131344 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 14974725227 ps |
| CPU time | 274.8 seconds |
| Started | Oct 12 02:22:53 AM UTC 24 |
| Finished | Oct 12 02:27:31 AM UTC 24 |
| Peak memory | 248996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087131344 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_corrupt_sig_fatal_chk.3087131344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_max_throughput_chk.2962496257 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 1111163634 ps |
| CPU time | 18.32 seconds |
| Started | Oct 12 02:22:49 AM UTC 24 |
| Finished | Oct 12 02:23:08 AM UTC 24 |
| Peak memory | 230364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2962496257 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.2962496257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_sec_cm.2476442453 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 496298564 ps |
| CPU time | 118.95 seconds |
| Started | Oct 12 02:22:58 AM UTC 24 |
| Finished | Oct 12 02:24:59 AM UTC 24 |
| Peak memory | 261340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2476442453 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.2476442453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_smoke.2892267985 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 837082595 ps |
| CPU time | 16.21 seconds |
| Started | Oct 12 02:22:39 AM UTC 24 |
| Finished | Oct 12 02:22:57 AM UTC 24 |
| Peak memory | 230712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2892267985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64 kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.2892267985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.3700941031 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 79657793294 ps |
| CPU time | 271.35 seconds |
| Started | Oct 12 02:22:56 AM UTC 24 |
| Finished | Oct 12 02:27:31 AM UTC 24 |
| Peak memory | 242096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=3700941031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.rom_ctrl_stress_all_with_rand_reset.3700941031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_alert_test.3778077906 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 608810658 ps |
| CPU time | 12.49 seconds |
| Started | Oct 12 02:27:15 AM UTC 24 |
| Finished | Oct 12 02:27:29 AM UTC 24 |
| Peak memory | 229900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3778077906 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.3778077906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/20.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.537255990 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 6439182560 ps |
| CPU time | 159.09 seconds |
| Started | Oct 12 02:27:12 AM UTC 24 |
| Finished | Oct 12 02:29:53 AM UTC 24 |
| Peak memory | 247792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=537255990 -assert nopostproc +UVM_TEST NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_corrupt_sig_fatal_chk.537255990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/20.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_kmac_err_chk.10369052 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 371423476 ps |
| CPU time | 19.54 seconds |
| Started | Oct 12 02:27:12 AM UTC 24 |
| Finished | Oct 12 02:27:33 AM UTC 24 |
| Peak memory | 230016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10369052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_ TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ct rl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.10369052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/20.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_max_throughput_chk.3791257345 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 19875998566 ps |
| CPU time | 21.62 seconds |
| Started | Oct 12 02:27:11 AM UTC 24 |
| Finished | Oct 12 02:27:33 AM UTC 24 |
| Peak memory | 230952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3791257345 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.3791257345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/20.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all.1840492073 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 845578590 ps |
| CPU time | 17.88 seconds |
| Started | Oct 12 02:27:08 AM UTC 24 |
| Finished | Oct 12 02:27:28 AM UTC 24 |
| Peak memory | 230880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184049207 3 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all.1840492073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/20.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_alert_test.826495350 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 1869209710 ps |
| CPU time | 7.87 seconds |
| Started | Oct 12 02:27:28 AM UTC 24 |
| Finished | Oct 12 02:27:37 AM UTC 24 |
| Peak memory | 229760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=826495350 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.826495350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/21.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3753434949 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 4696143927 ps |
| CPU time | 196.03 seconds |
| Started | Oct 12 02:27:22 AM UTC 24 |
| Finished | Oct 12 02:30:41 AM UTC 24 |
| Peak memory | 230308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3753434949 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_corrupt_sig_fatal_chk.3753434949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/21.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_kmac_err_chk.1176829669 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 2010920068 ps |
| CPU time | 23.96 seconds |
| Started | Oct 12 02:27:24 AM UTC 24 |
| Finished | Oct 12 02:27:49 AM UTC 24 |
| Peak memory | 230324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1176829669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.1176829669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/21.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_max_throughput_chk.4220872931 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 1061769474 ps |
| CPU time | 16.61 seconds |
| Started | Oct 12 02:27:16 AM UTC 24 |
| Finished | Oct 12 02:27:34 AM UTC 24 |
| Peak memory | 230364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220872931 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.4220872931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/21.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all.1112536318 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 2380237105 ps |
| CPU time | 28.6 seconds |
| Started | Oct 12 02:27:15 AM UTC 24 |
| Finished | Oct 12 02:27:45 AM UTC 24 |
| Peak memory | 230728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111253631 8 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all.1112536318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/21.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.2439792358 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 12963804440 ps |
| CPU time | 193.62 seconds |
| Started | Oct 12 02:27:25 AM UTC 24 |
| Finished | Oct 12 02:30:42 AM UTC 24 |
| Peak memory | 248424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2439792358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 21.rom_ctrl_stress_all_with_rand_reset.2439792358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/21.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_alert_test.907671439 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 1071080179 ps |
| CPU time | 13.75 seconds |
| Started | Oct 12 02:27:34 AM UTC 24 |
| Finished | Oct 12 02:27:49 AM UTC 24 |
| Peak memory | 229572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907671439 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.907671439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/22.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.4105028368 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 4918503899 ps |
| CPU time | 193.23 seconds |
| Started | Oct 12 02:27:33 AM UTC 24 |
| Finished | Oct 12 02:30:49 AM UTC 24 |
| Peak memory | 261388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105028368 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_corrupt_sig_fatal_chk.4105028368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/22.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_kmac_err_chk.4127160663 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 534298225 ps |
| CPU time | 34.88 seconds |
| Started | Oct 12 02:27:34 AM UTC 24 |
| Finished | Oct 12 02:28:10 AM UTC 24 |
| Peak memory | 230044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127160663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.4127160663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/22.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_max_throughput_chk.3956954143 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 3496003186 ps |
| CPU time | 16.2 seconds |
| Started | Oct 12 02:27:32 AM UTC 24 |
| Finished | Oct 12 02:27:49 AM UTC 24 |
| Peak memory | 230404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956954143 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.3956954143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/22.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all.879917360 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 806399244 ps |
| CPU time | 19.84 seconds |
| Started | Oct 12 02:27:29 AM UTC 24 |
| Finished | Oct 12 02:27:51 AM UTC 24 |
| Peak memory | 230872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879917360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all.879917360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/22.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.3526285285 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 3613059009 ps |
| CPU time | 154.11 seconds |
| Started | Oct 12 02:27:34 AM UTC 24 |
| Finished | Oct 12 02:30:10 AM UTC 24 |
| Peak memory | 236976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=3526285285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 22.rom_ctrl_stress_all_with_rand_reset.3526285285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/22.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_alert_test.4121588512 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 541828369 ps |
| CPU time | 14.65 seconds |
| Started | Oct 12 02:27:45 AM UTC 24 |
| Finished | Oct 12 02:28:01 AM UTC 24 |
| Peak memory | 229776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121588512 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.4121588512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/23.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.939998216 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 15205642215 ps |
| CPU time | 175.16 seconds |
| Started | Oct 12 02:27:38 AM UTC 24 |
| Finished | Oct 12 02:30:36 AM UTC 24 |
| Peak memory | 247628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=939998216 -assert nopostproc +UVM_TEST NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_corrupt_sig_fatal_chk.939998216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/23.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_kmac_err_chk.2719456661 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 1375050383 ps |
| CPU time | 23 seconds |
| Started | Oct 12 02:27:41 AM UTC 24 |
| Finished | Oct 12 02:28:06 AM UTC 24 |
| Peak memory | 229968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719456661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.2719456661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/23.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_max_throughput_chk.3555740298 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 567625310 ps |
| CPU time | 11.26 seconds |
| Started | Oct 12 02:27:36 AM UTC 24 |
| Finished | Oct 12 02:27:48 AM UTC 24 |
| Peak memory | 230068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3555740298 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.3555740298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/23.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all.1151405774 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 319995366 ps |
| CPU time | 16.23 seconds |
| Started | Oct 12 02:27:35 AM UTC 24 |
| Finished | Oct 12 02:27:52 AM UTC 24 |
| Peak memory | 230684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115140577 4 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all.1151405774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/23.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.3599478141 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 11272399510 ps |
| CPU time | 61.73 seconds |
| Started | Oct 12 02:27:43 AM UTC 24 |
| Finished | Oct 12 02:28:47 AM UTC 24 |
| Peak memory | 247216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=3599478141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 23.rom_ctrl_stress_all_with_rand_reset.3599478141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/23.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_alert_test.2888541314 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 541125843 ps |
| CPU time | 13.91 seconds |
| Started | Oct 12 02:27:50 AM UTC 24 |
| Finished | Oct 12 02:28:05 AM UTC 24 |
| Peak memory | 230200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888541314 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.2888541314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/24.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2772539369 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 2991585012 ps |
| CPU time | 248.64 seconds |
| Started | Oct 12 02:27:49 AM UTC 24 |
| Finished | Oct 12 02:32:01 AM UTC 24 |
| Peak memory | 245796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772539369 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_corrupt_sig_fatal_chk.2772539369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/24.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_kmac_err_chk.1000008983 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 373895921 ps |
| CPU time | 22.03 seconds |
| Started | Oct 12 02:27:50 AM UTC 24 |
| Finished | Oct 12 02:28:13 AM UTC 24 |
| Peak memory | 230280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000008983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.1000008983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/24.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_max_throughput_chk.2662917829 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 307731574 ps |
| CPU time | 14.11 seconds |
| Started | Oct 12 02:27:48 AM UTC 24 |
| Finished | Oct 12 02:28:04 AM UTC 24 |
| Peak memory | 230052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662917829 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.2662917829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/24.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all.1095097692 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 828467745 ps |
| CPU time | 56.39 seconds |
| Started | Oct 12 02:27:46 AM UTC 24 |
| Finished | Oct 12 02:28:44 AM UTC 24 |
| Peak memory | 230688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109509769 2 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all.1095097692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/24.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.1872534351 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 16935469230 ps |
| CPU time | 76.1 seconds |
| Started | Oct 12 02:27:50 AM UTC 24 |
| Finished | Oct 12 02:29:08 AM UTC 24 |
| Peak memory | 237040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1872534351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 24.rom_ctrl_stress_all_with_rand_reset.1872534351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/24.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_alert_test.3082830649 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 1028936234 ps |
| CPU time | 11.78 seconds |
| Started | Oct 12 02:28:02 AM UTC 24 |
| Finished | Oct 12 02:28:16 AM UTC 24 |
| Peak memory | 229964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082830649 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.3082830649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/25.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1022950068 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 15172388186 ps |
| CPU time | 293.81 seconds |
| Started | Oct 12 02:27:53 AM UTC 24 |
| Finished | Oct 12 02:32:51 AM UTC 24 |
| Peak memory | 261360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022950068 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_corrupt_sig_fatal_chk.1022950068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/25.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_kmac_err_chk.2005514839 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 2012369441 ps |
| CPU time | 29.55 seconds |
| Started | Oct 12 02:27:58 AM UTC 24 |
| Finished | Oct 12 02:28:29 AM UTC 24 |
| Peak memory | 230320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2005514839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.2005514839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/25.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_max_throughput_chk.859309888 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 558007239 ps |
| CPU time | 16.13 seconds |
| Started | Oct 12 02:27:52 AM UTC 24 |
| Finished | Oct 12 02:28:09 AM UTC 24 |
| Peak memory | 230372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859309888 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.859309888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/25.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all.255001993 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 2731364097 ps |
| CPU time | 26.53 seconds |
| Started | Oct 12 02:27:51 AM UTC 24 |
| Finished | Oct 12 02:28:19 AM UTC 24 |
| Peak memory | 230956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=255001993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all.255001993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/25.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.878801987 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 3907143584 ps |
| CPU time | 200.15 seconds |
| Started | Oct 12 02:27:59 AM UTC 24 |
| Finished | Oct 12 02:31:22 AM UTC 24 |
| Peak memory | 236984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=878801987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 25.rom_ctrl_stress_all_with_rand_reset.878801987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/25.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_alert_test.1846571782 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 1009189864 ps |
| CPU time | 10.91 seconds |
| Started | Oct 12 02:28:13 AM UTC 24 |
| Finished | Oct 12 02:28:25 AM UTC 24 |
| Peak memory | 229628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846571782 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.1846571782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/26.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.736088596 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 18203836866 ps |
| CPU time | 254.5 seconds |
| Started | Oct 12 02:28:06 AM UTC 24 |
| Finished | Oct 12 02:32:25 AM UTC 24 |
| Peak memory | 258472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736088596 -assert nopostproc +UVM_TEST NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_corrupt_sig_fatal_chk.736088596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/26.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_kmac_err_chk.3432167543 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 1414077647 ps |
| CPU time | 18.79 seconds |
| Started | Oct 12 02:28:10 AM UTC 24 |
| Finished | Oct 12 02:28:30 AM UTC 24 |
| Peak memory | 230232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3432167543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.3432167543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/26.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_max_throughput_chk.587998735 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 314163348 ps |
| CPU time | 19.44 seconds |
| Started | Oct 12 02:28:05 AM UTC 24 |
| Finished | Oct 12 02:28:26 AM UTC 24 |
| Peak memory | 230300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=587998735 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.587998735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/26.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all.1680482629 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 642077690 ps |
| CPU time | 16.15 seconds |
| Started | Oct 12 02:28:04 AM UTC 24 |
| Finished | Oct 12 02:28:22 AM UTC 24 |
| Peak memory | 230684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168048262 9 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all.1680482629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/26.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.3204129078 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 1955124363 ps |
| CPU time | 82 seconds |
| Started | Oct 12 02:28:11 AM UTC 24 |
| Finished | Oct 12 02:29:35 AM UTC 24 |
| Peak memory | 234864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=3204129078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 26.rom_ctrl_stress_all_with_rand_reset.3204129078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/26.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_alert_test.3951493133 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 1024836945 ps |
| CPU time | 14.2 seconds |
| Started | Oct 12 02:28:22 AM UTC 24 |
| Finished | Oct 12 02:28:38 AM UTC 24 |
| Peak memory | 229576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3951493133 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.3951493133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/27.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.1179349626 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 17718663419 ps |
| CPU time | 283.7 seconds |
| Started | Oct 12 02:28:19 AM UTC 24 |
| Finished | Oct 12 02:33:07 AM UTC 24 |
| Peak memory | 258360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179349626 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_corrupt_sig_fatal_chk.1179349626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/27.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_kmac_err_chk.2552401414 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 380734376 ps |
| CPU time | 29.42 seconds |
| Started | Oct 12 02:28:19 AM UTC 24 |
| Finished | Oct 12 02:28:50 AM UTC 24 |
| Peak memory | 230036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552401414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.2552401414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/27.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_max_throughput_chk.621525258 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 1061329269 ps |
| CPU time | 18.18 seconds |
| Started | Oct 12 02:28:16 AM UTC 24 |
| Finished | Oct 12 02:28:35 AM UTC 24 |
| Peak memory | 230340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621525258 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.621525258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/27.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all.1330041262 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 395896299 ps |
| CPU time | 33.79 seconds |
| Started | Oct 12 02:28:14 AM UTC 24 |
| Finished | Oct 12 02:28:49 AM UTC 24 |
| Peak memory | 230688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133004126 2 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all.1330041262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/27.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.1606714828 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 4433789818 ps |
| CPU time | 276.58 seconds |
| Started | Oct 12 02:28:20 AM UTC 24 |
| Finished | Oct 12 02:33:01 AM UTC 24 |
| Peak memory | 236976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1606714828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 27.rom_ctrl_stress_all_with_rand_reset.1606714828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/27.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_alert_test.3974913440 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 295788000 ps |
| CPU time | 13.81 seconds |
| Started | Oct 12 02:28:35 AM UTC 24 |
| Finished | Oct 12 02:28:50 AM UTC 24 |
| Peak memory | 229716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974913440 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.3974913440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/28.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.937987181 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 6161528914 ps |
| CPU time | 362.88 seconds |
| Started | Oct 12 02:28:30 AM UTC 24 |
| Finished | Oct 12 02:34:37 AM UTC 24 |
| Peak memory | 261544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=937987181 -assert nopostproc +UVM_TEST NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_corrupt_sig_fatal_chk.937987181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/28.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_kmac_err_chk.432904912 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 2094451159 ps |
| CPU time | 27.62 seconds |
| Started | Oct 12 02:28:31 AM UTC 24 |
| Finished | Oct 12 02:29:00 AM UTC 24 |
| Peak memory | 229968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=432904912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM _TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_c trl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.432904912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/28.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_max_throughput_chk.1138608301 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 222377679 ps |
| CPU time | 16.84 seconds |
| Started | Oct 12 02:28:27 AM UTC 24 |
| Finished | Oct 12 02:28:46 AM UTC 24 |
| Peak memory | 230116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138608301 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.1138608301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/28.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all.3584589111 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 827119269 ps |
| CPU time | 13.75 seconds |
| Started | Oct 12 02:28:25 AM UTC 24 |
| Finished | Oct 12 02:28:40 AM UTC 24 |
| Peak memory | 230704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358458911 1 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all.3584589111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/28.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.945192160 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 3622376810 ps |
| CPU time | 203.51 seconds |
| Started | Oct 12 02:28:34 AM UTC 24 |
| Finished | Oct 12 02:32:01 AM UTC 24 |
| Peak memory | 237684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=945192160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 28.rom_ctrl_stress_all_with_rand_reset.945192160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/28.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_alert_test.1830118792 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 383618454 ps |
| CPU time | 9.47 seconds |
| Started | Oct 12 02:28:45 AM UTC 24 |
| Finished | Oct 12 02:28:56 AM UTC 24 |
| Peak memory | 229864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830118792 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.1830118792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/29.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.250850493 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 15629398670 ps |
| CPU time | 306.72 seconds |
| Started | Oct 12 02:28:41 AM UTC 24 |
| Finished | Oct 12 02:33:52 AM UTC 24 |
| Peak memory | 259252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=250850493 -assert nopostproc +UVM_TEST NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_corrupt_sig_fatal_chk.250850493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/29.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_kmac_err_chk.3807470701 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 7932677818 ps |
| CPU time | 30.78 seconds |
| Started | Oct 12 02:28:43 AM UTC 24 |
| Finished | Oct 12 02:29:15 AM UTC 24 |
| Peak memory | 230884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807470701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.3807470701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/29.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_max_throughput_chk.432977308 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 222791505 ps |
| CPU time | 11.05 seconds |
| Started | Oct 12 02:28:39 AM UTC 24 |
| Finished | Oct 12 02:28:51 AM UTC 24 |
| Peak memory | 230076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=432977308 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.432977308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/29.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all.139742699 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 384825057 ps |
| CPU time | 35.95 seconds |
| Started | Oct 12 02:28:36 AM UTC 24 |
| Finished | Oct 12 02:29:13 AM UTC 24 |
| Peak memory | 230876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139742699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all.139742699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/29.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.1442436052 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 3683706466 ps |
| CPU time | 81.94 seconds |
| Started | Oct 12 02:28:44 AM UTC 24 |
| Finished | Oct 12 02:30:08 AM UTC 24 |
| Peak memory | 236976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1442436052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 29.rom_ctrl_stress_all_with_rand_reset.1442436052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/29.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_alert_test.1119075780 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 212391923 ps |
| CPU time | 11.24 seconds |
| Started | Oct 12 02:23:12 AM UTC 24 |
| Finished | Oct 12 02:23:25 AM UTC 24 |
| Peak memory | 229660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119075780 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.1119075780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2705920270 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 50921391897 ps |
| CPU time | 512.09 seconds |
| Started | Oct 12 02:23:09 AM UTC 24 |
| Finished | Oct 12 02:31:47 AM UTC 24 |
| Peak memory | 262464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705920270 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_corrupt_sig_fatal_chk.2705920270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_kmac_err_chk.94598479 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 2009898303 ps |
| CPU time | 33.57 seconds |
| Started | Oct 12 02:23:09 AM UTC 24 |
| Finished | Oct 12 02:23:44 AM UTC 24 |
| Peak memory | 230540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94598479 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_ TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ct rl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.94598479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_max_throughput_chk.3089324546 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 968871237 ps |
| CPU time | 16.46 seconds |
| Started | Oct 12 02:23:06 AM UTC 24 |
| Finished | Oct 12 02:23:24 AM UTC 24 |
| Peak memory | 230092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3089324546 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.3089324546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_smoke.3409421501 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 825299951 ps |
| CPU time | 14.64 seconds |
| Started | Oct 12 02:22:58 AM UTC 24 |
| Finished | Oct 12 02:23:14 AM UTC 24 |
| Peak memory | 230712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409421501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64 kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.3409421501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all.2068247896 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 338370820 ps |
| CPU time | 31.27 seconds |
| Started | Oct 12 02:22:58 AM UTC 24 |
| Finished | Oct 12 02:23:31 AM UTC 24 |
| Peak memory | 230632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206824789 6 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all.2068247896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_alert_test.1367271975 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 1217135410 ps |
| CPU time | 11.14 seconds |
| Started | Oct 12 02:28:51 AM UTC 24 |
| Finished | Oct 12 02:29:03 AM UTC 24 |
| Peak memory | 229868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367271975 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.1367271975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/30.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.3059455235 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 3288045249 ps |
| CPU time | 248.23 seconds |
| Started | Oct 12 02:28:50 AM UTC 24 |
| Finished | Oct 12 02:33:02 AM UTC 24 |
| Peak memory | 230284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3059455235 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_corrupt_sig_fatal_chk.3059455235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/30.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_kmac_err_chk.4068509533 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 1538783509 ps |
| CPU time | 25.28 seconds |
| Started | Oct 12 02:28:50 AM UTC 24 |
| Finished | Oct 12 02:29:16 AM UTC 24 |
| Peak memory | 230504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4068509533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.4068509533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/30.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_max_throughput_chk.166834506 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 1119067820 ps |
| CPU time | 11.69 seconds |
| Started | Oct 12 02:28:48 AM UTC 24 |
| Finished | Oct 12 02:29:01 AM UTC 24 |
| Peak memory | 230364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166834506 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.166834506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/30.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all.3735807722 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 674644929 ps |
| CPU time | 25.47 seconds |
| Started | Oct 12 02:28:47 AM UTC 24 |
| Finished | Oct 12 02:29:13 AM UTC 24 |
| Peak memory | 230684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373580772 2 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all.3735807722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/30.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.2685875287 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 14264290666 ps |
| CPU time | 144.52 seconds |
| Started | Oct 12 02:28:51 AM UTC 24 |
| Finished | Oct 12 02:31:18 AM UTC 24 |
| Peak memory | 248232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2685875287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 30.rom_ctrl_stress_all_with_rand_reset.2685875287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/30.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_alert_test.410651755 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 297527794 ps |
| CPU time | 16.05 seconds |
| Started | Oct 12 02:29:04 AM UTC 24 |
| Finished | Oct 12 02:29:21 AM UTC 24 |
| Peak memory | 230024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410651755 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.410651755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/31.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.889485507 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 21665576854 ps |
| CPU time | 345.27 seconds |
| Started | Oct 12 02:29:00 AM UTC 24 |
| Finished | Oct 12 02:34:51 AM UTC 24 |
| Peak memory | 261360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=889485507 -assert nopostproc +UVM_TEST NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_corrupt_sig_fatal_chk.889485507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/31.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_kmac_err_chk.1866309976 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 741616955 ps |
| CPU time | 22.71 seconds |
| Started | Oct 12 02:29:01 AM UTC 24 |
| Finished | Oct 12 02:29:25 AM UTC 24 |
| Peak memory | 229936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866309976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.1866309976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/31.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_max_throughput_chk.120981502 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 1100842895 ps |
| CPU time | 16.05 seconds |
| Started | Oct 12 02:28:57 AM UTC 24 |
| Finished | Oct 12 02:29:15 AM UTC 24 |
| Peak memory | 230564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120981502 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.120981502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/31.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all.1578489672 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 731777040 ps |
| CPU time | 39.85 seconds |
| Started | Oct 12 02:28:52 AM UTC 24 |
| Finished | Oct 12 02:29:33 AM UTC 24 |
| Peak memory | 230684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157848967 2 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all.1578489672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/31.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.46717351 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 1833153202 ps |
| CPU time | 80.87 seconds |
| Started | Oct 12 02:29:02 AM UTC 24 |
| Finished | Oct 12 02:30:24 AM UTC 24 |
| Peak memory | 241012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=46717351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.46717351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/31.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_alert_test.2397679255 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 1538703211 ps |
| CPU time | 10.88 seconds |
| Started | Oct 12 02:29:17 AM UTC 24 |
| Finished | Oct 12 02:29:29 AM UTC 24 |
| Peak memory | 229964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397679255 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.2397679255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/32.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.835470953 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 3285535493 ps |
| CPU time | 216.96 seconds |
| Started | Oct 12 02:29:14 AM UTC 24 |
| Finished | Oct 12 02:32:54 AM UTC 24 |
| Peak memory | 261440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835470953 -assert nopostproc +UVM_TEST NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_corrupt_sig_fatal_chk.835470953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/32.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_kmac_err_chk.1424123486 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 534559986 ps |
| CPU time | 34.84 seconds |
| Started | Oct 12 02:29:15 AM UTC 24 |
| Finished | Oct 12 02:29:51 AM UTC 24 |
| Peak memory | 230224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424123486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.1424123486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/32.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_max_throughput_chk.1180582758 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 232976804 ps |
| CPU time | 16.35 seconds |
| Started | Oct 12 02:29:14 AM UTC 24 |
| Finished | Oct 12 02:29:31 AM UTC 24 |
| Peak memory | 229148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1180582758 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.1180582758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/32.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all.2074041689 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 2087156877 ps |
| CPU time | 59.3 seconds |
| Started | Oct 12 02:29:09 AM UTC 24 |
| Finished | Oct 12 02:30:10 AM UTC 24 |
| Peak memory | 230688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207404168 9 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all.2074041689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/32.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.47567319 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 14361109056 ps |
| CPU time | 73.85 seconds |
| Started | Oct 12 02:29:16 AM UTC 24 |
| Finished | Oct 12 02:30:32 AM UTC 24 |
| Peak memory | 236980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=47567319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.47567319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/32.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_alert_test.2625319601 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 699372153 ps |
| CPU time | 8.23 seconds |
| Started | Oct 12 02:29:32 AM UTC 24 |
| Finished | Oct 12 02:29:41 AM UTC 24 |
| Peak memory | 229804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625319601 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.2625319601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/33.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.47692275 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 7934692863 ps |
| CPU time | 314.21 seconds |
| Started | Oct 12 02:29:29 AM UTC 24 |
| Finished | Oct 12 02:34:47 AM UTC 24 |
| Peak memory | 261308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47692275 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_corrupt_sig_fatal_chk.47692275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/33.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_kmac_err_chk.3293642547 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 2788806095 ps |
| CPU time | 29.11 seconds |
| Started | Oct 12 02:29:30 AM UTC 24 |
| Finished | Oct 12 02:30:00 AM UTC 24 |
| Peak memory | 230312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3293642547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.3293642547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/33.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_max_throughput_chk.1814030129 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 797275127 ps |
| CPU time | 12.73 seconds |
| Started | Oct 12 02:29:26 AM UTC 24 |
| Finished | Oct 12 02:29:40 AM UTC 24 |
| Peak memory | 230116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814030129 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.1814030129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/33.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all.3386534861 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 271818520 ps |
| CPU time | 29.32 seconds |
| Started | Oct 12 02:29:21 AM UTC 24 |
| Finished | Oct 12 02:29:52 AM UTC 24 |
| Peak memory | 230896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338653486 1 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all.3386534861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/33.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.3773411931 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 4302343367 ps |
| CPU time | 106.79 seconds |
| Started | Oct 12 02:29:32 AM UTC 24 |
| Finished | Oct 12 02:31:21 AM UTC 24 |
| Peak memory | 237168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=3773411931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 33.rom_ctrl_stress_all_with_rand_reset.3773411931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/33.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_alert_test.2914968389 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 555092306 ps |
| CPU time | 14.5 seconds |
| Started | Oct 12 02:29:44 AM UTC 24 |
| Finished | Oct 12 02:30:00 AM UTC 24 |
| Peak memory | 229836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2914968389 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.2914968389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/34.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.76104496 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 20573509946 ps |
| CPU time | 300.2 seconds |
| Started | Oct 12 02:29:35 AM UTC 24 |
| Finished | Oct 12 02:34:39 AM UTC 24 |
| Peak memory | 263352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76104496 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_corrupt_sig_fatal_chk.76104496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/34.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_kmac_err_chk.2092575732 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 2190710595 ps |
| CPU time | 34.28 seconds |
| Started | Oct 12 02:29:41 AM UTC 24 |
| Finished | Oct 12 02:30:17 AM UTC 24 |
| Peak memory | 230384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092575732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.2092575732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/34.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_max_throughput_chk.4058695173 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 1104347885 ps |
| CPU time | 16.95 seconds |
| Started | Oct 12 02:29:34 AM UTC 24 |
| Finished | Oct 12 02:29:52 AM UTC 24 |
| Peak memory | 230412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4058695173 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.4058695173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/34.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all.2877413997 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 1601710125 ps |
| CPU time | 49.97 seconds |
| Started | Oct 12 02:29:33 AM UTC 24 |
| Finished | Oct 12 02:30:25 AM UTC 24 |
| Peak memory | 230704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=287741399 7 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all.2877413997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/34.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.1584620205 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 14601816061 ps |
| CPU time | 60.02 seconds |
| Started | Oct 12 02:29:42 AM UTC 24 |
| Finished | Oct 12 02:30:44 AM UTC 24 |
| Peak memory | 241136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1584620205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 34.rom_ctrl_stress_all_with_rand_reset.1584620205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/34.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_alert_test.10577264 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 589294165 ps |
| CPU time | 12.48 seconds |
| Started | Oct 12 02:30:01 AM UTC 24 |
| Finished | Oct 12 02:30:15 AM UTC 24 |
| Peak memory | 229844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10577264 -assert nopostproc +UVM_TESTNAM E=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.10577264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/35.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3445579610 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 6322636302 ps |
| CPU time | 134.03 seconds |
| Started | Oct 12 02:29:53 AM UTC 24 |
| Finished | Oct 12 02:32:09 AM UTC 24 |
| Peak memory | 245968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445579610 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_corrupt_sig_fatal_chk.3445579610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/35.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_kmac_err_chk.2107258148 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 4979631609 ps |
| CPU time | 26.28 seconds |
| Started | Oct 12 02:29:54 AM UTC 24 |
| Finished | Oct 12 02:30:21 AM UTC 24 |
| Peak memory | 230380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2107258148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.2107258148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/35.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_max_throughput_chk.3627747325 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 219814880 ps |
| CPU time | 16.65 seconds |
| Started | Oct 12 02:29:53 AM UTC 24 |
| Finished | Oct 12 02:30:10 AM UTC 24 |
| Peak memory | 230260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627747325 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.3627747325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/35.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all.2180189273 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 853567085 ps |
| CPU time | 61.26 seconds |
| Started | Oct 12 02:29:53 AM UTC 24 |
| Finished | Oct 12 02:30:56 AM UTC 24 |
| Peak memory | 230704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=218018927 3 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all.2180189273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/35.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.366078204 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 2144849590 ps |
| CPU time | 109.2 seconds |
| Started | Oct 12 02:30:01 AM UTC 24 |
| Finished | Oct 12 02:31:53 AM UTC 24 |
| Peak memory | 243064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=366078204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 35.rom_ctrl_stress_all_with_rand_reset.366078204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/35.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_alert_test.567383078 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 212559954 ps |
| CPU time | 13.25 seconds |
| Started | Oct 12 02:30:12 AM UTC 24 |
| Finished | Oct 12 02:30:26 AM UTC 24 |
| Peak memory | 229672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=567383078 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.567383078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/36.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3701634704 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 3445493999 ps |
| CPU time | 219.9 seconds |
| Started | Oct 12 02:30:09 AM UTC 24 |
| Finished | Oct 12 02:33:53 AM UTC 24 |
| Peak memory | 259296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3701634704 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_corrupt_sig_fatal_chk.3701634704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/36.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_kmac_err_chk.308376953 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 383995121 ps |
| CPU time | 30.26 seconds |
| Started | Oct 12 02:30:10 AM UTC 24 |
| Finished | Oct 12 02:30:42 AM UTC 24 |
| Peak memory | 229952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308376953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM _TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_c trl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.308376953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/36.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_max_throughput_chk.124646972 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 224554622 ps |
| CPU time | 16.89 seconds |
| Started | Oct 12 02:30:05 AM UTC 24 |
| Finished | Oct 12 02:30:24 AM UTC 24 |
| Peak memory | 230348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=124646972 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.124646972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/36.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all.1167381686 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 606243114 ps |
| CPU time | 18.21 seconds |
| Started | Oct 12 02:30:04 AM UTC 24 |
| Finished | Oct 12 02:30:24 AM UTC 24 |
| Peak memory | 230620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116738168 6 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all.1167381686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/36.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.328120106 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 3340076381 ps |
| CPU time | 80.28 seconds |
| Started | Oct 12 02:30:12 AM UTC 24 |
| Finished | Oct 12 02:31:34 AM UTC 24 |
| Peak memory | 234936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=328120106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 36.rom_ctrl_stress_all_with_rand_reset.328120106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/36.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_alert_test.1114335181 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 239552839 ps |
| CPU time | 13.42 seconds |
| Started | Oct 12 02:30:25 AM UTC 24 |
| Finished | Oct 12 02:30:40 AM UTC 24 |
| Peak memory | 229776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114335181 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.1114335181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/37.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.4015793192 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 6710925457 ps |
| CPU time | 234.04 seconds |
| Started | Oct 12 02:30:22 AM UTC 24 |
| Finished | Oct 12 02:34:20 AM UTC 24 |
| Peak memory | 261300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4015793192 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_corrupt_sig_fatal_chk.4015793192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/37.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_kmac_err_chk.29527170 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 2101931409 ps |
| CPU time | 24.74 seconds |
| Started | Oct 12 02:30:25 AM UTC 24 |
| Finished | Oct 12 02:30:52 AM UTC 24 |
| Peak memory | 230320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29527170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_ TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ct rl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.29527170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/37.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_max_throughput_chk.3801157646 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 755241625 ps |
| CPU time | 15.77 seconds |
| Started | Oct 12 02:30:18 AM UTC 24 |
| Finished | Oct 12 02:30:35 AM UTC 24 |
| Peak memory | 230340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3801157646 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.3801157646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/37.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all.229758249 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 6164399641 ps |
| CPU time | 51.84 seconds |
| Started | Oct 12 02:30:16 AM UTC 24 |
| Finished | Oct 12 02:31:09 AM UTC 24 |
| Peak memory | 230748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229758249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all.229758249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/37.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.1931151907 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 74771163948 ps |
| CPU time | 225.33 seconds |
| Started | Oct 12 02:30:25 AM UTC 24 |
| Finished | Oct 12 02:34:14 AM UTC 24 |
| Peak memory | 247224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1931151907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 37.rom_ctrl_stress_all_with_rand_reset.1931151907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/37.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_alert_test.3452158510 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 216238280 ps |
| CPU time | 8.81 seconds |
| Started | Oct 12 02:30:41 AM UTC 24 |
| Finished | Oct 12 02:30:51 AM UTC 24 |
| Peak memory | 229788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452158510 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.3452158510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/38.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.586194536 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 4364265986 ps |
| CPU time | 235.77 seconds |
| Started | Oct 12 02:30:32 AM UTC 24 |
| Finished | Oct 12 02:34:32 AM UTC 24 |
| Peak memory | 258360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586194536 -assert nopostproc +UVM_TEST NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_corrupt_sig_fatal_chk.586194536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/38.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_kmac_err_chk.1517908807 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 559576492 ps |
| CPU time | 32.58 seconds |
| Started | Oct 12 02:30:36 AM UTC 24 |
| Finished | Oct 12 02:31:10 AM UTC 24 |
| Peak memory | 230584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517908807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.1517908807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/38.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_max_throughput_chk.2714989855 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 221353824 ps |
| CPU time | 17.17 seconds |
| Started | Oct 12 02:30:26 AM UTC 24 |
| Finished | Oct 12 02:30:45 AM UTC 24 |
| Peak memory | 230068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2714989855 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.2714989855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/38.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all.3721301435 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 16526968637 ps |
| CPU time | 76.67 seconds |
| Started | Oct 12 02:30:25 AM UTC 24 |
| Finished | Oct 12 02:31:44 AM UTC 24 |
| Peak memory | 231008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372130143 5 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all.3721301435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/38.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.1263418648 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 5557311854 ps |
| CPU time | 148.75 seconds |
| Started | Oct 12 02:30:37 AM UTC 24 |
| Finished | Oct 12 02:33:08 AM UTC 24 |
| Peak memory | 237168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1263418648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 38.rom_ctrl_stress_all_with_rand_reset.1263418648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/38.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_alert_test.1366265023 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 212616645 ps |
| CPU time | 9.02 seconds |
| Started | Oct 12 02:30:46 AM UTC 24 |
| Finished | Oct 12 02:30:56 AM UTC 24 |
| Peak memory | 229660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366265023 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.1366265023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/39.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2054985557 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 6686087717 ps |
| CPU time | 160.53 seconds |
| Started | Oct 12 02:30:43 AM UTC 24 |
| Finished | Oct 12 02:33:26 AM UTC 24 |
| Peak memory | 230172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054985557 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_corrupt_sig_fatal_chk.2054985557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/39.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_kmac_err_chk.768176769 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 2021076605 ps |
| CPU time | 22.03 seconds |
| Started | Oct 12 02:30:43 AM UTC 24 |
| Finished | Oct 12 02:31:06 AM UTC 24 |
| Peak memory | 230536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768176769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM _TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_c trl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.768176769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/39.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_max_throughput_chk.2443019109 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 565087777 ps |
| CPU time | 11.51 seconds |
| Started | Oct 12 02:30:43 AM UTC 24 |
| Finished | Oct 12 02:30:56 AM UTC 24 |
| Peak memory | 230092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2443019109 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.2443019109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/39.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all.2025921591 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 647694362 ps |
| CPU time | 40.17 seconds |
| Started | Oct 12 02:30:42 AM UTC 24 |
| Finished | Oct 12 02:31:23 AM UTC 24 |
| Peak memory | 230684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202592159 1 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all.2025921591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/39.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.2767304813 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 9413408098 ps |
| CPU time | 101.8 seconds |
| Started | Oct 12 02:30:45 AM UTC 24 |
| Finished | Oct 12 02:32:29 AM UTC 24 |
| Peak memory | 248228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2767304813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 39.rom_ctrl_stress_all_with_rand_reset.2767304813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/39.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_alert_test.2524963840 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 2036729172 ps |
| CPU time | 21.9 seconds |
| Started | Oct 12 02:23:26 AM UTC 24 |
| Finished | Oct 12 02:23:49 AM UTC 24 |
| Peak memory | 229576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2524963840 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.2524963840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2623313759 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 4896776701 ps |
| CPU time | 307.81 seconds |
| Started | Oct 12 02:23:21 AM UTC 24 |
| Finished | Oct 12 02:28:32 AM UTC 24 |
| Peak memory | 261296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2623313759 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_corrupt_sig_fatal_chk.2623313759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_max_throughput_chk.3709618260 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 295027253 ps |
| CPU time | 19.05 seconds |
| Started | Oct 12 02:23:15 AM UTC 24 |
| Finished | Oct 12 02:23:35 AM UTC 24 |
| Peak memory | 230100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709618260 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.3709618260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_sec_cm.1631598779 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 512925168 ps |
| CPU time | 118.25 seconds |
| Started | Oct 12 02:23:26 AM UTC 24 |
| Finished | Oct 12 02:25:26 AM UTC 24 |
| Peak memory | 259292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1631598779 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.1631598779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_smoke.3249734736 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 236173278 ps |
| CPU time | 17.1 seconds |
| Started | Oct 12 02:23:13 AM UTC 24 |
| Finished | Oct 12 02:23:32 AM UTC 24 |
| Peak memory | 230888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249734736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64 kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.3249734736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all.3373330141 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 608372263 ps |
| CPU time | 31.35 seconds |
| Started | Oct 12 02:23:14 AM UTC 24 |
| Finished | Oct 12 02:23:46 AM UTC 24 |
| Peak memory | 230680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=337333014 1 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all.3373330141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.2600293220 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 3233124765 ps |
| CPU time | 200.67 seconds |
| Started | Oct 12 02:23:25 AM UTC 24 |
| Finished | Oct 12 02:26:49 AM UTC 24 |
| Peak memory | 236968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2600293220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 4.rom_ctrl_stress_all_with_rand_reset.2600293220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_alert_test.3599674812 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 294631035 ps |
| CPU time | 13.06 seconds |
| Started | Oct 12 02:30:57 AM UTC 24 |
| Finished | Oct 12 02:31:11 AM UTC 24 |
| Peak memory | 230008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599674812 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.3599674812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/40.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.1765876713 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 12326799147 ps |
| CPU time | 204.46 seconds |
| Started | Oct 12 02:30:49 AM UTC 24 |
| Finished | Oct 12 02:34:17 AM UTC 24 |
| Peak memory | 260504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765876713 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_corrupt_sig_fatal_chk.1765876713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/40.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_kmac_err_chk.2933838192 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 727955814 ps |
| CPU time | 25.41 seconds |
| Started | Oct 12 02:30:52 AM UTC 24 |
| Finished | Oct 12 02:31:18 AM UTC 24 |
| Peak memory | 230504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933838192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.2933838192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/40.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_max_throughput_chk.3025437413 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 311034332 ps |
| CPU time | 18.28 seconds |
| Started | Oct 12 02:30:48 AM UTC 24 |
| Finished | Oct 12 02:31:08 AM UTC 24 |
| Peak memory | 230044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025437413 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.3025437413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/40.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all.1690550710 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 2152332316 ps |
| CPU time | 32.28 seconds |
| Started | Oct 12 02:30:46 AM UTC 24 |
| Finished | Oct 12 02:31:20 AM UTC 24 |
| Peak memory | 230768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169055071 0 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all.1690550710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/40.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.2184487002 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 5318527578 ps |
| CPU time | 289.81 seconds |
| Started | Oct 12 02:30:53 AM UTC 24 |
| Finished | Oct 12 02:35:46 AM UTC 24 |
| Peak memory | 239964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2184487002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 40.rom_ctrl_stress_all_with_rand_reset.2184487002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/40.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_alert_test.2743864130 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 1068322560 ps |
| CPU time | 14.89 seconds |
| Started | Oct 12 02:31:08 AM UTC 24 |
| Finished | Oct 12 02:31:24 AM UTC 24 |
| Peak memory | 229776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2743864130 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.2743864130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/41.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3627159201 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 6011447651 ps |
| CPU time | 271.63 seconds |
| Started | Oct 12 02:31:02 AM UTC 24 |
| Finished | Oct 12 02:35:38 AM UTC 24 |
| Peak memory | 261296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627159201 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_corrupt_sig_fatal_chk.3627159201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/41.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_kmac_err_chk.2816453059 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 1276220320 ps |
| CPU time | 24.34 seconds |
| Started | Oct 12 02:31:04 AM UTC 24 |
| Finished | Oct 12 02:31:30 AM UTC 24 |
| Peak memory | 230224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2816453059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.2816453059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/41.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_max_throughput_chk.2688455471 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 299815119 ps |
| CPU time | 17.92 seconds |
| Started | Oct 12 02:30:57 AM UTC 24 |
| Finished | Oct 12 02:31:16 AM UTC 24 |
| Peak memory | 230372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688455471 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.2688455471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/41.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all.1961771485 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 842246254 ps |
| CPU time | 61.11 seconds |
| Started | Oct 12 02:30:57 AM UTC 24 |
| Finished | Oct 12 02:32:00 AM UTC 24 |
| Peak memory | 230896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=196177148 5 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all.1961771485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/41.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.3729744098 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 7886168295 ps |
| CPU time | 91.43 seconds |
| Started | Oct 12 02:31:07 AM UTC 24 |
| Finished | Oct 12 02:32:41 AM UTC 24 |
| Peak memory | 237040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=3729744098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 41.rom_ctrl_stress_all_with_rand_reset.3729744098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/41.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_alert_test.3054263523 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 300727116 ps |
| CPU time | 12.54 seconds |
| Started | Oct 12 02:31:17 AM UTC 24 |
| Finished | Oct 12 02:31:30 AM UTC 24 |
| Peak memory | 229580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3054263523 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.3054263523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/42.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.4019801696 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 26965136040 ps |
| CPU time | 184.6 seconds |
| Started | Oct 12 02:31:12 AM UTC 24 |
| Finished | Oct 12 02:34:19 AM UTC 24 |
| Peak memory | 259248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019801696 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_corrupt_sig_fatal_chk.4019801696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/42.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_kmac_err_chk.1853574314 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 535607081 ps |
| CPU time | 25.42 seconds |
| Started | Oct 12 02:31:12 AM UTC 24 |
| Finished | Oct 12 02:31:38 AM UTC 24 |
| Peak memory | 230324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1853574314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.1853574314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/42.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_max_throughput_chk.2927931408 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 396421211 ps |
| CPU time | 15.26 seconds |
| Started | Oct 12 02:31:10 AM UTC 24 |
| Finished | Oct 12 02:31:27 AM UTC 24 |
| Peak memory | 230380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2927931408 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.2927931408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/42.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all.765988967 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 432651939 ps |
| CPU time | 17.28 seconds |
| Started | Oct 12 02:31:10 AM UTC 24 |
| Finished | Oct 12 02:31:29 AM UTC 24 |
| Peak memory | 230444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=765988967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all.765988967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/42.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.489402517 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 13709475518 ps |
| CPU time | 125.43 seconds |
| Started | Oct 12 02:31:12 AM UTC 24 |
| Finished | Oct 12 02:33:19 AM UTC 24 |
| Peak memory | 248240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=489402517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 42.rom_ctrl_stress_all_with_rand_reset.489402517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/42.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_alert_test.2394683344 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 708056344 ps |
| CPU time | 12.24 seconds |
| Started | Oct 12 02:31:21 AM UTC 24 |
| Finished | Oct 12 02:31:35 AM UTC 24 |
| Peak memory | 229584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394683344 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.2394683344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/43.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1742279113 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 9443572143 ps |
| CPU time | 216.32 seconds |
| Started | Oct 12 02:31:19 AM UTC 24 |
| Finished | Oct 12 02:34:59 AM UTC 24 |
| Peak memory | 259276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1742279113 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_corrupt_sig_fatal_chk.1742279113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/43.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_kmac_err_chk.4155354323 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 2576639067 ps |
| CPU time | 21.95 seconds |
| Started | Oct 12 02:31:21 AM UTC 24 |
| Finished | Oct 12 02:31:45 AM UTC 24 |
| Peak memory | 230380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4155354323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.4155354323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/43.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_max_throughput_chk.2685361446 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 389473247 ps |
| CPU time | 13.3 seconds |
| Started | Oct 12 02:31:19 AM UTC 24 |
| Finished | Oct 12 02:31:33 AM UTC 24 |
| Peak memory | 230116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2685361446 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.2685361446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/43.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all.1076710505 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 1658198532 ps |
| CPU time | 37.09 seconds |
| Started | Oct 12 02:31:19 AM UTC 24 |
| Finished | Oct 12 02:31:59 AM UTC 24 |
| Peak memory | 230704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107671050 5 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all.1076710505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/43.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.1581614599 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 6745779251 ps |
| CPU time | 50.24 seconds |
| Started | Oct 12 02:31:21 AM UTC 24 |
| Finished | Oct 12 02:32:13 AM UTC 24 |
| Peak memory | 247216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1581614599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 43.rom_ctrl_stress_all_with_rand_reset.1581614599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/43.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_alert_test.2803762091 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 384162371 ps |
| CPU time | 9.59 seconds |
| Started | Oct 12 02:31:31 AM UTC 24 |
| Finished | Oct 12 02:31:42 AM UTC 24 |
| Peak memory | 229580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2803762091 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.2803762091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/44.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.173026623 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 10219089429 ps |
| CPU time | 303.29 seconds |
| Started | Oct 12 02:31:26 AM UTC 24 |
| Finished | Oct 12 02:36:33 AM UTC 24 |
| Peak memory | 263488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=173026623 -assert nopostproc +UVM_TEST NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_corrupt_sig_fatal_chk.173026623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/44.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_kmac_err_chk.3282873643 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 4161213704 ps |
| CPU time | 22.15 seconds |
| Started | Oct 12 02:31:28 AM UTC 24 |
| Finished | Oct 12 02:31:51 AM UTC 24 |
| Peak memory | 230388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3282873643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.3282873643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/44.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_max_throughput_chk.3209054519 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 304792568 ps |
| CPU time | 15.44 seconds |
| Started | Oct 12 02:31:24 AM UTC 24 |
| Finished | Oct 12 02:31:41 AM UTC 24 |
| Peak memory | 230556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209054519 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.3209054519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/44.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all.1371055468 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 576053689 ps |
| CPU time | 32.53 seconds |
| Started | Oct 12 02:31:23 AM UTC 24 |
| Finished | Oct 12 02:31:58 AM UTC 24 |
| Peak memory | 230704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=137105546 8 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all.1371055468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/44.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.2469619231 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 26586247086 ps |
| CPU time | 128.44 seconds |
| Started | Oct 12 02:31:30 AM UTC 24 |
| Finished | Oct 12 02:33:40 AM UTC 24 |
| Peak memory | 240232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2469619231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 44.rom_ctrl_stress_all_with_rand_reset.2469619231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/44.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_alert_test.1266033178 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 1585653730 ps |
| CPU time | 9.33 seconds |
| Started | Oct 12 02:31:42 AM UTC 24 |
| Finished | Oct 12 02:31:53 AM UTC 24 |
| Peak memory | 229876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266033178 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.1266033178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/45.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1112307365 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 3821347333 ps |
| CPU time | 243.17 seconds |
| Started | Oct 12 02:31:35 AM UTC 24 |
| Finished | Oct 12 02:35:42 AM UTC 24 |
| Peak memory | 259252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112307365 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_corrupt_sig_fatal_chk.1112307365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/45.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_kmac_err_chk.2756797437 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 553741994 ps |
| CPU time | 29.1 seconds |
| Started | Oct 12 02:31:35 AM UTC 24 |
| Finished | Oct 12 02:32:06 AM UTC 24 |
| Peak memory | 230028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756797437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.2756797437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/45.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_max_throughput_chk.886497918 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 311967198 ps |
| CPU time | 15.57 seconds |
| Started | Oct 12 02:31:34 AM UTC 24 |
| Finished | Oct 12 02:31:51 AM UTC 24 |
| Peak memory | 230068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=886497918 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.886497918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/45.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all.971113491 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 2074294982 ps |
| CPU time | 41.41 seconds |
| Started | Oct 12 02:31:31 AM UTC 24 |
| Finished | Oct 12 02:32:14 AM UTC 24 |
| Peak memory | 230872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971113491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all.971113491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/45.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.3824604191 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 2118590958 ps |
| CPU time | 106.52 seconds |
| Started | Oct 12 02:31:39 AM UTC 24 |
| Finished | Oct 12 02:33:28 AM UTC 24 |
| Peak memory | 241008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=3824604191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 45.rom_ctrl_stress_all_with_rand_reset.3824604191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/45.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_alert_test.946642299 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 1536506494 ps |
| CPU time | 11.49 seconds |
| Started | Oct 12 02:31:52 AM UTC 24 |
| Finished | Oct 12 02:32:05 AM UTC 24 |
| Peak memory | 230144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=946642299 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.946642299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/46.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.479041581 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 6907025357 ps |
| CPU time | 192.74 seconds |
| Started | Oct 12 02:31:46 AM UTC 24 |
| Finished | Oct 12 02:35:01 AM UTC 24 |
| Peak memory | 261320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=479041581 -assert nopostproc +UVM_TEST NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_corrupt_sig_fatal_chk.479041581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/46.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_kmac_err_chk.2370782718 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 370169842 ps |
| CPU time | 22.87 seconds |
| Started | Oct 12 02:31:47 AM UTC 24 |
| Finished | Oct 12 02:32:11 AM UTC 24 |
| Peak memory | 230216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370782718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.2370782718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/46.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_max_throughput_chk.2365470513 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 477409247 ps |
| CPU time | 12.03 seconds |
| Started | Oct 12 02:31:45 AM UTC 24 |
| Finished | Oct 12 02:31:58 AM UTC 24 |
| Peak memory | 230340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2365470513 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.2365470513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/46.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all.617218959 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 5850909554 ps |
| CPU time | 52.53 seconds |
| Started | Oct 12 02:31:42 AM UTC 24 |
| Finished | Oct 12 02:32:36 AM UTC 24 |
| Peak memory | 230764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617218959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all.617218959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/46.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.1708668688 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 3887854665 ps |
| CPU time | 177.68 seconds |
| Started | Oct 12 02:31:48 AM UTC 24 |
| Finished | Oct 12 02:34:48 AM UTC 24 |
| Peak memory | 247216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1708668688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 46.rom_ctrl_stress_all_with_rand_reset.1708668688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/46.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_alert_test.1304817103 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 351903045 ps |
| CPU time | 12.87 seconds |
| Started | Oct 12 02:31:59 AM UTC 24 |
| Finished | Oct 12 02:32:13 AM UTC 24 |
| Peak memory | 229852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1304817103 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.1304817103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/47.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2647625331 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 2565401986 ps |
| CPU time | 189.51 seconds |
| Started | Oct 12 02:31:54 AM UTC 24 |
| Finished | Oct 12 02:35:06 AM UTC 24 |
| Peak memory | 259144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647625331 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_corrupt_sig_fatal_chk.2647625331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/47.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_kmac_err_chk.3534440998 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 1415700502 ps |
| CPU time | 19.41 seconds |
| Started | Oct 12 02:31:56 AM UTC 24 |
| Finished | Oct 12 02:32:17 AM UTC 24 |
| Peak memory | 230232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3534440998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.3534440998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/47.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_max_throughput_chk.1565382167 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 558386348 ps |
| CPU time | 18.38 seconds |
| Started | Oct 12 02:31:53 AM UTC 24 |
| Finished | Oct 12 02:32:13 AM UTC 24 |
| Peak memory | 230076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565382167 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.1565382167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/47.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all.2513495452 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 779817392 ps |
| CPU time | 60.2 seconds |
| Started | Oct 12 02:31:52 AM UTC 24 |
| Finished | Oct 12 02:32:54 AM UTC 24 |
| Peak memory | 230704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251349545 2 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all.2513495452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/47.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.2459225727 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 5996701721 ps |
| CPU time | 75.07 seconds |
| Started | Oct 12 02:31:59 AM UTC 24 |
| Finished | Oct 12 02:33:16 AM UTC 24 |
| Peak memory | 237172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2459225727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 47.rom_ctrl_stress_all_with_rand_reset.2459225727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/47.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_alert_test.457457494 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 699718631 ps |
| CPU time | 12.59 seconds |
| Started | Oct 12 02:32:06 AM UTC 24 |
| Finished | Oct 12 02:32:20 AM UTC 24 |
| Peak memory | 229968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=457457494 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.457457494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/48.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1718134251 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 3875006260 ps |
| CPU time | 213.5 seconds |
| Started | Oct 12 02:32:02 AM UTC 24 |
| Finished | Oct 12 02:35:39 AM UTC 24 |
| Peak memory | 230424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718134251 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_corrupt_sig_fatal_chk.1718134251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/48.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_kmac_err_chk.1554406088 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 1943034462 ps |
| CPU time | 26.17 seconds |
| Started | Oct 12 02:32:02 AM UTC 24 |
| Finished | Oct 12 02:32:29 AM UTC 24 |
| Peak memory | 230520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1554406088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1554406088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/48.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_max_throughput_chk.4116172952 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 2027358004 ps |
| CPU time | 16.96 seconds |
| Started | Oct 12 02:32:00 AM UTC 24 |
| Finished | Oct 12 02:32:19 AM UTC 24 |
| Peak memory | 230696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116172952 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.4116172952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/48.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all.1443424326 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 241567739 ps |
| CPU time | 24.91 seconds |
| Started | Oct 12 02:32:00 AM UTC 24 |
| Finished | Oct 12 02:32:27 AM UTC 24 |
| Peak memory | 230944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144342432 6 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all.1443424326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/48.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.2362882937 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 3386183965 ps |
| CPU time | 132.34 seconds |
| Started | Oct 12 02:32:04 AM UTC 24 |
| Finished | Oct 12 02:34:19 AM UTC 24 |
| Peak memory | 247216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2362882937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 48.rom_ctrl_stress_all_with_rand_reset.2362882937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/48.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_alert_test.3937160460 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 1069757879 ps |
| CPU time | 14.55 seconds |
| Started | Oct 12 02:32:14 AM UTC 24 |
| Finished | Oct 12 02:32:30 AM UTC 24 |
| Peak memory | 229748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937160460 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.3937160460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/49.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.2841224533 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 7020020333 ps |
| CPU time | 175.83 seconds |
| Started | Oct 12 02:32:12 AM UTC 24 |
| Finished | Oct 12 02:35:10 AM UTC 24 |
| Peak memory | 259144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841224533 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_corrupt_sig_fatal_chk.2841224533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/49.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_kmac_err_chk.269551318 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 385061793 ps |
| CPU time | 24.12 seconds |
| Started | Oct 12 02:32:14 AM UTC 24 |
| Finished | Oct 12 02:32:40 AM UTC 24 |
| Peak memory | 230276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269551318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM _TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_c trl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.269551318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/49.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_max_throughput_chk.1010058162 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 766259336 ps |
| CPU time | 12.33 seconds |
| Started | Oct 12 02:32:10 AM UTC 24 |
| Finished | Oct 12 02:32:24 AM UTC 24 |
| Peak memory | 230284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010058162 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1010058162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/49.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all.4071147054 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 802612721 ps |
| CPU time | 49.15 seconds |
| Started | Oct 12 02:32:06 AM UTC 24 |
| Finished | Oct 12 02:32:57 AM UTC 24 |
| Peak memory | 230960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407114705 4 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all.4071147054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/49.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.2809588060 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 1482702198 ps |
| CPU time | 62.66 seconds |
| Started | Oct 12 02:32:14 AM UTC 24 |
| Finished | Oct 12 02:33:18 AM UTC 24 |
| Peak memory | 243056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2809588060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 49.rom_ctrl_stress_all_with_rand_reset.2809588060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/49.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_alert_test.2976808468 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 1029509821 ps |
| CPU time | 11.65 seconds |
| Started | Oct 12 02:23:47 AM UTC 24 |
| Finished | Oct 12 02:23:59 AM UTC 24 |
| Peak memory | 229776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976808468 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.2976808468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.945927161 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 15219045011 ps |
| CPU time | 272.54 seconds |
| Started | Oct 12 02:23:35 AM UTC 24 |
| Finished | Oct 12 02:28:12 AM UTC 24 |
| Peak memory | 261300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=945927161 -assert nopostproc +UVM_TEST NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_corrupt_sig_fatal_chk.945927161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_kmac_err_chk.710724459 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 5529603820 ps |
| CPU time | 21.47 seconds |
| Started | Oct 12 02:23:45 AM UTC 24 |
| Finished | Oct 12 02:24:08 AM UTC 24 |
| Peak memory | 230396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=710724459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM _TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_c trl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.710724459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_max_throughput_chk.957541099 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 226097614 ps |
| CPU time | 15.5 seconds |
| Started | Oct 12 02:23:32 AM UTC 24 |
| Finished | Oct 12 02:23:49 AM UTC 24 |
| Peak memory | 230176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957541099 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.957541099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_smoke.276461715 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 387421163 ps |
| CPU time | 16.19 seconds |
| Started | Oct 12 02:23:27 AM UTC 24 |
| Finished | Oct 12 02:23:45 AM UTC 24 |
| Peak memory | 230760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276461715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM _TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64k B-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.276461715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all.2042293056 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 2797979572 ps |
| CPU time | 22.03 seconds |
| Started | Oct 12 02:23:31 AM UTC 24 |
| Finished | Oct 12 02:23:54 AM UTC 24 |
| Peak memory | 230872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204229305 6 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all.2042293056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.1271439343 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 9826415507 ps |
| CPU time | 200.8 seconds |
| Started | Oct 12 02:23:45 AM UTC 24 |
| Finished | Oct 12 02:27:10 AM UTC 24 |
| Peak memory | 247352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1271439343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 5.rom_ctrl_stress_all_with_rand_reset.1271439343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_alert_test.154624497 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 3994287261 ps |
| CPU time | 16.4 seconds |
| Started | Oct 12 02:23:56 AM UTC 24 |
| Finished | Oct 12 02:24:14 AM UTC 24 |
| Peak memory | 229636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154624497 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.154624497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3727065484 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 20888922016 ps |
| CPU time | 279.9 seconds |
| Started | Oct 12 02:23:50 AM UTC 24 |
| Finished | Oct 12 02:28:34 AM UTC 24 |
| Peak memory | 249196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3727065484 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_corrupt_sig_fatal_chk.3727065484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_kmac_err_chk.3850296969 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 6195101584 ps |
| CPU time | 33.72 seconds |
| Started | Oct 12 02:23:50 AM UTC 24 |
| Finished | Oct 12 02:24:25 AM UTC 24 |
| Peak memory | 230424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850296969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.3850296969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_max_throughput_chk.2051138068 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 244245308 ps |
| CPU time | 15.63 seconds |
| Started | Oct 12 02:23:49 AM UTC 24 |
| Finished | Oct 12 02:24:06 AM UTC 24 |
| Peak memory | 230060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2051138068 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.2051138068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_smoke.2611105102 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 1115019337 ps |
| CPU time | 16.39 seconds |
| Started | Oct 12 02:23:47 AM UTC 24 |
| Finished | Oct 12 02:24:04 AM UTC 24 |
| Peak memory | 230456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611105102 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64 kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.2611105102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all.1335923421 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 2865104495 ps |
| CPU time | 43.05 seconds |
| Started | Oct 12 02:23:47 AM UTC 24 |
| Finished | Oct 12 02:24:31 AM UTC 24 |
| Peak memory | 230748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133592342 1 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all.1335923421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_alert_test.4223528452 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 727566145 ps |
| CPU time | 12.15 seconds |
| Started | Oct 12 02:24:15 AM UTC 24 |
| Finished | Oct 12 02:24:28 AM UTC 24 |
| Peak memory | 229984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223528452 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.4223528452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.4048861876 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 13989618548 ps |
| CPU time | 331.66 seconds |
| Started | Oct 12 02:24:07 AM UTC 24 |
| Finished | Oct 12 02:29:44 AM UTC 24 |
| Peak memory | 249132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048861876 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_corrupt_sig_fatal_chk.4048861876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_kmac_err_chk.1898131252 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 554932465 ps |
| CPU time | 32.39 seconds |
| Started | Oct 12 02:24:08 AM UTC 24 |
| Finished | Oct 12 02:24:42 AM UTC 24 |
| Peak memory | 229936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898131252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.1898131252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_max_throughput_chk.2866098349 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 310190644 ps |
| CPU time | 19.4 seconds |
| Started | Oct 12 02:24:06 AM UTC 24 |
| Finished | Oct 12 02:24:27 AM UTC 24 |
| Peak memory | 230076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866098349 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.2866098349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_smoke.178697395 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 1730088284 ps |
| CPU time | 14.55 seconds |
| Started | Oct 12 02:24:00 AM UTC 24 |
| Finished | Oct 12 02:24:16 AM UTC 24 |
| Peak memory | 230696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178697395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM _TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64k B-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.178697395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all.3689556570 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 548124294 ps |
| CPU time | 18.09 seconds |
| Started | Oct 12 02:24:05 AM UTC 24 |
| Finished | Oct 12 02:24:24 AM UTC 24 |
| Peak memory | 230616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=368955657 0 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all.3689556570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.3459530345 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 6462010034 ps |
| CPU time | 64.81 seconds |
| Started | Oct 12 02:24:12 AM UTC 24 |
| Finished | Oct 12 02:25:18 AM UTC 24 |
| Peak memory | 247224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=3459530345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 7.rom_ctrl_stress_all_with_rand_reset.3459530345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_alert_test.209474340 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 650156007 ps |
| CPU time | 12.46 seconds |
| Started | Oct 12 02:24:32 AM UTC 24 |
| Finished | Oct 12 02:24:46 AM UTC 24 |
| Peak memory | 229572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=209474340 -assert nopostproc +UVM_TESTNA ME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.209474340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1500824838 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 4989630004 ps |
| CPU time | 196.71 seconds |
| Started | Oct 12 02:24:28 AM UTC 24 |
| Finished | Oct 12 02:27:48 AM UTC 24 |
| Peak memory | 246336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500824838 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_corrupt_sig_fatal_chk.1500824838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_kmac_err_chk.582422444 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 4975799395 ps |
| CPU time | 31.06 seconds |
| Started | Oct 12 02:24:29 AM UTC 24 |
| Finished | Oct 12 02:25:01 AM UTC 24 |
| Peak memory | 230308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582422444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM _TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_c trl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.582422444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_max_throughput_chk.726722813 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 303850198 ps |
| CPU time | 18.9 seconds |
| Started | Oct 12 02:24:26 AM UTC 24 |
| Finished | Oct 12 02:24:47 AM UTC 24 |
| Peak memory | 230140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=726722813 -assert nopostproc +UVM_TESTNAME=rom_ctrl _base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.726722813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_smoke.1586781881 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 413267071 ps |
| CPU time | 9.94 seconds |
| Started | Oct 12 02:24:17 AM UTC 24 |
| Finished | Oct 12 02:24:28 AM UTC 24 |
| Peak memory | 230700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1586781881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64 kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.1586781881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all.236680262 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 1121344369 ps |
| CPU time | 51.76 seconds |
| Started | Oct 12 02:24:25 AM UTC 24 |
| Finished | Oct 12 02:25:19 AM UTC 24 |
| Peak memory | 230704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=236680262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all.236680262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.1239677770 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 2469246739 ps |
| CPU time | 171.88 seconds |
| Started | Oct 12 02:24:29 AM UTC 24 |
| Finished | Oct 12 02:27:24 AM UTC 24 |
| Peak memory | 241064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1239677770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 8.rom_ctrl_stress_all_with_rand_reset.1239677770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_alert_test.4023931775 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 207046198 ps |
| CPU time | 11.17 seconds |
| Started | Oct 12 02:24:55 AM UTC 24 |
| Finished | Oct 12 02:25:07 AM UTC 24 |
| Peak memory | 229864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4023931775 -assert nopostproc +UVM_TESTN AME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.4023931775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.3051160131 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 13663350462 ps |
| CPU time | 354.02 seconds |
| Started | Oct 12 02:24:46 AM UTC 24 |
| Finished | Oct 12 02:30:45 AM UTC 24 |
| Peak memory | 261332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051160131 -assert nopostproc +UVM_TES TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_corrupt_sig_fatal_chk.3051160131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_kmac_err_chk.3639880730 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 384361255 ps |
| CPU time | 29.15 seconds |
| Started | Oct 12 02:24:48 AM UTC 24 |
| Finished | Oct 12 02:25:18 AM UTC 24 |
| Peak memory | 230040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639880730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.3639880730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_max_throughput_chk.3601972797 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 402486616 ps |
| CPU time | 16.72 seconds |
| Started | Oct 12 02:24:43 AM UTC 24 |
| Finished | Oct 12 02:25:02 AM UTC 24 |
| Peak memory | 230580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601972797 -assert nopostproc +UVM_TESTNAME=rom_ctr l_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.3601972797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_smoke.2335880189 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 313378194 ps |
| CPU time | 10.55 seconds |
| Started | Oct 12 02:24:38 AM UTC 24 |
| Finished | Oct 12 02:24:50 AM UTC 24 |
| Peak memory | 230716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335880189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV M_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64 kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.2335880189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all.3093548366 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 3289898704 ps |
| CPU time | 50.98 seconds |
| Started | Oct 12 02:24:41 AM UTC 24 |
| Finished | Oct 12 02:25:34 AM UTC 24 |
| Peak memory | 230936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309354836 6 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all.3093548366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.2368268275 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 12139601272 ps |
| CPU time | 228.74 seconds |
| Started | Oct 12 02:24:51 AM UTC 24 |
| Finished | Oct 12 02:28:43 AM UTC 24 |
| Peak memory | 248240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2368268275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 9.rom_ctrl_stress_all_with_rand_reset.2368268275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/9.rom_ctrl_stress_all_with_rand_reset/latest |
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