| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.81 | 99.36 | 92.13 | 97.68 | 100.00 | 98.55 | 97.91 | 99.06 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP | |||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 67.54 | 67.54 | 95.16 | 95.16 | 68.82 | 68.82 | 51.90 | 51.90 | 53.33 | 53.33 | 91.30 | 91.30 | 93.73 | 93.73 | 18.50 | 18.50 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all.2455817625 |
| 82.59 | 15.06 | 95.54 | 0.38 | 77.25 | 8.43 | 76.94 | 25.04 | 53.33 | 0.00 | 92.75 | 1.45 | 95.22 | 1.49 | 87.12 | 68.62 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.65822563 |
| 88.85 | 6.25 | 95.67 | 0.13 | 79.49 | 2.25 | 76.99 | 0.05 | 93.33 | 40.00 | 93.48 | 0.72 | 95.37 | 0.15 | 87.59 | 0.47 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1867988382 |
| 92.30 | 3.45 | 95.92 | 0.25 | 84.55 | 5.06 | 86.01 | 9.02 | 100.00 | 6.67 | 95.65 | 2.17 | 95.67 | 0.30 | 88.29 | 0.70 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_kmac_err_chk.2204266141 |
| 94.28 | 1.98 | 99.11 | 3.18 | 87.92 | 3.37 | 91.68 | 5.67 | 100.00 | 0.00 | 96.74 | 1.09 | 95.97 | 0.30 | 88.52 | 0.23 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.2786064339 |
| 95.37 | 1.09 | 99.36 | 0.25 | 88.62 | 0.70 | 91.68 | 0.00 | 100.00 | 0.00 | 97.83 | 1.09 | 95.97 | 0.00 | 94.15 | 5.62 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2415683069 |
| 96.14 | 0.77 | 99.36 | 0.00 | 89.89 | 1.26 | 94.85 | 3.17 | 100.00 | 0.00 | 97.83 | 0.00 | 95.97 | 0.00 | 95.08 | 0.94 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all.1886497342 |
| 96.61 | 0.47 | 99.36 | 0.00 | 90.59 | 0.70 | 96.73 | 1.87 | 100.00 | 0.00 | 97.83 | 0.00 | 95.97 | 0.00 | 95.78 | 0.70 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1247117905 |
| 96.82 | 0.21 | 99.36 | 0.00 | 91.15 | 0.56 | 96.88 | 0.15 | 100.00 | 0.00 | 97.83 | 0.00 | 96.27 | 0.30 | 96.25 | 0.47 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_sec_cm.4289540011 |
| 96.99 | 0.17 | 99.36 | 0.00 | 91.15 | 0.00 | 96.88 | 0.00 | 100.00 | 0.00 | 97.83 | 0.00 | 96.27 | 0.00 | 97.42 | 1.17 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3987215260 |
| 97.13 | 0.14 | 99.36 | 0.00 | 91.15 | 0.00 | 96.88 | 0.00 | 100.00 | 0.00 | 97.83 | 0.00 | 97.01 | 0.75 | 97.66 | 0.23 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3213109418 |
| 97.26 | 0.13 | 99.36 | 0.00 | 91.71 | 0.56 | 97.23 | 0.35 | 100.00 | 0.00 | 97.83 | 0.00 | 97.01 | 0.00 | 97.66 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_alert_test.1574948882 |
| 97.36 | 0.10 | 99.36 | 0.00 | 91.85 | 0.14 | 97.43 | 0.20 | 100.00 | 0.00 | 98.19 | 0.36 | 97.01 | 0.00 | 97.66 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_kmac_err_chk.1367714089 |
| 97.45 | 0.09 | 99.36 | 0.00 | 91.85 | 0.00 | 97.43 | 0.00 | 100.00 | 0.00 | 98.19 | 0.00 | 97.16 | 0.15 | 98.13 | 0.47 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_max_throughput_chk.728543046 |
| 97.53 | 0.08 | 99.36 | 0.00 | 91.99 | 0.14 | 97.43 | 0.00 | 100.00 | 0.00 | 98.19 | 0.00 | 97.61 | 0.45 | 98.13 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1485675464 |
| 97.60 | 0.07 | 99.36 | 0.00 | 92.13 | 0.14 | 97.43 | 0.00 | 100.00 | 0.00 | 98.55 | 0.36 | 97.61 | 0.00 | 98.13 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_kmac_err_chk.2192169008 |
| 97.67 | 0.07 | 99.36 | 0.00 | 92.13 | 0.00 | 97.43 | 0.00 | 100.00 | 0.00 | 98.55 | 0.00 | 97.61 | 0.00 | 98.59 | 0.47 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2202844972 |
| 97.74 | 0.07 | 99.36 | 0.00 | 92.13 | 0.00 | 97.43 | 0.00 | 100.00 | 0.00 | 98.55 | 0.00 | 97.61 | 0.00 | 99.06 | 0.47 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.66251535 |
| 97.79 | 0.06 | 99.36 | 0.00 | 92.13 | 0.00 | 97.68 | 0.25 | 100.00 | 0.00 | 98.55 | 0.00 | 97.76 | 0.15 | 99.06 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all.1731215048 |
| 97.81 | 0.02 | 99.36 | 0.00 | 92.13 | 0.00 | 97.68 | 0.00 | 100.00 | 0.00 | 98.55 | 0.00 | 97.91 | 0.15 | 99.06 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1747711576 |
| Name |
|---|
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2952420424 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2158798377 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.439856517 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2831113372 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1757019950 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1126307526 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1470574664 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1746601767 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2463208706 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2233213722 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1782221029 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2458935686 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.304899325 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1340213068 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3522378814 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3007757583 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1430248233 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3535898670 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_errors.192706438 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3934805555 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3520200274 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2278364179 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2840879202 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1845858032 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1802651958 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.4178531293 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3993833910 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1822385286 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.542211103 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_errors.593106565 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.327808752 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3958995734 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_rw.778837606 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1623989870 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2065829222 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2772839676 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2713684403 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1937458879 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3928202250 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1035373457 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.327964649 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3993135090 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2088871442 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1615264067 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3123484636 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3448965730 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2270962482 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3490395820 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2818897308 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2217386242 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1733115009 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.162084918 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3691964579 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.332364673 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3242764459 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2020619929 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.935091970 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2130522794 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1674949873 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3323208354 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2820827884 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2412438975 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.4229222575 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1158577563 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3978860852 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1199936468 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3759951485 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2162098440 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2155988912 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1032408858 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1673846509 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2426293506 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1789136060 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_rw.4011631710 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.4027576199 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.73990192 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_errors.375703297 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.4262449448 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.923885827 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.117540334 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2172832478 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2507691093 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.320887267 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1291983280 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1213096564 |
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| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3627159201 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_kmac_err_chk.2816453059 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_max_throughput_chk.2688455471 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all.1961771485 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.3729744098 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_alert_test.3054263523 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.4019801696 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_kmac_err_chk.1853574314 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_max_throughput_chk.2927931408 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all.765988967 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.489402517 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_alert_test.2394683344 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1742279113 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_kmac_err_chk.4155354323 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_max_throughput_chk.2685361446 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all.1076710505 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.1581614599 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_alert_test.2803762091 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.173026623 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_kmac_err_chk.3282873643 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_max_throughput_chk.3209054519 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all.1371055468 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.2469619231 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_alert_test.1266033178 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1112307365 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_kmac_err_chk.2756797437 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_max_throughput_chk.886497918 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all.971113491 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.3824604191 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_alert_test.946642299 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.479041581 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_kmac_err_chk.2370782718 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_max_throughput_chk.2365470513 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all.617218959 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.1708668688 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_alert_test.1304817103 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2647625331 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_kmac_err_chk.3534440998 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_max_throughput_chk.1565382167 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all.2513495452 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.2459225727 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_alert_test.457457494 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1718134251 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_kmac_err_chk.1554406088 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_max_throughput_chk.4116172952 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all.1443424326 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.2362882937 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_alert_test.3937160460 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.2841224533 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_kmac_err_chk.269551318 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_max_throughput_chk.1010058162 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all.4071147054 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.2809588060 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_alert_test.2976808468 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.945927161 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_kmac_err_chk.710724459 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_max_throughput_chk.957541099 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_smoke.276461715 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all.2042293056 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.1271439343 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_alert_test.154624497 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3727065484 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_kmac_err_chk.3850296969 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_max_throughput_chk.2051138068 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_smoke.2611105102 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all.1335923421 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_alert_test.4223528452 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.4048861876 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_kmac_err_chk.1898131252 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_max_throughput_chk.2866098349 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_smoke.178697395 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all.3689556570 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.3459530345 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_alert_test.209474340 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1500824838 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_kmac_err_chk.582422444 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_max_throughput_chk.726722813 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_smoke.1586781881 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all.236680262 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.1239677770 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_alert_test.4023931775 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.3051160131 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_kmac_err_chk.3639880730 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_max_throughput_chk.3601972797 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_smoke.2335880189 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all.3093548366 |
| /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.2368268275 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_alert_test.3106358943 | Oct 12 02:22:38 AM UTC 24 | Oct 12 02:22:48 AM UTC 24 | 212438824 ps | ||
| T2 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_max_throughput_chk.4171761494 | Oct 12 02:22:38 AM UTC 24 | Oct 12 02:22:52 AM UTC 24 | 1107455809 ps | ||
| T3 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_smoke.1083260634 | Oct 12 02:22:37 AM UTC 24 | Oct 12 02:22:52 AM UTC 24 | 770281242 ps | ||
| T4 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_alert_test.3047654188 | Oct 12 02:22:39 AM UTC 24 | Oct 12 02:22:55 AM UTC 24 | 1026020747 ps | ||
| T5 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_smoke.2892267985 | Oct 12 02:22:39 AM UTC 24 | Oct 12 02:22:57 AM UTC 24 | 837082595 ps | ||
| T6 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_max_throughput_chk.3912130398 | Oct 12 02:22:38 AM UTC 24 | Oct 12 02:22:57 AM UTC 24 | 3234418500 ps | ||
| T7 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_smoke.3488953027 | Oct 12 02:22:38 AM UTC 24 | Oct 12 02:22:57 AM UTC 24 | 914087258 ps | ||
| T8 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all.2455817625 | Oct 12 02:22:37 AM UTC 24 | Oct 12 02:23:08 AM UTC 24 | 425225368 ps | ||
| T9 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_max_throughput_chk.2962496257 | Oct 12 02:22:49 AM UTC 24 | Oct 12 02:23:08 AM UTC 24 | 1111163634 ps | ||
| T10 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_kmac_err_chk.1031212695 | Oct 12 02:22:38 AM UTC 24 | Oct 12 02:23:09 AM UTC 24 | 380576108 ps | ||
| T19 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_alert_test.1574948882 | Oct 12 02:22:58 AM UTC 24 | Oct 12 02:23:12 AM UTC 24 | 727470649 ps | ||
| T11 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_kmac_err_chk.1737370575 | Oct 12 02:22:39 AM UTC 24 | Oct 12 02:23:12 AM UTC 24 | 370739644 ps | ||
| T15 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all.1731215048 | Oct 12 02:22:39 AM UTC 24 | Oct 12 02:23:13 AM UTC 24 | 575033023 ps | ||
| T17 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_smoke.3409421501 | Oct 12 02:22:58 AM UTC 24 | Oct 12 02:23:14 AM UTC 24 | 825299951 ps | ||
| T16 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all.1886497342 | Oct 12 02:22:38 AM UTC 24 | Oct 12 02:23:20 AM UTC 24 | 804137960 ps | ||
| T26 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_kmac_err_chk.1367714089 | Oct 12 02:22:53 AM UTC 24 | Oct 12 02:23:24 AM UTC 24 | 1415218903 ps | ||
| T47 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_max_throughput_chk.3089324546 | Oct 12 02:23:06 AM UTC 24 | Oct 12 02:23:24 AM UTC 24 | 968871237 ps | ||
| T28 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_alert_test.1119075780 | Oct 12 02:23:12 AM UTC 24 | Oct 12 02:23:25 AM UTC 24 | 212391923 ps | ||
| T48 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all.2068247896 | Oct 12 02:22:58 AM UTC 24 | Oct 12 02:23:31 AM UTC 24 | 338370820 ps | ||
| T70 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_smoke.3249734736 | Oct 12 02:23:13 AM UTC 24 | Oct 12 02:23:32 AM UTC 24 | 236173278 ps | ||
| T76 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_max_throughput_chk.3709618260 | Oct 12 02:23:15 AM UTC 24 | Oct 12 02:23:35 AM UTC 24 | 295027253 ps | ||
| T44 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_kmac_err_chk.94598479 | Oct 12 02:23:09 AM UTC 24 | Oct 12 02:23:44 AM UTC 24 | 2009898303 ps | ||
| T116 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_smoke.276461715 | Oct 12 02:23:27 AM UTC 24 | Oct 12 02:23:45 AM UTC 24 | 387421163 ps | ||
| T29 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_kmac_err_chk.2204266141 | Oct 12 02:23:25 AM UTC 24 | Oct 12 02:23:46 AM UTC 24 | 1414584870 ps | ||
| T54 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all.3373330141 | Oct 12 02:23:14 AM UTC 24 | Oct 12 02:23:46 AM UTC 24 | 608372263 ps | ||
| T12 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.2786064339 | Oct 12 02:22:39 AM UTC 24 | Oct 12 02:23:47 AM UTC 24 | 3950562805 ps | ||
| T61 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_max_throughput_chk.957541099 | Oct 12 02:23:32 AM UTC 24 | Oct 12 02:23:49 AM UTC 24 | 226097614 ps | ||
| T27 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_alert_test.2524963840 | Oct 12 02:23:26 AM UTC 24 | Oct 12 02:23:49 AM UTC 24 | 2036729172 ps | ||
| T62 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all.2042293056 | Oct 12 02:23:31 AM UTC 24 | Oct 12 02:23:54 AM UTC 24 | 2797979572 ps | ||
| T63 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_alert_test.2976808468 | Oct 12 02:23:47 AM UTC 24 | Oct 12 02:23:59 AM UTC 24 | 1029509821 ps | ||
| T18 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_smoke.2611105102 | Oct 12 02:23:47 AM UTC 24 | Oct 12 02:24:04 AM UTC 24 | 1115019337 ps | ||
| T64 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_max_throughput_chk.2051138068 | Oct 12 02:23:49 AM UTC 24 | Oct 12 02:24:06 AM UTC 24 | 244245308 ps | ||
| T30 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_kmac_err_chk.710724459 | Oct 12 02:23:45 AM UTC 24 | Oct 12 02:24:08 AM UTC 24 | 5529603820 ps | ||
| T65 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_alert_test.154624497 | Oct 12 02:23:56 AM UTC 24 | Oct 12 02:24:14 AM UTC 24 | 3994287261 ps | ||
| T66 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_smoke.178697395 | Oct 12 02:24:00 AM UTC 24 | Oct 12 02:24:16 AM UTC 24 | 1730088284 ps | ||
| T135 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all.3689556570 | Oct 12 02:24:05 AM UTC 24 | Oct 12 02:24:24 AM UTC 24 | 548124294 ps | ||
| T45 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_kmac_err_chk.3850296969 | Oct 12 02:23:50 AM UTC 24 | Oct 12 02:24:25 AM UTC 24 | 6195101584 ps | ||
| T113 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_max_throughput_chk.2866098349 | Oct 12 02:24:06 AM UTC 24 | Oct 12 02:24:27 AM UTC 24 | 310190644 ps | ||
| T85 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_smoke.1586781881 | Oct 12 02:24:17 AM UTC 24 | Oct 12 02:24:28 AM UTC 24 | 413267071 ps | ||
| T74 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_alert_test.4223528452 | Oct 12 02:24:15 AM UTC 24 | Oct 12 02:24:28 AM UTC 24 | 727566145 ps | ||
| T31 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all.1335923421 | Oct 12 02:23:47 AM UTC 24 | Oct 12 02:24:31 AM UTC 24 | 2865104495 ps | ||
| T46 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_kmac_err_chk.1898131252 | Oct 12 02:24:08 AM UTC 24 | Oct 12 02:24:42 AM UTC 24 | 554932465 ps | ||
| T75 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_alert_test.209474340 | Oct 12 02:24:32 AM UTC 24 | Oct 12 02:24:46 AM UTC 24 | 650156007 ps | ||
| T114 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_max_throughput_chk.726722813 | Oct 12 02:24:26 AM UTC 24 | Oct 12 02:24:47 AM UTC 24 | 303850198 ps | ||
| T134 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_smoke.2335880189 | Oct 12 02:24:38 AM UTC 24 | Oct 12 02:24:50 AM UTC 24 | 313378194 ps | ||
| T13 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.65822563 | Oct 12 02:23:09 AM UTC 24 | Oct 12 02:24:54 AM UTC 24 | 7809217736 ps | ||
| T23 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_sec_cm.2476442453 | Oct 12 02:22:58 AM UTC 24 | Oct 12 02:24:59 AM UTC 24 | 496298564 ps | ||
| T34 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_kmac_err_chk.582422444 | Oct 12 02:24:29 AM UTC 24 | Oct 12 02:25:01 AM UTC 24 | 4975799395 ps | ||
| T35 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_max_throughput_chk.728543046 | Oct 12 02:25:42 AM UTC 24 | Oct 12 02:26:02 AM UTC 24 | 1070392590 ps | ||
| T36 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_max_throughput_chk.3601972797 | Oct 12 02:24:43 AM UTC 24 | Oct 12 02:25:02 AM UTC 24 | 402486616 ps | ||
| T24 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_sec_cm.4289540011 | Oct 12 02:23:12 AM UTC 24 | Oct 12 02:25:04 AM UTC 24 | 375732184 ps | ||
| T37 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_alert_test.4023931775 | Oct 12 02:24:55 AM UTC 24 | Oct 12 02:25:07 AM UTC 24 | 207046198 ps | ||
| T14 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.3459530345 | Oct 12 02:24:12 AM UTC 24 | Oct 12 02:25:18 AM UTC 24 | 6462010034 ps | ||
| T38 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_kmac_err_chk.3639880730 | Oct 12 02:24:48 AM UTC 24 | Oct 12 02:25:18 AM UTC 24 | 384361255 ps | ||
| T39 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all.236680262 | Oct 12 02:24:25 AM UTC 24 | Oct 12 02:25:19 AM UTC 24 | 1121344369 ps | ||
| T40 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_alert_test.2236614846 | Oct 12 02:25:08 AM UTC 24 | Oct 12 02:25:21 AM UTC 24 | 377381518 ps | ||
| T25 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_sec_cm.1631598779 | Oct 12 02:23:26 AM UTC 24 | Oct 12 02:25:26 AM UTC 24 | 512925168 ps | ||
| T115 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_max_throughput_chk.3982314743 | Oct 12 02:25:02 AM UTC 24 | Oct 12 02:25:28 AM UTC 24 | 19933464258 ps | ||
| T136 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_kmac_err_chk.1790115049 | Oct 12 02:25:03 AM UTC 24 | Oct 12 02:25:31 AM UTC 24 | 2143227153 ps | ||
| T137 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_max_throughput_chk.315433241 | Oct 12 02:25:19 AM UTC 24 | Oct 12 02:25:34 AM UTC 24 | 807179314 ps | ||
| T86 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all.3093548366 | Oct 12 02:24:41 AM UTC 24 | Oct 12 02:25:34 AM UTC 24 | 3289898704 ps | ||
| T138 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all.3650800732 | Oct 12 02:25:00 AM UTC 24 | Oct 12 02:25:39 AM UTC 24 | 400092144 ps | ||
| T139 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_alert_test.219127633 | Oct 12 02:25:26 AM UTC 24 | Oct 12 02:25:40 AM UTC 24 | 370178335 ps | ||
| T140 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_max_throughput_chk.239414703 | Oct 12 02:25:29 AM UTC 24 | Oct 12 02:25:44 AM UTC 24 | 218317083 ps | ||
| T141 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_kmac_err_chk.2839993408 | Oct 12 02:25:22 AM UTC 24 | Oct 12 02:25:47 AM UTC 24 | 2013667954 ps | ||
| T87 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all.3271669885 | Oct 12 02:25:19 AM UTC 24 | Oct 12 02:25:48 AM UTC 24 | 407995018 ps | ||
| T50 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.3593188019 | Oct 12 02:25:25 AM UTC 24 | Oct 12 02:25:51 AM UTC 24 | 2816856616 ps | ||
| T142 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_alert_test.3336872386 | Oct 12 02:25:39 AM UTC 24 | Oct 12 02:25:53 AM UTC 24 | 288491899 ps | ||
| T20 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1247117905 | Oct 12 02:22:38 AM UTC 24 | Oct 12 02:26:00 AM UTC 24 | 28353142878 ps | ||
| T143 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_alert_test.1606235627 | Oct 12 02:25:50 AM UTC 24 | Oct 12 02:26:04 AM UTC 24 | 212732497 ps | ||
| T55 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.4265430815 | Oct 12 02:22:38 AM UTC 24 | Oct 12 02:26:06 AM UTC 24 | 8945171220 ps | ||
| T144 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_kmac_err_chk.317993379 | Oct 12 02:25:47 AM UTC 24 | Oct 12 02:26:09 AM UTC 24 | 700119964 ps | ||
| T145 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_kmac_err_chk.3499659468 | Oct 12 02:25:35 AM UTC 24 | Oct 12 02:26:11 AM UTC 24 | 539807374 ps | ||
| T146 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_max_throughput_chk.597783027 | Oct 12 02:25:54 AM UTC 24 | Oct 12 02:26:12 AM UTC 24 | 405957434 ps | ||
| T147 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all.4103205554 | Oct 12 02:25:27 AM UTC 24 | Oct 12 02:26:12 AM UTC 24 | 3319738018 ps | ||
| T88 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all.37992538 | Oct 12 02:25:41 AM UTC 24 | Oct 12 02:26:15 AM UTC 24 | 749050026 ps | ||
| T148 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all.3949917034 | Oct 12 02:25:52 AM UTC 24 | Oct 12 02:26:19 AM UTC 24 | 392342961 ps | ||
| T149 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_kmac_err_chk.4004341756 | Oct 12 02:26:01 AM UTC 24 | Oct 12 02:26:22 AM UTC 24 | 1261446553 ps | ||
| T150 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_max_throughput_chk.3513112618 | Oct 12 02:26:06 AM UTC 24 | Oct 12 02:26:24 AM UTC 24 | 811761031 ps | ||
| T151 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_alert_test.3020018165 | Oct 12 02:26:13 AM UTC 24 | Oct 12 02:26:25 AM UTC 24 | 2092337888 ps | ||
| T32 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_sec_cm.205725838 | Oct 12 02:22:39 AM UTC 24 | Oct 12 02:26:30 AM UTC 24 | 619847514 ps | ||
| T152 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_alert_test.1650884696 | Oct 12 02:26:05 AM UTC 24 | Oct 12 02:26:28 AM UTC 24 | 5485687194 ps | ||
| T51 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all.2743061723 | Oct 12 02:26:05 AM UTC 24 | Oct 12 02:26:31 AM UTC 24 | 2137457599 ps | ||
| T153 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_alert_test.28548941 | Oct 12 02:26:25 AM UTC 24 | Oct 12 02:26:39 AM UTC 24 | 1009362981 ps | ||
| T154 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_max_throughput_chk.1356916231 | Oct 12 02:26:19 AM UTC 24 | Oct 12 02:26:43 AM UTC 24 | 4172533089 ps | ||
| T155 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_kmac_err_chk.3691324200 | Oct 12 02:26:12 AM UTC 24 | Oct 12 02:26:44 AM UTC 24 | 1357890768 ps | ||
| T156 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_max_throughput_chk.4069011627 | Oct 12 02:26:29 AM UTC 24 | Oct 12 02:26:46 AM UTC 24 | 1216585067 ps | ||
| T56 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.2600293220 | Oct 12 02:23:25 AM UTC 24 | Oct 12 02:26:49 AM UTC 24 | 3233124765 ps | ||
| T157 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all.1670431552 | Oct 12 02:26:26 AM UTC 24 | Oct 12 02:26:53 AM UTC 24 | 406367460 ps | ||
| T52 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_kmac_err_chk.2192169008 | Oct 12 02:26:23 AM UTC 24 | Oct 12 02:26:56 AM UTC 24 | 1071539230 ps | ||
| T158 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_alert_test.1719189462 | Oct 12 02:26:41 AM UTC 24 | Oct 12 02:26:57 AM UTC 24 | 1336865684 ps | ||
| T159 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_max_throughput_chk.2489514013 | Oct 12 02:26:45 AM UTC 24 | Oct 12 02:27:00 AM UTC 24 | 4038016727 ps | ||
| T160 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_kmac_err_chk.4128219598 | Oct 12 02:26:32 AM UTC 24 | Oct 12 02:27:01 AM UTC 24 | 371144010 ps | ||
| T57 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.2265654767 | Oct 12 02:26:24 AM UTC 24 | Oct 12 02:27:04 AM UTC 24 | 5110656177 ps | ||
| T161 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_alert_test.2332606206 | Oct 12 02:26:54 AM UTC 24 | Oct 12 02:27:07 AM UTC 24 | 1138104317 ps | ||
| T58 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.1271439343 | Oct 12 02:23:45 AM UTC 24 | Oct 12 02:27:10 AM UTC 24 | 9826415507 ps | ||
| T33 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_sec_cm.924588776 | Oct 12 02:22:38 AM UTC 24 | Oct 12 02:27:11 AM UTC 24 | 2030278624 ps | ||
| T162 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all.3224309350 | Oct 12 02:26:43 AM UTC 24 | Oct 12 02:27:11 AM UTC 24 | 934857839 ps | ||
| T163 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all.294444419 | Oct 12 02:26:17 AM UTC 24 | Oct 12 02:27:11 AM UTC 24 | 837876198 ps | ||
| T164 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_max_throughput_chk.3245490085 | Oct 12 02:26:58 AM UTC 24 | Oct 12 02:27:14 AM UTC 24 | 215305801 ps | ||
| T165 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_alert_test.975940633 | Oct 12 02:27:04 AM UTC 24 | Oct 12 02:27:15 AM UTC 24 | 376974841 ps | ||
| T166 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_kmac_err_chk.438579956 | Oct 12 02:26:47 AM UTC 24 | Oct 12 02:27:21 AM UTC 24 | 2096697105 ps | ||
| T167 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all.3031666014 | Oct 12 02:26:57 AM UTC 24 | Oct 12 02:27:24 AM UTC 24 | 348366560 ps | ||
| T59 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.1239677770 | Oct 12 02:24:29 AM UTC 24 | Oct 12 02:27:24 AM UTC 24 | 2469246739 ps | ||
| T168 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all.1840492073 | Oct 12 02:27:08 AM UTC 24 | Oct 12 02:27:28 AM UTC 24 | 845578590 ps | ||
| T169 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_alert_test.3778077906 | Oct 12 02:27:15 AM UTC 24 | Oct 12 02:27:29 AM UTC 24 | 608810658 ps | ||
| T60 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.3700941031 | Oct 12 02:22:56 AM UTC 24 | Oct 12 02:27:31 AM UTC 24 | 79657793294 ps | ||
| T21 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3087131344 | Oct 12 02:22:53 AM UTC 24 | Oct 12 02:27:31 AM UTC 24 | 14974725227 ps | ||
| T170 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_kmac_err_chk.10369052 | Oct 12 02:27:12 AM UTC 24 | Oct 12 02:27:33 AM UTC 24 | 371423476 ps | ||
| T171 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_max_throughput_chk.3791257345 | Oct 12 02:27:11 AM UTC 24 | Oct 12 02:27:33 AM UTC 24 | 19875998566 ps | ||
| T172 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_max_throughput_chk.4220872931 | Oct 12 02:27:16 AM UTC 24 | Oct 12 02:27:34 AM UTC 24 | 1061769474 ps | ||
| T173 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_kmac_err_chk.2907017737 | Oct 12 02:27:02 AM UTC 24 | Oct 12 02:27:35 AM UTC 24 | 2012600404 ps | ||
| T174 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_alert_test.826495350 | Oct 12 02:27:28 AM UTC 24 | Oct 12 02:27:37 AM UTC 24 | 1869209710 ps | ||
| T175 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.2564349982 | Oct 12 02:25:35 AM UTC 24 | Oct 12 02:27:41 AM UTC 24 | 2650304876 ps | ||
| T176 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all.1112536318 | Oct 12 02:27:15 AM UTC 24 | Oct 12 02:27:45 AM UTC 24 | 2380237105 ps | ||
| T177 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.950987817 | Oct 12 02:25:47 AM UTC 24 | Oct 12 02:27:45 AM UTC 24 | 2178896021 ps | ||
| T22 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1500824838 | Oct 12 02:24:28 AM UTC 24 | Oct 12 02:27:48 AM UTC 24 | 4989630004 ps | ||
| T178 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.2515655901 | Oct 12 02:26:39 AM UTC 24 | Oct 12 02:27:48 AM UTC 24 | 2169136442 ps | ||
| T179 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_max_throughput_chk.3555740298 | Oct 12 02:27:36 AM UTC 24 | Oct 12 02:27:48 AM UTC 24 | 567625310 ps | ||
| T180 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_alert_test.907671439 | Oct 12 02:27:34 AM UTC 24 | Oct 12 02:27:49 AM UTC 24 | 1071080179 ps | ||
| T181 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_max_throughput_chk.3956954143 | Oct 12 02:27:32 AM UTC 24 | Oct 12 02:27:49 AM UTC 24 | 3496003186 ps | ||
| T182 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_kmac_err_chk.1176829669 | Oct 12 02:27:24 AM UTC 24 | Oct 12 02:27:49 AM UTC 24 | 2010920068 ps | ||
| T183 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all.879917360 | Oct 12 02:27:29 AM UTC 24 | Oct 12 02:27:51 AM UTC 24 | 806399244 ps | ||
| T184 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all.1151405774 | Oct 12 02:27:35 AM UTC 24 | Oct 12 02:27:52 AM UTC 24 | 319995366 ps | ||
| T41 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1867988382 | Oct 12 02:25:03 AM UTC 24 | Oct 12 02:27:58 AM UTC 24 | 2529221798 ps | ||
| T185 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.761851820 | Oct 12 02:25:05 AM UTC 24 | Oct 12 02:27:59 AM UTC 24 | 16897085989 ps | ||
| T186 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_alert_test.4121588512 | Oct 12 02:27:45 AM UTC 24 | Oct 12 02:28:01 AM UTC 24 | 541828369 ps | ||
| T187 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_max_throughput_chk.2662917829 | Oct 12 02:27:48 AM UTC 24 | Oct 12 02:28:04 AM UTC 24 | 307731574 ps | ||
| T188 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_alert_test.2888541314 | Oct 12 02:27:50 AM UTC 24 | Oct 12 02:28:05 AM UTC 24 | 541125843 ps | ||
| T189 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_kmac_err_chk.2719456661 | Oct 12 02:27:41 AM UTC 24 | Oct 12 02:28:06 AM UTC 24 | 1375050383 ps | ||
| T190 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_max_throughput_chk.859309888 | Oct 12 02:27:52 AM UTC 24 | Oct 12 02:28:09 AM UTC 24 | 558007239 ps | ||
| T191 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_kmac_err_chk.4127160663 | Oct 12 02:27:34 AM UTC 24 | Oct 12 02:28:10 AM UTC 24 | 534298225 ps | ||
| T42 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.945927161 | Oct 12 02:23:35 AM UTC 24 | Oct 12 02:28:12 AM UTC 24 | 15219045011 ps | ||
| T192 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_kmac_err_chk.1000008983 | Oct 12 02:27:50 AM UTC 24 | Oct 12 02:28:13 AM UTC 24 | 373895921 ps | ||
| T193 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_alert_test.3082830649 | Oct 12 02:28:02 AM UTC 24 | Oct 12 02:28:16 AM UTC 24 | 1028936234 ps | ||
| T43 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1736944937 | Oct 12 02:22:39 AM UTC 24 | Oct 12 02:28:19 AM UTC 24 | 16818015014 ps | ||
| T194 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all.255001993 | Oct 12 02:27:51 AM UTC 24 | Oct 12 02:28:19 AM UTC 24 | 2731364097 ps | ||
| T49 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1319928772 | Oct 12 02:25:32 AM UTC 24 | Oct 12 02:28:19 AM UTC 24 | 5412559242 ps | ||
| T195 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all.1680482629 | Oct 12 02:28:04 AM UTC 24 | Oct 12 02:28:22 AM UTC 24 | 642077690 ps | ||
| T196 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_alert_test.1846571782 | Oct 12 02:28:13 AM UTC 24 | Oct 12 02:28:25 AM UTC 24 | 1009189864 ps | ||
| T197 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_max_throughput_chk.587998735 | Oct 12 02:28:05 AM UTC 24 | Oct 12 02:28:26 AM UTC 24 | 314163348 ps | ||
| T198 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_kmac_err_chk.2005514839 | Oct 12 02:27:58 AM UTC 24 | Oct 12 02:28:29 AM UTC 24 | 2012369441 ps | ||
| T199 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_kmac_err_chk.3432167543 | Oct 12 02:28:10 AM UTC 24 | Oct 12 02:28:30 AM UTC 24 | 1414077647 ps | ||
| T200 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2623313759 | Oct 12 02:23:21 AM UTC 24 | Oct 12 02:28:32 AM UTC 24 | 4896776701 ps | ||
| T201 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3727065484 | Oct 12 02:23:50 AM UTC 24 | Oct 12 02:28:34 AM UTC 24 | 20888922016 ps | ||
| T202 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_max_throughput_chk.621525258 | Oct 12 02:28:16 AM UTC 24 | Oct 12 02:28:35 AM UTC 24 | 1061329269 ps | ||
| T203 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_alert_test.3951493133 | Oct 12 02:28:22 AM UTC 24 | Oct 12 02:28:38 AM UTC 24 | 1024836945 ps | ||
| T204 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all.3584589111 | Oct 12 02:28:25 AM UTC 24 | Oct 12 02:28:40 AM UTC 24 | 827119269 ps | ||
| T205 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.2368268275 | Oct 12 02:24:51 AM UTC 24 | Oct 12 02:28:43 AM UTC 24 | 12139601272 ps | ||
| T206 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.2513058422 | Oct 12 02:27:03 AM UTC 24 | Oct 12 02:28:43 AM UTC 24 | 27647627360 ps | ||
| T207 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all.1095097692 | Oct 12 02:27:46 AM UTC 24 | Oct 12 02:28:44 AM UTC 24 | 828467745 ps | ||
| T208 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_max_throughput_chk.1138608301 | Oct 12 02:28:27 AM UTC 24 | Oct 12 02:28:46 AM UTC 24 | 222377679 ps | ||
| T209 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.3599478141 | Oct 12 02:27:43 AM UTC 24 | Oct 12 02:28:47 AM UTC 24 | 11272399510 ps | ||
| T210 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all.1330041262 | Oct 12 02:28:14 AM UTC 24 | Oct 12 02:28:49 AM UTC 24 | 395896299 ps | ||
| T211 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.1734057823 | Oct 12 02:26:03 AM UTC 24 | Oct 12 02:28:49 AM UTC 24 | 3220965966 ps | ||
| T212 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_alert_test.3974913440 | Oct 12 02:28:35 AM UTC 24 | Oct 12 02:28:50 AM UTC 24 | 295788000 ps | ||
| T213 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_kmac_err_chk.2552401414 | Oct 12 02:28:19 AM UTC 24 | Oct 12 02:28:50 AM UTC 24 | 380734376 ps | ||
| T214 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_max_throughput_chk.432977308 | Oct 12 02:28:39 AM UTC 24 | Oct 12 02:28:51 AM UTC 24 | 222791505 ps | ||
| T215 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_alert_test.1830118792 | Oct 12 02:28:45 AM UTC 24 | Oct 12 02:28:56 AM UTC 24 | 383618454 ps | ||
| T53 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_kmac_err_chk.432904912 | Oct 12 02:28:31 AM UTC 24 | Oct 12 02:29:00 AM UTC 24 | 2094451159 ps | ||
| T216 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.1556999759 | Oct 12 02:26:12 AM UTC 24 | Oct 12 02:29:00 AM UTC 24 | 5939961883 ps | ||
| T217 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_max_throughput_chk.166834506 | Oct 12 02:28:48 AM UTC 24 | Oct 12 02:29:01 AM UTC 24 | 1119067820 ps | ||
| T218 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_alert_test.1367271975 | Oct 12 02:28:51 AM UTC 24 | Oct 12 02:29:03 AM UTC 24 | 1217135410 ps | ||
| T219 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.1872534351 | Oct 12 02:27:50 AM UTC 24 | Oct 12 02:29:08 AM UTC 24 | 16935469230 ps | ||
| T220 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all.3735807722 | Oct 12 02:28:47 AM UTC 24 | Oct 12 02:29:13 AM UTC 24 | 674644929 ps | ||
| T221 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all.139742699 | Oct 12 02:28:36 AM UTC 24 | Oct 12 02:29:13 AM UTC 24 | 384825057 ps | ||
| T222 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_max_throughput_chk.120981502 | Oct 12 02:28:57 AM UTC 24 | Oct 12 02:29:15 AM UTC 24 | 1100842895 ps | ||
| T223 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_kmac_err_chk.3807470701 | Oct 12 02:28:43 AM UTC 24 | Oct 12 02:29:15 AM UTC 24 | 7932677818 ps | ||
| T224 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_kmac_err_chk.4068509533 | Oct 12 02:28:50 AM UTC 24 | Oct 12 02:29:16 AM UTC 24 | 1538783509 ps | ||
| T225 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_alert_test.410651755 | Oct 12 02:29:04 AM UTC 24 | Oct 12 02:29:21 AM UTC 24 | 297527794 ps | ||
| T226 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_kmac_err_chk.1866309976 | Oct 12 02:29:01 AM UTC 24 | Oct 12 02:29:25 AM UTC 24 | 741616955 ps | ||
| T227 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1697774084 | Oct 12 02:26:10 AM UTC 24 | Oct 12 02:29:28 AM UTC 24 | 9255682428 ps | ||
| T228 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_alert_test.2397679255 | Oct 12 02:29:17 AM UTC 24 | Oct 12 02:29:29 AM UTC 24 | 1538703211 ps | ||
| T229 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.786584151 | Oct 12 02:25:19 AM UTC 24 | Oct 12 02:29:31 AM UTC 24 | 5949917916 ps | ||
| T230 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_max_throughput_chk.1180582758 | Oct 12 02:29:14 AM UTC 24 | Oct 12 02:29:31 AM UTC 24 | 232976804 ps | ||
| T231 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2832343636 | Oct 12 02:26:20 AM UTC 24 | Oct 12 02:29:32 AM UTC 24 | 1654795696 ps | ||
| T232 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all.1578489672 | Oct 12 02:28:52 AM UTC 24 | Oct 12 02:29:33 AM UTC 24 | 731777040 ps | ||
| T233 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.3204129078 | Oct 12 02:28:11 AM UTC 24 | Oct 12 02:29:35 AM UTC 24 | 1955124363 ps | ||
| T234 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_max_throughput_chk.1814030129 | Oct 12 02:29:26 AM UTC 24 | Oct 12 02:29:40 AM UTC 24 | 797275127 ps | ||
| T235 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_alert_test.2625319601 | Oct 12 02:29:32 AM UTC 24 | Oct 12 02:29:41 AM UTC 24 | 699372153 ps | ||
| T236 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.4048861876 | Oct 12 02:24:07 AM UTC 24 | Oct 12 02:29:44 AM UTC 24 | 13989618548 ps | ||
| T237 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_kmac_err_chk.1424123486 | Oct 12 02:29:15 AM UTC 24 | Oct 12 02:29:51 AM UTC 24 | 534559986 ps | ||
| T238 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all.3386534861 | Oct 12 02:29:21 AM UTC 24 | Oct 12 02:29:52 AM UTC 24 | 271818520 ps | ||
| T239 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_max_throughput_chk.4058695173 | Oct 12 02:29:34 AM UTC 24 | Oct 12 02:29:52 AM UTC 24 | 1104347885 ps | ||
| T240 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.537255990 | Oct 12 02:27:12 AM UTC 24 | Oct 12 02:29:53 AM UTC 24 | 6439182560 ps | ||
| T241 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_kmac_err_chk.3293642547 | Oct 12 02:29:30 AM UTC 24 | Oct 12 02:30:00 AM UTC 24 | 2788806095 ps | ||
| T242 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_alert_test.2914968389 | Oct 12 02:29:44 AM UTC 24 | Oct 12 02:30:00 AM UTC 24 | 555092306 ps | ||
| T131 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.2959765998 | Oct 12 02:26:50 AM UTC 24 | Oct 12 02:30:04 AM UTC 24 | 5097092783 ps | ||
| T243 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2859024470 | Oct 12 02:26:31 AM UTC 24 | Oct 12 02:30:04 AM UTC 24 | 55874869066 ps | ||
| T244 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.1442436052 | Oct 12 02:28:44 AM UTC 24 | Oct 12 02:30:08 AM UTC 24 | 3683706466 ps | ||
| T245 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all.2074041689 | Oct 12 02:29:09 AM UTC 24 | Oct 12 02:30:10 AM UTC 24 | 2087156877 ps | ||
| T246 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.3526285285 | Oct 12 02:27:34 AM UTC 24 | Oct 12 02:30:10 AM UTC 24 | 3613059009 ps | ||
| T247 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_max_throughput_chk.3627747325 | Oct 12 02:29:53 AM UTC 24 | Oct 12 02:30:10 AM UTC 24 | 219814880 ps | ||
| T248 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_alert_test.10577264 | Oct 12 02:30:01 AM UTC 24 | Oct 12 02:30:15 AM UTC 24 | 589294165 ps | ||
| T249 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_kmac_err_chk.2092575732 | Oct 12 02:29:41 AM UTC 24 | Oct 12 02:30:17 AM UTC 24 | 2190710595 ps | ||
| T250 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_kmac_err_chk.2107258148 | Oct 12 02:29:54 AM UTC 24 | Oct 12 02:30:21 AM UTC 24 | 4979631609 ps | ||
| T251 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all.1167381686 | Oct 12 02:30:04 AM UTC 24 | Oct 12 02:30:24 AM UTC 24 | 606243114 ps | ||
| T252 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_max_throughput_chk.124646972 | Oct 12 02:30:05 AM UTC 24 | Oct 12 02:30:24 AM UTC 24 | 224554622 ps | ||
| T253 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.46717351 | Oct 12 02:29:02 AM UTC 24 | Oct 12 02:30:24 AM UTC 24 | 1833153202 ps | ||
| T254 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all.2877413997 | Oct 12 02:29:33 AM UTC 24 | Oct 12 02:30:25 AM UTC 24 | 1601710125 ps | ||
| T255 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_alert_test.567383078 | Oct 12 02:30:12 AM UTC 24 | Oct 12 02:30:26 AM UTC 24 | 212559954 ps | ||
| T256 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.47567319 | Oct 12 02:29:16 AM UTC 24 | Oct 12 02:30:32 AM UTC 24 | 14361109056 ps | ||
| T257 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_max_throughput_chk.3801157646 | Oct 12 02:30:18 AM UTC 24 | Oct 12 02:30:35 AM UTC 24 | 755241625 ps | ||
| T258 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.939998216 | Oct 12 02:27:38 AM UTC 24 | Oct 12 02:30:36 AM UTC 24 | 15205642215 ps | ||
| T259 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_alert_test.1114335181 | Oct 12 02:30:25 AM UTC 24 | Oct 12 02:30:40 AM UTC 24 | 239552839 ps | ||
| T260 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3753434949 | Oct 12 02:27:22 AM UTC 24 | Oct 12 02:30:41 AM UTC 24 | 4696143927 ps | ||
| T261 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.2439792358 | Oct 12 02:27:25 AM UTC 24 | Oct 12 02:30:42 AM UTC 24 | 12963804440 ps | ||
| T262 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_kmac_err_chk.308376953 | Oct 12 02:30:10 AM UTC 24 | Oct 12 02:30:42 AM UTC 24 | 383995121 ps | ||
| T263 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.1584620205 | Oct 12 02:29:42 AM UTC 24 | Oct 12 02:30:44 AM UTC 24 | 14601816061 ps | ||
| T264 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_max_throughput_chk.2714989855 | Oct 12 02:30:26 AM UTC 24 | Oct 12 02:30:45 AM UTC 24 | 221353824 ps | ||
| T265 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.3051160131 | Oct 12 02:24:46 AM UTC 24 | Oct 12 02:30:45 AM UTC 24 | 13663350462 ps | ||
| T266 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.4105028368 | Oct 12 02:27:33 AM UTC 24 | Oct 12 02:30:49 AM UTC 24 | 4918503899 ps | ||
| T267 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_alert_test.3452158510 | Oct 12 02:30:41 AM UTC 24 | Oct 12 02:30:51 AM UTC 24 | 216238280 ps | ||
| T268 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_kmac_err_chk.29527170 | Oct 12 02:30:25 AM UTC 24 | Oct 12 02:30:52 AM UTC 24 | 2101931409 ps | ||
| T269 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_max_throughput_chk.2443019109 | Oct 12 02:30:43 AM UTC 24 | Oct 12 02:30:56 AM UTC 24 | 565087777 ps | ||
| T270 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all.2180189273 | Oct 12 02:29:53 AM UTC 24 | Oct 12 02:30:56 AM UTC 24 | 853567085 ps | ||
| T271 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_alert_test.1366265023 | Oct 12 02:30:46 AM UTC 24 | Oct 12 02:30:56 AM UTC 24 | 212616645 ps | ||
| T272 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_kmac_err_chk.768176769 | Oct 12 02:30:43 AM UTC 24 | Oct 12 02:31:06 AM UTC 24 | 2021076605 ps | ||
| T273 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_max_throughput_chk.3025437413 | Oct 12 02:30:48 AM UTC 24 | Oct 12 02:31:08 AM UTC 24 | 311034332 ps | ||
| T274 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all.229758249 | Oct 12 02:30:16 AM UTC 24 | Oct 12 02:31:09 AM UTC 24 | 6164399641 ps | ||
| T275 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_kmac_err_chk.1517908807 | Oct 12 02:30:36 AM UTC 24 | Oct 12 02:31:10 AM UTC 24 | 559576492 ps | ||
| T276 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2769018219 | Oct 12 02:25:44 AM UTC 24 | Oct 12 02:31:11 AM UTC 24 | 5353404197 ps | ||
| T277 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_alert_test.3599674812 | Oct 12 02:30:57 AM UTC 24 | Oct 12 02:31:11 AM UTC 24 | 294631035 ps | ||
| T278 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_max_throughput_chk.2688455471 | Oct 12 02:30:57 AM UTC 24 | Oct 12 02:31:16 AM UTC 24 | 299815119 ps | ||
| T279 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.2685875287 | Oct 12 02:28:51 AM UTC 24 | Oct 12 02:31:18 AM UTC 24 | 14264290666 ps | ||
| T280 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_kmac_err_chk.2933838192 | Oct 12 02:30:52 AM UTC 24 | Oct 12 02:31:18 AM UTC 24 | 727955814 ps | ||
| T281 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all.1690550710 | Oct 12 02:30:46 AM UTC 24 | Oct 12 02:31:20 AM UTC 24 | 2152332316 ps | ||
| T282 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.3773411931 | Oct 12 02:29:32 AM UTC 24 | Oct 12 02:31:21 AM UTC 24 | 4302343367 ps | ||
| T283 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.878801987 | Oct 12 02:27:59 AM UTC 24 | Oct 12 02:31:22 AM UTC 24 | 3907143584 ps | ||
| T284 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all.2025921591 | Oct 12 02:30:42 AM UTC 24 | Oct 12 02:31:23 AM UTC 24 | 647694362 ps | ||
| T285 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_alert_test.2743864130 | Oct 12 02:31:08 AM UTC 24 | Oct 12 02:31:24 AM UTC 24 | 1068322560 ps | ||
| T286 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_max_throughput_chk.2927931408 | Oct 12 02:31:10 AM UTC 24 | Oct 12 02:31:27 AM UTC 24 | 396421211 ps | ||
| T287 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all.765988967 | Oct 12 02:31:10 AM UTC 24 | Oct 12 02:31:29 AM UTC 24 | 432651939 ps | ||
| T288 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_kmac_err_chk.2816453059 | Oct 12 02:31:04 AM UTC 24 | Oct 12 02:31:30 AM UTC 24 | 1276220320 ps | ||
| T289 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_alert_test.3054263523 | Oct 12 02:31:17 AM UTC 24 | Oct 12 02:31:30 AM UTC 24 | 300727116 ps | ||
| T290 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_max_throughput_chk.2685361446 | Oct 12 02:31:19 AM UTC 24 | Oct 12 02:31:33 AM UTC 24 | 389473247 ps | ||
| T291 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.328120106 | Oct 12 02:30:12 AM UTC 24 | Oct 12 02:31:34 AM UTC 24 | 3340076381 ps | ||
| T292 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_alert_test.2394683344 | Oct 12 02:31:21 AM UTC 24 | Oct 12 02:31:35 AM UTC 24 | 708056344 ps | ||
| T293 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_kmac_err_chk.1853574314 | Oct 12 02:31:12 AM UTC 24 | Oct 12 02:31:38 AM UTC 24 | 535607081 ps | ||
| T294 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_max_throughput_chk.3209054519 | Oct 12 02:31:24 AM UTC 24 | Oct 12 02:31:41 AM UTC 24 | 304792568 ps | ||
| T295 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_alert_test.2803762091 | Oct 12 02:31:31 AM UTC 24 | Oct 12 02:31:42 AM UTC 24 | 384162371 ps | ||
| T296 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all.3721301435 | Oct 12 02:30:25 AM UTC 24 | Oct 12 02:31:44 AM UTC 24 | 16526968637 ps | ||
| T297 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_kmac_err_chk.4155354323 | Oct 12 02:31:21 AM UTC 24 | Oct 12 02:31:45 AM UTC 24 | 2576639067 ps | ||
| T298 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2705920270 | Oct 12 02:23:09 AM UTC 24 | Oct 12 02:31:47 AM UTC 24 | 50921391897 ps | ||
| T299 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_max_throughput_chk.886497918 | Oct 12 02:31:34 AM UTC 24 | Oct 12 02:31:51 AM UTC 24 | 311967198 ps | ||
| T300 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_kmac_err_chk.3282873643 | Oct 12 02:31:28 AM UTC 24 | Oct 12 02:31:51 AM UTC 24 | 4161213704 ps | ||
| T301 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.366078204 | Oct 12 02:30:01 AM UTC 24 | Oct 12 02:31:53 AM UTC 24 | 2144849590 ps | ||
| T302 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_alert_test.1266033178 | Oct 12 02:31:42 AM UTC 24 | Oct 12 02:31:53 AM UTC 24 | 1585653730 ps | ||
| T303 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3424684646 | Oct 12 02:25:54 AM UTC 24 | Oct 12 02:31:54 AM UTC 24 | 4530940373 ps | ||
| T304 | /workspaces/repo/scratch/os_regression_2024_10_11/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all.1371055468 | Oct 12 02:31:23 AM UTC 24 | Oct 12 02:31:58 AM UTC 24 | 576053689 ps |
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