| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.83 | 99.36 | 92.28 | 97.68 | 100.00 | 98.55 | 97.91 | 99.06 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP | |||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 63.01 | 63.01 | 94.78 | 94.78 | 70.51 | 70.51 | 40.43 | 40.43 | 40.00 | 40.00 | 89.86 | 89.86 | 93.58 | 93.58 | 11.94 | 11.94 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_smoke.145564271 |
| 78.77 | 15.76 | 95.29 | 0.51 | 77.11 | 6.60 | 63.87 | 23.44 | 46.67 | 6.67 | 91.67 | 1.81 | 95.07 | 1.49 | 81.73 | 69.79 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.2123690098 |
| 84.84 | 6.06 | 95.67 | 0.38 | 83.99 | 6.88 | 79.86 | 15.99 | 60.00 | 13.33 | 93.48 | 1.81 | 95.37 | 0.30 | 85.48 | 3.75 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all.910764996 |
| 89.95 | 5.12 | 95.67 | 0.00 | 85.96 | 1.97 | 79.86 | 0.00 | 93.33 | 33.33 | 93.84 | 0.36 | 95.52 | 0.15 | 85.48 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1195275758 |
| 92.48 | 2.53 | 95.92 | 0.25 | 86.94 | 0.98 | 86.63 | 6.77 | 100.00 | 6.67 | 95.65 | 1.81 | 95.82 | 0.30 | 86.42 | 0.94 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_kmac_err_chk.2557228168 |
| 94.25 | 1.77 | 99.11 | 3.18 | 88.20 | 1.26 | 92.23 | 5.60 | 100.00 | 0.00 | 96.74 | 1.09 | 96.12 | 0.30 | 87.35 | 0.94 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.369555950 |
| 95.31 | 1.06 | 99.36 | 0.25 | 88.90 | 0.70 | 92.23 | 0.00 | 100.00 | 0.00 | 97.83 | 1.09 | 96.12 | 0.00 | 92.74 | 5.39 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1461963372 |
| 95.88 | 0.56 | 99.36 | 0.00 | 89.04 | 0.14 | 94.63 | 2.40 | 100.00 | 0.00 | 97.83 | 0.00 | 96.12 | 0.00 | 94.15 | 1.41 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.3343779602 |
| 96.26 | 0.39 | 99.36 | 0.00 | 89.75 | 0.70 | 94.93 | 0.30 | 100.00 | 0.00 | 97.83 | 0.00 | 96.42 | 0.30 | 95.55 | 1.41 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_sec_cm.850288195 |
| 96.53 | 0.27 | 99.36 | 0.00 | 90.87 | 1.12 | 95.48 | 0.55 | 100.00 | 0.00 | 97.83 | 0.00 | 96.42 | 0.00 | 95.78 | 0.23 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_alert_test.2188608963 |
| 96.74 | 0.21 | 99.36 | 0.00 | 90.87 | 0.00 | 96.93 | 1.45 | 100.00 | 0.00 | 97.83 | 0.00 | 96.42 | 0.00 | 95.78 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.2857948248 |
| 96.94 | 0.20 | 99.36 | 0.00 | 90.87 | 0.00 | 96.93 | 0.00 | 100.00 | 0.00 | 97.83 | 0.00 | 96.42 | 0.00 | 97.19 | 1.41 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3918378673 |
| 97.12 | 0.17 | 99.36 | 0.00 | 90.87 | 0.00 | 96.93 | 0.00 | 100.00 | 0.00 | 97.83 | 0.00 | 97.16 | 0.75 | 97.66 | 0.47 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1577574826 |
| 97.23 | 0.11 | 99.36 | 0.00 | 90.87 | 0.00 | 97.23 | 0.30 | 100.00 | 0.00 | 97.83 | 0.00 | 97.16 | 0.00 | 98.13 | 0.47 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all.4040198950 |
| 97.33 | 0.10 | 99.36 | 0.00 | 91.57 | 0.70 | 97.25 | 0.02 | 100.00 | 0.00 | 97.83 | 0.00 | 97.16 | 0.00 | 98.13 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.965910535 |
| 97.43 | 0.10 | 99.36 | 0.00 | 91.71 | 0.14 | 97.43 | 0.17 | 100.00 | 0.00 | 98.19 | 0.36 | 97.16 | 0.00 | 98.13 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_kmac_err_chk.1972938286 |
| 97.52 | 0.09 | 99.36 | 0.00 | 91.85 | 0.14 | 97.55 | 0.12 | 100.00 | 0.00 | 98.55 | 0.36 | 97.16 | 0.00 | 98.13 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_kmac_err_chk.3367949398 |
| 97.60 | 0.09 | 99.36 | 0.00 | 91.85 | 0.00 | 97.55 | 0.00 | 100.00 | 0.00 | 98.55 | 0.00 | 97.76 | 0.60 | 98.13 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2198048936 |
| 97.67 | 0.07 | 99.36 | 0.00 | 91.85 | 0.00 | 97.55 | 0.00 | 100.00 | 0.00 | 98.55 | 0.00 | 97.76 | 0.00 | 98.59 | 0.47 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2787853928 |
| 97.73 | 0.07 | 99.36 | 0.00 | 91.85 | 0.00 | 97.55 | 0.00 | 100.00 | 0.00 | 98.55 | 0.00 | 97.76 | 0.00 | 99.06 | 0.47 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1602778047 |
| 97.77 | 0.03 | 99.36 | 0.00 | 91.85 | 0.00 | 97.63 | 0.07 | 100.00 | 0.00 | 98.55 | 0.00 | 97.91 | 0.15 | 99.06 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_max_throughput_chk.1962073947 |
| 97.79 | 0.02 | 99.36 | 0.00 | 91.99 | 0.14 | 97.65 | 0.02 | 100.00 | 0.00 | 98.55 | 0.00 | 97.91 | 0.00 | 99.06 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all.1097239750 |
| 97.81 | 0.02 | 99.36 | 0.00 | 92.13 | 0.14 | 97.65 | 0.00 | 100.00 | 0.00 | 98.55 | 0.00 | 97.91 | 0.00 | 99.06 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.311980380 |
| 97.83 | 0.02 | 99.36 | 0.00 | 92.28 | 0.14 | 97.65 | 0.00 | 100.00 | 0.00 | 98.55 | 0.00 | 97.91 | 0.00 | 99.06 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.3145023560 |
| 97.83 | 0.01 | 99.36 | 0.00 | 92.28 | 0.00 | 97.68 | 0.02 | 100.00 | 0.00 | 98.55 | 0.00 | 97.91 | 0.00 | 99.06 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all.170464885 |
| Name |
|---|
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2997353498 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.476858963 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1061056553 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_csr_rw.725371091 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.715887087 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1312077947 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.4056608155 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3897931291 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2653361202 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.482284221 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2910777710 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2115647603 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3333486194 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1763845643 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3942814063 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3798321063 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2375715061 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3159998160 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.4118885554 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1906776849 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3142945084 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2667348646 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1371614471 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2491542332 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2302474064 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1770614178 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.4226701880 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1717203024 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3061001989 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2200819009 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.4278015887 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2468578461 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2885002352 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2142706628 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2565047082 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3931122118 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_csr_rw.4023142875 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.70524319 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3226786316 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3503912964 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2741044595 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.581634334 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_csr_rw.941290533 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3170928149 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.542306216 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2958872739 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1328375725 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.47985722 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_csr_rw.130730057 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2219127711 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1831506364 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1472413147 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.746735335 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2652191985 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_csr_rw.365297127 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.4066923725 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3574946431 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1630338852 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1472146265 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2645110932 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3015382258 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2627150145 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3165603797 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3149472058 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1197665062 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3292461284 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1828047607 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.251996400 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_errors.885892403 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2311967215 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1615115460 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_csr_rw.212965884 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1453736618 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.297495462 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_errors.37925362 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2098120410 |
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| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_max_throughput_chk.3332117383 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_smoke.681394320 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all.3660632632 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_alert_test.927473859 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.2796880226 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_kmac_err_chk.2279352372 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_max_throughput_chk.1587356886 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all.5017466 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.1889408247 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_alert_test.4101948431 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1358481514 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_kmac_err_chk.724204863 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_max_throughput_chk.881610167 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all.2305889497 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.555423161 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_alert_test.286818356 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.723794410 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_kmac_err_chk.3965772312 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_max_throughput_chk.801046270 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all.2414247529 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.1270894608 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_alert_test.4171776091 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.4235748451 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_kmac_err_chk.2822724411 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_max_throughput_chk.1399247745 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all.3239250823 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.1805428829 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_alert_test.992048989 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.4055093089 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_kmac_err_chk.537519253 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_max_throughput_chk.742302768 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all.2747609967 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.724617847 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_alert_test.1375616733 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.3475497115 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_kmac_err_chk.3166523146 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_max_throughput_chk.3970609832 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all.3920893975 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.493269581 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_alert_test.2099019592 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1451154468 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_kmac_err_chk.1967059118 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_max_throughput_chk.2301828252 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all.603028614 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.4066686171 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_alert_test.2825342979 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1698852511 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_kmac_err_chk.1836363398 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_max_throughput_chk.1414408486 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all.1964248367 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.1305396561 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_alert_test.3901548692 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2101953687 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_kmac_err_chk.2164303689 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_max_throughput_chk.1260511634 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all.3446320630 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.971064022 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_alert_test.3466298559 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3070893617 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_kmac_err_chk.3777823182 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_max_throughput_chk.2645427779 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all.4243002769 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.2384063720 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_alert_test.3790549719 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_kmac_err_chk.406043168 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_max_throughput_chk.1823398849 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_smoke.409729838 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all.1588435340 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.1826895703 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_alert_test.1834347156 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2819828963 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_max_throughput_chk.2558108556 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_smoke.1214456484 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all.724277675 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_alert_test.2117219524 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.757959459 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_kmac_err_chk.463909665 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_max_throughput_chk.3497291254 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_smoke.1071709605 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all.186070318 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.1371651327 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_alert_test.3368795327 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3889524015 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_max_throughput_chk.2525542419 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_smoke.4084882047 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all.1142970464 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.3970198972 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_alert_test.2764488322 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.609180313 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_kmac_err_chk.822630832 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_max_throughput_chk.3279413972 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_smoke.886399470 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all.3829000886 |
| /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.2804807339 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_alert_test.4215625866 | Oct 15 12:42:42 AM UTC 24 | Oct 15 12:42:53 AM UTC 24 | 1305547150 ps | ||
| T2 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_smoke.145564271 | Oct 15 12:42:42 AM UTC 24 | Oct 15 12:42:54 AM UTC 24 | 772139786 ps | ||
| T3 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_smoke.3233438701 | Oct 15 12:42:43 AM UTC 24 | Oct 15 12:42:56 AM UTC 24 | 223839102 ps | ||
| T4 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_max_throughput_chk.1962073947 | Oct 15 12:42:40 AM UTC 24 | Oct 15 12:42:57 AM UTC 24 | 1975866399 ps | ||
| T5 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_smoke.165102726 | Oct 15 12:42:40 AM UTC 24 | Oct 15 12:42:58 AM UTC 24 | 335878618 ps | ||
| T6 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_alert_test.2188608963 | Oct 15 12:42:43 AM UTC 24 | Oct 15 12:42:58 AM UTC 24 | 532143085 ps | ||
| T7 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_max_throughput_chk.369675447 | Oct 15 12:42:42 AM UTC 24 | Oct 15 12:42:58 AM UTC 24 | 303449697 ps | ||
| T8 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_max_throughput_chk.1619070756 | Oct 15 12:42:44 AM UTC 24 | Oct 15 12:42:58 AM UTC 24 | 623757215 ps | ||
| T9 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_alert_test.732087292 | Oct 15 12:42:48 AM UTC 24 | Oct 15 12:43:01 AM UTC 24 | 534020732 ps | ||
| T10 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_kmac_err_chk.163076108 | Oct 15 12:42:42 AM UTC 24 | Oct 15 12:43:02 AM UTC 24 | 1359204700 ps | ||
| T20 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_smoke.1469197171 | Oct 15 12:42:49 AM UTC 24 | Oct 15 12:43:03 AM UTC 24 | 990824047 ps | ||
| T29 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_alert_test.825210943 | Oct 15 12:42:57 AM UTC 24 | Oct 15 12:43:07 AM UTC 24 | 2390156130 ps | ||
| T21 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_max_throughput_chk.789191131 | Oct 15 12:42:51 AM UTC 24 | Oct 15 12:43:07 AM UTC 24 | 1077205825 ps | ||
| T11 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_kmac_err_chk.2557228168 | Oct 15 12:42:40 AM UTC 24 | Oct 15 12:43:11 AM UTC 24 | 8232459911 ps | ||
| T12 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all.910764996 | Oct 15 12:42:42 AM UTC 24 | Oct 15 12:43:11 AM UTC 24 | 1115796981 ps | ||
| T28 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_kmac_err_chk.78195291 | Oct 15 12:42:45 AM UTC 24 | Oct 15 12:43:12 AM UTC 24 | 1309860369 ps | ||
| T16 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_max_throughput_chk.3332117383 | Oct 15 12:42:59 AM UTC 24 | Oct 15 12:43:14 AM UTC 24 | 305089109 ps | ||
| T30 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_alert_test.163128417 | Oct 15 12:43:02 AM UTC 24 | Oct 15 12:43:15 AM UTC 24 | 376780310 ps | ||
| T17 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all.2974011145 | Oct 15 12:42:40 AM UTC 24 | Oct 15 12:43:16 AM UTC 24 | 2055371150 ps | ||
| T54 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_smoke.681394320 | Oct 15 12:42:57 AM UTC 24 | Oct 15 12:43:18 AM UTC 24 | 808911821 ps | ||
| T18 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_smoke.409729838 | Oct 15 12:43:03 AM UTC 24 | Oct 15 12:43:19 AM UTC 24 | 400026088 ps | ||
| T31 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all.1097239750 | Oct 15 12:42:50 AM UTC 24 | Oct 15 12:43:22 AM UTC 24 | 2028227517 ps | ||
| T50 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_kmac_err_chk.3992417694 | Oct 15 12:42:59 AM UTC 24 | Oct 15 12:43:23 AM UTC 24 | 555075365 ps | ||
| T121 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_max_throughput_chk.1823398849 | Oct 15 12:43:08 AM UTC 24 | Oct 15 12:43:25 AM UTC 24 | 223177153 ps | ||
| T93 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_smoke.1214456484 | Oct 15 12:43:13 AM UTC 24 | Oct 15 12:43:25 AM UTC 24 | 220542671 ps | ||
| T80 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_alert_test.3790549719 | Oct 15 12:43:13 AM UTC 24 | Oct 15 12:43:27 AM UTC 24 | 398233174 ps | ||
| T32 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all.4040198950 | Oct 15 12:42:43 AM UTC 24 | Oct 15 12:43:27 AM UTC 24 | 1162630247 ps | ||
| T94 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all.1588435340 | Oct 15 12:43:04 AM UTC 24 | Oct 15 12:43:27 AM UTC 24 | 552969151 ps | ||
| T33 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_kmac_err_chk.28977750 | Oct 15 12:42:55 AM UTC 24 | Oct 15 12:43:28 AM UTC 24 | 2010378842 ps | ||
| T81 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_alert_test.1834347156 | Oct 15 12:43:18 AM UTC 24 | Oct 15 12:43:30 AM UTC 24 | 533830331 ps | ||
| T144 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_max_throughput_chk.2558108556 | Oct 15 12:43:15 AM UTC 24 | Oct 15 12:43:30 AM UTC 24 | 567477776 ps | ||
| T59 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all.3660632632 | Oct 15 12:42:57 AM UTC 24 | Oct 15 12:43:35 AM UTC 24 | 2113171935 ps | ||
| T145 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_smoke.1071709605 | Oct 15 12:43:20 AM UTC 24 | Oct 15 12:43:36 AM UTC 24 | 1096034296 ps | ||
| T122 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_max_throughput_chk.3497291254 | Oct 15 12:43:23 AM UTC 24 | Oct 15 12:43:38 AM UTC 24 | 2910577343 ps | ||
| T34 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_kmac_err_chk.406043168 | Oct 15 12:43:08 AM UTC 24 | Oct 15 12:43:39 AM UTC 24 | 381193385 ps | ||
| T146 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_smoke.4084882047 | Oct 15 12:43:28 AM UTC 24 | Oct 15 12:43:44 AM UTC 24 | 970022221 ps | ||
| T82 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_alert_test.2117219524 | Oct 15 12:43:28 AM UTC 24 | Oct 15 12:43:44 AM UTC 24 | 3548348553 ps | ||
| T35 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_kmac_err_chk.1972938286 | Oct 15 12:43:17 AM UTC 24 | Oct 15 12:43:45 AM UTC 24 | 370854692 ps | ||
| T123 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all.724277675 | Oct 15 12:43:14 AM UTC 24 | Oct 15 12:43:46 AM UTC 24 | 774563244 ps | ||
| T83 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_alert_test.3368795327 | Oct 15 12:43:35 AM UTC 24 | Oct 15 12:43:47 AM UTC 24 | 205382601 ps | ||
| T124 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_max_throughput_chk.2525542419 | Oct 15 12:43:29 AM UTC 24 | Oct 15 12:43:48 AM UTC 24 | 333154085 ps | ||
| T151 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_smoke.886399470 | Oct 15 12:43:37 AM UTC 24 | Oct 15 12:43:51 AM UTC 24 | 554569122 ps | ||
| T51 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_kmac_err_chk.3367949398 | Oct 15 12:43:31 AM UTC 24 | Oct 15 12:43:55 AM UTC 24 | 1027869051 ps | ||
| T52 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_kmac_err_chk.463909665 | Oct 15 12:43:26 AM UTC 24 | Oct 15 12:43:56 AM UTC 24 | 714127836 ps | ||
| T13 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.369555950 | Oct 15 12:42:59 AM UTC 24 | Oct 15 12:43:57 AM UTC 24 | 1148483603 ps | ||
| T66 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_max_throughput_chk.3279413972 | Oct 15 12:43:40 AM UTC 24 | Oct 15 12:43:59 AM UTC 24 | 1378804075 ps | ||
| T67 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all.186070318 | Oct 15 12:43:22 AM UTC 24 | Oct 15 12:43:59 AM UTC 24 | 1523909191 ps | ||
| T68 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_alert_test.2764488322 | Oct 15 12:43:45 AM UTC 24 | Oct 15 12:43:59 AM UTC 24 | 212258112 ps | ||
| T69 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all.3829000886 | Oct 15 12:43:39 AM UTC 24 | Oct 15 12:44:03 AM UTC 24 | 2936495602 ps | ||
| T70 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_max_throughput_chk.3412161461 | Oct 15 12:43:47 AM UTC 24 | Oct 15 12:44:03 AM UTC 24 | 309388142 ps | ||
| T71 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_alert_test.3741289235 | Oct 15 12:43:52 AM UTC 24 | Oct 15 12:44:05 AM UTC 24 | 376957909 ps | ||
| T14 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.3343779602 | Oct 15 12:43:17 AM UTC 24 | Oct 15 12:44:13 AM UTC 24 | 1370267493 ps | ||
| T72 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all.1142970464 | Oct 15 12:43:28 AM UTC 24 | Oct 15 12:44:14 AM UTC 24 | 1154033934 ps | ||
| T73 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all.170464885 | Oct 15 12:43:46 AM UTC 24 | Oct 15 12:44:14 AM UTC 24 | 397450840 ps | ||
| T152 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_max_throughput_chk.126513425 | Oct 15 12:43:56 AM UTC 24 | Oct 15 12:44:14 AM UTC 24 | 297748483 ps | ||
| T149 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_alert_test.400269165 | Oct 15 12:44:00 AM UTC 24 | Oct 15 12:44:15 AM UTC 24 | 3547766937 ps | ||
| T153 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_max_throughput_chk.2518411571 | Oct 15 12:44:00 AM UTC 24 | Oct 15 12:44:15 AM UTC 24 | 224084010 ps | ||
| T154 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all.3950942932 | Oct 15 12:43:55 AM UTC 24 | Oct 15 12:44:16 AM UTC 24 | 325648315 ps | ||
| T53 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_kmac_err_chk.822630832 | Oct 15 12:43:45 AM UTC 24 | Oct 15 12:44:16 AM UTC 24 | 554154417 ps | ||
| T150 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_kmac_err_chk.3943470090 | Oct 15 12:43:48 AM UTC 24 | Oct 15 12:44:18 AM UTC 24 | 555475909 ps | ||
| T155 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_alert_test.3146818772 | Oct 15 12:44:04 AM UTC 24 | Oct 15 12:44:19 AM UTC 24 | 297412550 ps | ||
| T156 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_max_throughput_chk.2710222000 | Oct 15 12:44:05 AM UTC 24 | Oct 15 12:44:19 AM UTC 24 | 2509238753 ps | ||
| T56 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_kmac_err_chk.4072476007 | Oct 15 12:43:57 AM UTC 24 | Oct 15 12:44:23 AM UTC 24 | 590431144 ps | ||
| T157 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all.3239292193 | Oct 15 12:44:00 AM UTC 24 | Oct 15 12:44:29 AM UTC 24 | 571398956 ps | ||
| T158 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all.1722565681 | Oct 15 12:44:04 AM UTC 24 | Oct 15 12:44:30 AM UTC 24 | 403198405 ps | ||
| T159 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_kmac_err_chk.4029016679 | Oct 15 12:44:01 AM UTC 24 | Oct 15 12:44:30 AM UTC 24 | 534552847 ps | ||
| T55 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_alert_test.4014465152 | Oct 15 12:44:22 AM UTC 24 | Oct 15 12:44:32 AM UTC 24 | 727042351 ps | ||
| T148 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_alert_test.2040159850 | Oct 15 12:44:22 AM UTC 24 | Oct 15 12:44:35 AM UTC 24 | 1689761197 ps | ||
| T15 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.2123690098 | Oct 15 12:42:45 AM UTC 24 | Oct 15 12:44:35 AM UTC 24 | 4278801648 ps | ||
| T160 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_max_throughput_chk.1963853423 | Oct 15 12:44:22 AM UTC 24 | Oct 15 12:44:36 AM UTC 24 | 996866387 ps | ||
| T147 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_alert_test.3565684910 | Oct 15 12:44:22 AM UTC 24 | Oct 15 12:44:36 AM UTC 24 | 212254995 ps | ||
| T161 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_max_throughput_chk.701557503 | Oct 15 12:44:22 AM UTC 24 | Oct 15 12:44:39 AM UTC 24 | 1069036385 ps | ||
| T60 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.2940990039 | Oct 15 12:42:55 AM UTC 24 | Oct 15 12:44:39 AM UTC 24 | 4820992521 ps | ||
| T25 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_sec_cm.1986748468 | Oct 15 12:42:45 AM UTC 24 | Oct 15 12:44:40 AM UTC 24 | 825848236 ps | ||
| T38 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_max_throughput_chk.2565499082 | Oct 15 12:44:25 AM UTC 24 | Oct 15 12:44:42 AM UTC 24 | 312799094 ps | ||
| T39 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all.923848496 | Oct 15 12:44:22 AM UTC 24 | Oct 15 12:44:43 AM UTC 24 | 701078844 ps | ||
| T40 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.2857948248 | Oct 15 12:42:41 AM UTC 24 | Oct 15 12:44:44 AM UTC 24 | 32364025767 ps | ||
| T41 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_kmac_err_chk.2439348145 | Oct 15 12:44:22 AM UTC 24 | Oct 15 12:44:44 AM UTC 24 | 2099714790 ps | ||
| T26 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_sec_cm.4136633364 | Oct 15 12:42:43 AM UTC 24 | Oct 15 12:44:45 AM UTC 24 | 1139365414 ps | ||
| T42 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_kmac_err_chk.2420432615 | Oct 15 12:44:22 AM UTC 24 | Oct 15 12:44:48 AM UTC 24 | 2010606265 ps | ||
| T27 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_sec_cm.3864451366 | Oct 15 12:42:57 AM UTC 24 | Oct 15 12:45:16 AM UTC 24 | 541330510 ps | ||
| T43 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all.3385415792 | Oct 15 12:44:22 AM UTC 24 | Oct 15 12:44:48 AM UTC 24 | 406735008 ps | ||
| T44 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_alert_test.897770476 | Oct 15 12:44:32 AM UTC 24 | Oct 15 12:44:49 AM UTC 24 | 287679544 ps | ||
| T162 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_max_throughput_chk.3622410766 | Oct 15 12:44:35 AM UTC 24 | Oct 15 12:44:49 AM UTC 24 | 679198365 ps | ||
| T163 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_alert_test.3224379737 | Oct 15 12:44:40 AM UTC 24 | Oct 15 12:44:50 AM UTC 24 | 384046041 ps | ||
| T61 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.2804807339 | Oct 15 12:43:45 AM UTC 24 | Oct 15 12:44:54 AM UTC 24 | 4986863607 ps | ||
| T164 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_kmac_err_chk.1340299148 | Oct 15 12:44:20 AM UTC 24 | Oct 15 12:44:55 AM UTC 24 | 543287546 ps | ||
| T165 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_alert_test.2845397103 | Oct 15 12:44:45 AM UTC 24 | Oct 15 12:44:56 AM UTC 24 | 532254256 ps | ||
| T166 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all.3081538188 | Oct 15 12:44:41 AM UTC 24 | Oct 15 12:44:57 AM UTC 24 | 315740183 ps | ||
| T167 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_max_throughput_chk.2632706103 | Oct 15 12:44:41 AM UTC 24 | Oct 15 12:44:59 AM UTC 24 | 297168190 ps | ||
| T168 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all.344658969 | Oct 15 12:44:23 AM UTC 24 | Oct 15 12:45:02 AM UTC 24 | 2263939697 ps | ||
| T169 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_kmac_err_chk.3416620203 | Oct 15 12:44:31 AM UTC 24 | Oct 15 12:45:02 AM UTC 24 | 2499044506 ps | ||
| T170 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_max_throughput_chk.1228733384 | Oct 15 12:44:48 AM UTC 24 | Oct 15 12:45:03 AM UTC 24 | 397328119 ps | ||
| T171 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_alert_test.1931807145 | Oct 15 12:44:50 AM UTC 24 | Oct 15 12:45:05 AM UTC 24 | 212505794 ps | ||
| T172 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_kmac_err_chk.3406129657 | Oct 15 12:44:36 AM UTC 24 | Oct 15 12:45:05 AM UTC 24 | 2393578625 ps | ||
| T173 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_max_throughput_chk.3474020685 | Oct 15 12:44:55 AM UTC 24 | Oct 15 12:45:13 AM UTC 24 | 295001517 ps | ||
| T174 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_kmac_err_chk.2990362518 | Oct 15 12:44:44 AM UTC 24 | Oct 15 12:45:13 AM UTC 24 | 4159793041 ps | ||
| T175 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_alert_test.4031705307 | Oct 15 12:45:00 AM UTC 24 | Oct 15 12:45:14 AM UTC 24 | 205439225 ps | ||
| T176 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all.1216404833 | Oct 15 12:44:32 AM UTC 24 | Oct 15 12:45:15 AM UTC 24 | 5149943907 ps | ||
| T62 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.1371651327 | Oct 15 12:43:26 AM UTC 24 | Oct 15 12:45:16 AM UTC 24 | 3515947868 ps | ||
| T63 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.543189545 | Oct 15 12:44:22 AM UTC 24 | Oct 15 12:45:17 AM UTC 24 | 876329587 ps | ||
| T177 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_kmac_err_chk.1855170113 | Oct 15 12:44:49 AM UTC 24 | Oct 15 12:45:19 AM UTC 24 | 1415099383 ps | ||
| T178 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_max_throughput_chk.1486170438 | Oct 15 12:45:03 AM UTC 24 | Oct 15 12:45:19 AM UTC 24 | 1780497762 ps | ||
| T36 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_sec_cm.1944843679 | Oct 15 12:42:42 AM UTC 24 | Oct 15 12:45:22 AM UTC 24 | 544402408 ps | ||
| T22 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.965910535 | Oct 15 12:42:45 AM UTC 24 | Oct 15 12:45:23 AM UTC 24 | 2033686122 ps | ||
| T179 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_kmac_err_chk.3912418648 | Oct 15 12:44:57 AM UTC 24 | Oct 15 12:45:24 AM UTC 24 | 713713273 ps | ||
| T180 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all.3022975767 | Oct 15 12:44:51 AM UTC 24 | Oct 15 12:45:27 AM UTC 24 | 884305539 ps | ||
| T181 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_alert_test.2718319656 | Oct 15 12:45:13 AM UTC 24 | Oct 15 12:45:30 AM UTC 24 | 535307141 ps | ||
| T182 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_kmac_err_chk.2954568997 | Oct 15 12:45:06 AM UTC 24 | Oct 15 12:45:31 AM UTC 24 | 1359058342 ps | ||
| T183 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_max_throughput_chk.2551920642 | Oct 15 12:45:14 AM UTC 24 | Oct 15 12:45:31 AM UTC 24 | 1065271755 ps | ||
| T184 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_alert_test.203371364 | Oct 15 12:45:18 AM UTC 24 | Oct 15 12:45:31 AM UTC 24 | 552582680 ps | ||
| T185 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all.434606069 | Oct 15 12:45:03 AM UTC 24 | Oct 15 12:45:33 AM UTC 24 | 387544693 ps | ||
| T23 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3889524015 | Oct 15 12:43:30 AM UTC 24 | Oct 15 12:45:34 AM UTC 24 | 5376617105 ps | ||
| T186 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all.783237160 | Oct 15 12:44:46 AM UTC 24 | Oct 15 12:45:35 AM UTC 24 | 12069319320 ps | ||
| T187 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all.2290236682 | Oct 15 12:45:14 AM UTC 24 | Oct 15 12:45:37 AM UTC 24 | 259964173 ps | ||
| T188 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_max_throughput_chk.1008255814 | Oct 15 12:45:20 AM UTC 24 | Oct 15 12:45:39 AM UTC 24 | 713256960 ps | ||
| T64 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.3040224574 | Oct 15 12:44:00 AM UTC 24 | Oct 15 12:45:39 AM UTC 24 | 6823017578 ps | ||
| T65 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.1837167746 | Oct 15 12:44:49 AM UTC 24 | Oct 15 12:45:41 AM UTC 24 | 4815107258 ps | ||
| T189 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_alert_test.1365821501 | Oct 15 12:45:27 AM UTC 24 | Oct 15 12:45:43 AM UTC 24 | 1497766953 ps | ||
| T190 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.2758297421 | Oct 15 12:43:49 AM UTC 24 | Oct 15 12:45:45 AM UTC 24 | 2211175793 ps | ||
| T191 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.1826895703 | Oct 15 12:43:11 AM UTC 24 | Oct 15 12:45:46 AM UTC 24 | 13858495419 ps | ||
| T140 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.1740748267 | Oct 15 12:44:31 AM UTC 24 | Oct 15 12:45:46 AM UTC 24 | 6597488837 ps | ||
| T192 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_max_throughput_chk.4013779368 | Oct 15 12:45:31 AM UTC 24 | Oct 15 12:45:47 AM UTC 24 | 309341022 ps | ||
| T193 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_kmac_err_chk.3257382901 | Oct 15 12:45:24 AM UTC 24 | Oct 15 12:45:48 AM UTC 24 | 1070409526 ps | ||
| T194 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_alert_test.527135247 | Oct 15 12:45:35 AM UTC 24 | Oct 15 12:45:48 AM UTC 24 | 210907754 ps | ||
| T195 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_kmac_err_chk.546962781 | Oct 15 12:45:17 AM UTC 24 | Oct 15 12:45:49 AM UTC 24 | 8295232858 ps | ||
| T196 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_max_throughput_chk.2578490177 | Oct 15 12:45:38 AM UTC 24 | Oct 15 12:45:50 AM UTC 24 | 733925381 ps | ||
| T24 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2819828963 | Oct 15 12:43:16 AM UTC 24 | Oct 15 12:45:52 AM UTC 24 | 2218791467 ps | ||
| T197 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.3970198972 | Oct 15 12:43:31 AM UTC 24 | Oct 15 12:45:54 AM UTC 24 | 2927050959 ps | ||
| T198 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_stress_all.2356731601 | Oct 15 12:45:20 AM UTC 24 | Oct 15 12:45:57 AM UTC 24 | 1117755569 ps | ||
| T199 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_alert_test.3065270905 | Oct 15 12:45:43 AM UTC 24 | Oct 15 12:45:58 AM UTC 24 | 1581174722 ps | ||
| T200 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all.2256143975 | Oct 15 12:45:30 AM UTC 24 | Oct 15 12:46:03 AM UTC 24 | 1434169167 ps | ||
| T201 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_alert_test.3724944522 | Oct 15 12:45:50 AM UTC 24 | Oct 15 12:46:03 AM UTC 24 | 294876473 ps | ||
| T202 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.3853594882 | Oct 15 12:44:22 AM UTC 24 | Oct 15 12:46:03 AM UTC 24 | 2083248345 ps | ||
| T203 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all.546791443 | Oct 15 12:45:37 AM UTC 24 | Oct 15 12:46:04 AM UTC 24 | 427791954 ps | ||
| T204 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_kmac_err_chk.1531922675 | Oct 15 12:45:32 AM UTC 24 | Oct 15 12:46:04 AM UTC 24 | 534929092 ps | ||
| T205 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_max_throughput_chk.1833339929 | Oct 15 12:45:47 AM UTC 24 | Oct 15 12:46:05 AM UTC 24 | 308875963 ps | ||
| T206 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all.3879347393 | Oct 15 12:45:45 AM UTC 24 | Oct 15 12:46:05 AM UTC 24 | 1321714052 ps | ||
| T207 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_kmac_err_chk.770622849 | Oct 15 12:45:40 AM UTC 24 | Oct 15 12:46:05 AM UTC 24 | 2013521711 ps | ||
| T208 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_max_throughput_chk.190089289 | Oct 15 12:45:51 AM UTC 24 | Oct 15 12:46:07 AM UTC 24 | 594374437 ps | ||
| T45 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1195275758 | Oct 15 12:43:08 AM UTC 24 | Oct 15 12:46:10 AM UTC 24 | 36425792232 ps | ||
| T209 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_alert_test.3678216724 | Oct 15 12:45:58 AM UTC 24 | Oct 15 12:46:10 AM UTC 24 | 1068520390 ps | ||
| T210 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.3040138829 | Oct 15 12:42:43 AM UTC 24 | Oct 15 12:46:12 AM UTC 24 | 10573288767 ps | ||
| T211 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_kmac_err_chk.1021617229 | Oct 15 12:45:47 AM UTC 24 | Oct 15 12:46:13 AM UTC 24 | 939549753 ps | ||
| T212 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.1745966610 | Oct 15 12:44:03 AM UTC 24 | Oct 15 12:46:15 AM UTC 24 | 6835917861 ps | ||
| T213 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_kmac_err_chk.81074882 | Oct 15 12:45:55 AM UTC 24 | Oct 15 12:46:15 AM UTC 24 | 699475508 ps | ||
| T214 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_alert_test.520737291 | Oct 15 12:46:06 AM UTC 24 | Oct 15 12:46:16 AM UTC 24 | 207374579 ps | ||
| T215 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_max_throughput_chk.2079090439 | Oct 15 12:46:05 AM UTC 24 | Oct 15 12:46:21 AM UTC 24 | 300593961 ps | ||
| T216 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1466828154 | Oct 15 12:44:22 AM UTC 24 | Oct 15 12:46:22 AM UTC 24 | 5447236952 ps | ||
| T217 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.609180313 | Oct 15 12:43:42 AM UTC 24 | Oct 15 12:46:23 AM UTC 24 | 2505742429 ps | ||
| T218 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_max_throughput_chk.1532848255 | Oct 15 12:46:08 AM UTC 24 | Oct 15 12:46:23 AM UTC 24 | 1026244719 ps | ||
| T219 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/27.rom_ctrl_stress_all.1068960244 | Oct 15 12:45:50 AM UTC 24 | Oct 15 12:46:26 AM UTC 24 | 1594622379 ps | ||
| T220 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_kmac_err_chk.836899344 | Oct 15 12:46:06 AM UTC 24 | Oct 15 12:46:28 AM UTC 24 | 380714570 ps | ||
| T221 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_alert_test.178870695 | Oct 15 12:46:16 AM UTC 24 | Oct 15 12:46:28 AM UTC 24 | 699146163 ps | ||
| T222 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_max_throughput_chk.4044268292 | Oct 15 12:46:16 AM UTC 24 | Oct 15 12:46:30 AM UTC 24 | 301477820 ps | ||
| T223 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all.2403730283 | Oct 15 12:46:04 AM UTC 24 | Oct 15 12:46:32 AM UTC 24 | 1806579450 ps | ||
| T224 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_alert_test.3356239648 | Oct 15 12:46:21 AM UTC 24 | Oct 15 12:46:36 AM UTC 24 | 212778218 ps | ||
| T37 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_sec_cm.850288195 | Oct 15 12:43:00 AM UTC 24 | Oct 15 12:47:25 AM UTC 24 | 1436617024 ps | ||
| T225 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_kmac_err_chk.1936494109 | Oct 15 12:46:18 AM UTC 24 | Oct 15 12:46:37 AM UTC 24 | 1978543602 ps | ||
| T226 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_max_throughput_chk.1468966888 | Oct 15 12:46:23 AM UTC 24 | Oct 15 12:46:40 AM UTC 24 | 1623441351 ps | ||
| T227 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all.4158478217 | Oct 15 12:46:06 AM UTC 24 | Oct 15 12:46:41 AM UTC 24 | 1939285278 ps | ||
| T228 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_kmac_err_chk.2537613768 | Oct 15 12:46:14 AM UTC 24 | Oct 15 12:46:41 AM UTC 24 | 380494963 ps | ||
| T229 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_alert_test.2142606429 | Oct 15 12:46:28 AM UTC 24 | Oct 15 12:46:43 AM UTC 24 | 497429299 ps | ||
| T230 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_stress_all.458111983 | Oct 15 12:46:22 AM UTC 24 | Oct 15 12:46:45 AM UTC 24 | 604669988 ps | ||
| T19 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.3145023560 | Oct 15 12:44:37 AM UTC 24 | Oct 15 12:46:48 AM UTC 24 | 6291757630 ps | ||
| T231 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.712067901 | Oct 15 12:45:48 AM UTC 24 | Oct 15 12:46:50 AM UTC 24 | 2706402191 ps | ||
| T232 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.2107563028 | Oct 15 12:46:15 AM UTC 24 | Oct 15 12:46:50 AM UTC 24 | 777682361 ps | ||
| T233 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_max_throughput_chk.3715784860 | Oct 15 12:46:31 AM UTC 24 | Oct 15 12:46:50 AM UTC 24 | 220748704 ps | ||
| T234 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_alert_test.245325767 | Oct 15 12:46:42 AM UTC 24 | Oct 15 12:46:53 AM UTC 24 | 651079726 ps | ||
| T235 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.3814629717 | Oct 15 12:45:34 AM UTC 24 | Oct 15 12:46:57 AM UTC 24 | 3866548294 ps | ||
| T236 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all.2723462599 | Oct 15 12:46:16 AM UTC 24 | Oct 15 12:46:58 AM UTC 24 | 3288114999 ps | ||
| T237 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/31.rom_ctrl_kmac_err_chk.502130276 | Oct 15 12:46:24 AM UTC 24 | Oct 15 12:46:58 AM UTC 24 | 3332986080 ps | ||
| T46 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2713535212 | Oct 15 12:42:40 AM UTC 24 | Oct 15 12:46:59 AM UTC 24 | 8530862566 ps | ||
| T238 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_max_throughput_chk.2647283267 | Oct 15 12:46:43 AM UTC 24 | Oct 15 12:47:00 AM UTC 24 | 733363058 ps | ||
| T239 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_max_throughput_chk.1876520460 | Oct 15 12:46:51 AM UTC 24 | Oct 15 12:47:05 AM UTC 24 | 404577940 ps | ||
| T240 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_alert_test.3125542821 | Oct 15 12:46:50 AM UTC 24 | Oct 15 12:47:06 AM UTC 24 | 542943728 ps | ||
| T241 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_kmac_err_chk.671949092 | Oct 15 12:46:36 AM UTC 24 | Oct 15 12:47:07 AM UTC 24 | 370853956 ps | ||
| T242 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all.2469053974 | Oct 15 12:46:29 AM UTC 24 | Oct 15 12:47:09 AM UTC 24 | 3133160904 ps | ||
| T243 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.1430516340 | Oct 15 12:44:58 AM UTC 24 | Oct 15 12:47:09 AM UTC 24 | 23221975911 ps | ||
| T47 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2466040350 | Oct 15 12:44:43 AM UTC 24 | Oct 15 12:47:11 AM UTC 24 | 15882549574 ps | ||
| T244 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_stress_all.2759034535 | Oct 15 12:46:43 AM UTC 24 | Oct 15 12:47:13 AM UTC 24 | 412407616 ps | ||
| T245 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.3772154522 | Oct 15 12:46:18 AM UTC 24 | Oct 15 12:47:14 AM UTC 24 | 3416272325 ps | ||
| T246 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/33.rom_ctrl_kmac_err_chk.3141901450 | Oct 15 12:46:46 AM UTC 24 | Oct 15 12:47:14 AM UTC 24 | 387789007 ps | ||
| T247 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_stress_all.2334444813 | Oct 15 12:46:51 AM UTC 24 | Oct 15 12:47:14 AM UTC 24 | 815401519 ps | ||
| T248 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_alert_test.1132755512 | Oct 15 12:47:00 AM UTC 24 | Oct 15 12:47:15 AM UTC 24 | 1027260398 ps | ||
| T249 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_max_throughput_chk.2399867824 | Oct 15 12:47:01 AM UTC 24 | Oct 15 12:47:17 AM UTC 24 | 4301525624 ps | ||
| T250 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_alert_test.2073724228 | Oct 15 12:47:10 AM UTC 24 | Oct 15 12:47:21 AM UTC 24 | 3103390575 ps | ||
| T251 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3383411028 | Oct 15 12:44:56 AM UTC 24 | Oct 15 12:47:25 AM UTC 24 | 1434029495 ps | ||
| T252 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.4183949343 | Oct 15 12:45:06 AM UTC 24 | Oct 15 12:47:26 AM UTC 24 | 12596125217 ps | ||
| T253 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_alert_test.3258332456 | Oct 15 12:47:17 AM UTC 24 | Oct 15 12:47:29 AM UTC 24 | 908443199 ps | ||
| T254 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/34.rom_ctrl_kmac_err_chk.4244481376 | Oct 15 12:46:58 AM UTC 24 | Oct 15 12:47:29 AM UTC 24 | 4146800674 ps | ||
| T255 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_max_throughput_chk.1467610862 | Oct 15 12:47:17 AM UTC 24 | Oct 15 12:47:32 AM UTC 24 | 395249866 ps | ||
| T256 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_max_throughput_chk.2068503627 | Oct 15 12:47:16 AM UTC 24 | Oct 15 12:47:32 AM UTC 24 | 1098734792 ps | ||
| T48 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2629021180 | Oct 15 12:44:20 AM UTC 24 | Oct 15 12:47:33 AM UTC 24 | 11202702217 ps | ||
| T257 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_alert_test.2318427498 | Oct 15 12:47:26 AM UTC 24 | Oct 15 12:47:36 AM UTC 24 | 726810776 ps | ||
| T258 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.2555473422 | Oct 15 12:46:06 AM UTC 24 | Oct 15 12:47:37 AM UTC 24 | 1636210393 ps | ||
| T57 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_kmac_err_chk.2834904938 | Oct 15 12:47:07 AM UTC 24 | Oct 15 12:47:38 AM UTC 24 | 544453561 ps | ||
| T259 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_stress_all.1386612117 | Oct 15 12:47:10 AM UTC 24 | Oct 15 12:47:41 AM UTC 24 | 822346103 ps | ||
| T49 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1189306238 | Oct 15 12:43:57 AM UTC 24 | Oct 15 12:47:42 AM UTC 24 | 64650048266 ps | ||
| T139 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2346937963 | Oct 15 12:42:54 AM UTC 24 | Oct 15 12:47:43 AM UTC 24 | 4080941492 ps | ||
| T260 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_max_throughput_chk.2742875847 | Oct 15 12:47:30 AM UTC 24 | Oct 15 12:47:43 AM UTC 24 | 1810871312 ps | ||
| T261 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2997680054 | Oct 15 12:44:36 AM UTC 24 | Oct 15 12:47:44 AM UTC 24 | 19142904164 ps | ||
| T262 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.2751785339 | Oct 15 12:44:22 AM UTC 24 | Oct 15 12:47:44 AM UTC 24 | 14771166814 ps | ||
| T263 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/36.rom_ctrl_kmac_err_chk.1624840556 | Oct 15 12:47:17 AM UTC 24 | Oct 15 12:47:45 AM UTC 24 | 560896003 ps | ||
| T264 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_alert_test.1993578830 | Oct 15 12:47:33 AM UTC 24 | Oct 15 12:47:47 AM UTC 24 | 4966753923 ps | ||
| T265 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all.2271724795 | Oct 15 12:47:17 AM UTC 24 | Oct 15 12:47:47 AM UTC 24 | 1104870639 ps | ||
| T266 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_kmac_err_chk.2331441890 | Oct 15 12:47:22 AM UTC 24 | Oct 15 12:47:48 AM UTC 24 | 3320427870 ps | ||
| T267 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1302746413 | Oct 15 12:42:42 AM UTC 24 | Oct 15 12:47:49 AM UTC 24 | 4472376942 ps | ||
| T268 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.4101195465 | Oct 15 12:44:45 AM UTC 24 | Oct 15 12:47:50 AM UTC 24 | 4143650180 ps | ||
| T269 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all.1755977012 | Oct 15 12:47:00 AM UTC 24 | Oct 15 12:47:51 AM UTC 24 | 580037661 ps | ||
| T270 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.2299235883 | Oct 15 12:44:01 AM UTC 24 | Oct 15 12:47:52 AM UTC 24 | 2449032527 ps | ||
| T271 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_max_throughput_chk.3143778999 | Oct 15 12:47:38 AM UTC 24 | Oct 15 12:47:52 AM UTC 24 | 399478190 ps | ||
| T272 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1769195666 | Oct 15 12:45:04 AM UTC 24 | Oct 15 12:47:55 AM UTC 24 | 3104229048 ps | ||
| T273 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_kmac_err_chk.2145492466 | Oct 15 12:47:32 AM UTC 24 | Oct 15 12:47:55 AM UTC 24 | 1029414383 ps | ||
| T274 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_alert_test.3737500831 | Oct 15 12:47:44 AM UTC 24 | Oct 15 12:47:56 AM UTC 24 | 4984148483 ps | ||
| T275 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_alert_test.927473859 | Oct 15 12:47:48 AM UTC 24 | Oct 15 12:47:59 AM UTC 24 | 630021468 ps | ||
| T276 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.2992058966 | Oct 15 12:45:17 AM UTC 24 | Oct 15 12:48:01 AM UTC 24 | 3648032680 ps | ||
| T277 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_max_throughput_chk.1587356886 | Oct 15 12:47:45 AM UTC 24 | Oct 15 12:48:01 AM UTC 24 | 379099440 ps | ||
| T278 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.2478081761 | Oct 15 12:46:39 AM UTC 24 | Oct 15 12:48:03 AM UTC 24 | 1598725753 ps | ||
| T279 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_max_throughput_chk.881610167 | Oct 15 12:47:49 AM UTC 24 | Oct 15 12:48:06 AM UTC 24 | 798945950 ps | ||
| T280 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_alert_test.4101948431 | Oct 15 12:47:53 AM UTC 24 | Oct 15 12:48:07 AM UTC 24 | 383667327 ps | ||
| T281 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_kmac_err_chk.158268290 | Oct 15 12:47:42 AM UTC 24 | Oct 15 12:48:07 AM UTC 24 | 1071887361 ps | ||
| T282 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all.5017466 | Oct 15 12:47:44 AM UTC 24 | Oct 15 12:48:07 AM UTC 24 | 240173113 ps | ||
| T283 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/38.rom_ctrl_stress_all.284223294 | Oct 15 12:47:27 AM UTC 24 | Oct 15 12:48:07 AM UTC 24 | 2183721436 ps | ||
| T284 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/39.rom_ctrl_stress_all.779015870 | Oct 15 12:47:37 AM UTC 24 | Oct 15 12:48:10 AM UTC 24 | 1620530695 ps | ||
| T285 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.263018103 | Oct 15 12:45:40 AM UTC 24 | Oct 15 12:48:10 AM UTC 24 | 9175916738 ps | ||
| T286 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_max_throughput_chk.801046270 | Oct 15 12:47:56 AM UTC 24 | Oct 15 12:48:12 AM UTC 24 | 587693193 ps | ||
| T58 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_kmac_err_chk.2279352372 | Oct 15 12:47:46 AM UTC 24 | Oct 15 12:48:15 AM UTC 24 | 687210416 ps | ||
| T287 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.4157513351 | Oct 15 12:47:08 AM UTC 24 | Oct 15 12:48:15 AM UTC 24 | 3177121917 ps | ||
| T288 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_kmac_err_chk.724204863 | Oct 15 12:47:52 AM UTC 24 | Oct 15 12:48:17 AM UTC 24 | 458613283 ps | ||
| T289 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_alert_test.286818356 | Oct 15 12:48:02 AM UTC 24 | Oct 15 12:48:17 AM UTC 24 | 4982594775 ps | ||
| T290 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_stress_all.2414247529 | Oct 15 12:47:56 AM UTC 24 | Oct 15 12:48:18 AM UTC 24 | 1620647394 ps | ||
| T291 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.1889408247 | Oct 15 12:47:47 AM UTC 24 | Oct 15 12:48:20 AM UTC 24 | 1573152733 ps | ||
| T292 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.2351717854 | Oct 15 12:45:23 AM UTC 24 | Oct 15 12:48:20 AM UTC 24 | 46182564479 ps | ||
| T293 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_max_throughput_chk.1399247745 | Oct 15 12:48:08 AM UTC 24 | Oct 15 12:48:21 AM UTC 24 | 977195985 ps | ||
| T294 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.1972376495 | Oct 15 12:42:59 AM UTC 24 | Oct 15 12:48:22 AM UTC 24 | 6080563920 ps | ||
| T295 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_alert_test.4171776091 | Oct 15 12:48:09 AM UTC 24 | Oct 15 12:48:25 AM UTC 24 | 1045068078 ps | ||
| T296 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/41.rom_ctrl_stress_all.2305889497 | Oct 15 12:47:49 AM UTC 24 | Oct 15 12:48:25 AM UTC 24 | 3524731566 ps | ||
| T297 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_stress_all.3239250823 | Oct 15 12:48:03 AM UTC 24 | Oct 15 12:48:26 AM UTC 24 | 1466954820 ps | ||
| T298 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_max_throughput_chk.742302768 | Oct 15 12:48:11 AM UTC 24 | Oct 15 12:48:27 AM UTC 24 | 1055803161 ps | ||
| T299 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/42.rom_ctrl_kmac_err_chk.3965772312 | Oct 15 12:48:00 AM UTC 24 | Oct 15 12:48:28 AM UTC 24 | 5564929232 ps | ||
| T300 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/44.rom_ctrl_stress_all.2747609967 | Oct 15 12:48:11 AM UTC 24 | Oct 15 12:48:29 AM UTC 24 | 774457792 ps | ||
| T301 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.3483434735 | Oct 15 12:47:26 AM UTC 24 | Oct 15 12:48:31 AM UTC 24 | 1096482848 ps | ||
| T302 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.3701529577 | Oct 15 12:45:42 AM UTC 24 | Oct 15 12:48:35 AM UTC 24 | 15328945863 ps | ||
| T303 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/43.rom_ctrl_kmac_err_chk.2822724411 | Oct 15 12:48:08 AM UTC 24 | Oct 15 12:48:35 AM UTC 24 | 3832258877 ps | ||
| T304 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.669656629 | Oct 15 12:43:48 AM UTC 24 | Oct 15 12:48:35 AM UTC 24 | 6295773540 ps | ||
| T305 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_max_throughput_chk.3970609832 | Oct 15 12:48:27 AM UTC 24 | Oct 15 12:48:43 AM UTC 24 | 313035199 ps | ||
| T306 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_alert_test.2099019592 | Oct 15 12:48:30 AM UTC 24 | Oct 15 12:48:44 AM UTC 24 | 614478938 ps | ||
| T307 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/45.rom_ctrl_alert_test.1375616733 | Oct 15 12:48:29 AM UTC 24 | Oct 15 12:48:44 AM UTC 24 | 524099824 ps | ||
| T308 | /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_64kB-sim-vcs/coverage/default/46.rom_ctrl_max_throughput_chk.2301828252 | Oct 15 12:48:29 AM UTC 24 | Oct 15 12:48:44 AM UTC 24 | 766630101 ps |
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