RSTMGR Simulation Results

Monday May 15 2023 07:07:46 UTC

GitHub Revision: 3d5660d90

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 705130430

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rstmgr_smoke	1.480s	253.375us	50	50	100.00
V1	csr_hw_reset	rstmgr_csr_hw_reset	0.930s	149.695us	5	5	100.00
V1	csr_rw	rstmgr_csr_rw	0.980s	93.783us	20	20	100.00
V1	csr_bit_bash	rstmgr_csr_bit_bash	7.300s	1.543ms	5	5	100.00
V1	csr_aliasing	rstmgr_csr_aliasing	2.170s	362.498us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rstmgr_csr_mem_rw_with_rand_reset	1.820s	192.400us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rstmgr_csr_rw	0.980s	93.783us	20	20	100.00
		rstmgr_csr_aliasing	2.170s	362.498us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	reset_stretcher	rstmgr_por_stretcher	0.910s	209.992us	50	50	100.00
V2	sw_rst	rstmgr_sw_rst	2.420s	442.498us	50	50	100.00
V2	sw_rst_reset_race	rstmgr_sw_rst_reset_race	1.440s	223.957us	50	50	100.00
V2	reset_info	rstmgr_reset	7.170s	1.862ms	50	50	100.00
V2	cpu_info	rstmgr_reset	7.170s	1.862ms	50	50	100.00
V2	alert_info	rstmgr_reset	7.170s	1.862ms	50	50	100.00
V2	reset_info_capture	rstmgr_reset	7.170s	1.862ms	50	50	100.00
V2	stress_all	rstmgr_stress_all	52.600s	17.755ms	50	50	100.00
V2	alert_test	rstmgr_alert_test	0.830s	90.701us	50	50	100.00
V2	tl_d_oob_addr_access	rstmgr_tl_errors	3.030s	447.991us	20	20	100.00
V2	tl_d_illegal_access	rstmgr_tl_errors	3.030s	447.991us	20	20	100.00
V2	tl_d_outstanding_access	rstmgr_csr_hw_reset	0.930s	149.695us	5	5	100.00
		rstmgr_csr_rw	0.980s	93.783us	20	20	100.00
		rstmgr_csr_aliasing	2.170s	362.498us	5	5	100.00
		rstmgr_same_csr_outstanding	1.540s	277.084us	20	20	100.00
V2	tl_d_partial_access	rstmgr_csr_hw_reset	0.930s	149.695us	5	5	100.00
		rstmgr_csr_rw	0.980s	93.783us	20	20	100.00
		rstmgr_csr_aliasing	2.170s	362.498us	5	5	100.00
		rstmgr_same_csr_outstanding	1.540s	277.084us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	rstmgr_sec_cm	20.420s	16.747ms	5	5	100.00
		rstmgr_tl_intg_err	3.060s	919.412us	20	20	100.00
V2S	prim_count_check	rstmgr_sec_cm	20.420s	16.747ms	5	5	100.00
V2S	prim_fsm_check	rstmgr_sec_cm	20.420s	16.747ms	5	5	100.00
V2S	sec_cm_bus_integrity	rstmgr_tl_intg_err	3.060s	919.412us	20	20	100.00
V2S	sec_cm_scan_intersig_mubi	rstmgr_sec_cm_scan_intersig_mubi	1.130s	180.817us	50	50	100.00
V2S	sec_cm_leaf_rst_bkgn_chk	rstmgr_leaf_rst_cnsty	8.340s	2.366ms	50	50	100.00
V2S	sec_cm_leaf_rst_shadow	rstmgr_leaf_rst_shadow_attack	1.160s	244.527us	50	50	100.00
V2S	sec_cm_leaf_fsm_sparse	rstmgr_sec_cm	20.420s	16.747ms	5	5	100.00
V2S	sec_cm_sw_rst_config_regwen	rstmgr_csr_rw	0.980s	93.783us	20	20	100.00
V2S	sec_cm_dump_ctrl_config_regwen	rstmgr_csr_rw	0.980s	93.783us	20	20	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	rstmgr_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			620	620	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	5	5	5	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.53	99.41	99.31	99.88	--	99.83	100.00	98.77

Past Results

• Latest
• 2023.05.14_18.15.21
• 2023.05.13_18.59.30
• 2023.05.12_18.50.12
• 2023.05.12_11.29.56
• 2023.05.11_18.05.47
• 2023.05.11_10.48.37
• 2023.05.10_17.40.27