RSTMGR Simulation Results

Wednesday January 24 2024 20:02:24 UTC

GitHub Revision: `17d5a97c3b`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 111545506019531132515166311410934274348263845011639206515682989027305484635840

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rstmgr_smoke	1.620s	249.246us	50	50	100.00
V1	csr_hw_reset	rstmgr_csr_hw_reset	0.960s	141.284us	5	5	100.00
V1	csr_rw	rstmgr_csr_rw	0.900s	76.608us	20	20	100.00
V1	csr_bit_bash	rstmgr_csr_bit_bash	6.030s	483.877us	5	5	100.00
V1	csr_aliasing	rstmgr_csr_aliasing	1.660s	231.158us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rstmgr_csr_mem_rw_with_rand_reset	1.990s	192.833us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rstmgr_csr_rw	0.900s	76.608us	20	20	100.00
		rstmgr_csr_aliasing	1.660s	231.158us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	reset_stretcher	rstmgr_por_stretcher	0.980s	259.071us	50	50	100.00
V2	sw_rst	rstmgr_sw_rst	2.900s	510.741us	50	50	100.00
V2	sw_rst_reset_race	rstmgr_sw_rst_reset_race	1.550s	290.289us	50	50	100.00
V2	reset_info	rstmgr_reset	7.670s	1.875ms	50	50	100.00
V2	cpu_info	rstmgr_reset	7.670s	1.875ms	50	50	100.00
V2	alert_info	rstmgr_reset	7.670s	1.875ms	50	50	100.00
V2	reset_info_capture	rstmgr_reset	7.670s	1.875ms	50	50	100.00
V2	stress_all	rstmgr_stress_all	56.500s	14.102ms	50	50	100.00
V2	alert_test	rstmgr_alert_test	0.870s	83.536us	49	50	98.00
V2	tl_d_oob_addr_access	rstmgr_tl_errors	3.430s	480.743us	20	20	100.00
V2	tl_d_illegal_access	rstmgr_tl_errors	3.430s	480.743us	20	20	100.00
V2	tl_d_outstanding_access	rstmgr_csr_hw_reset	0.960s	141.284us	5	5	100.00
		rstmgr_csr_rw	0.900s	76.608us	20	20	100.00
		rstmgr_csr_aliasing	1.660s	231.158us	5	5	100.00
		rstmgr_same_csr_outstanding	1.610s	286.038us	20	20	100.00
V2	tl_d_partial_access	rstmgr_csr_hw_reset	0.960s	141.284us	5	5	100.00
		rstmgr_csr_rw	0.900s	76.608us	20	20	100.00
		rstmgr_csr_aliasing	1.660s	231.158us	5	5	100.00
		rstmgr_same_csr_outstanding	1.610s	286.038us	20	20	100.00
V2		TOTAL			339	340	99.71
V2S	tl_intg_err	rstmgr_sec_cm	28.290s	16.506ms	5	5	100.00
		rstmgr_tl_intg_err	3.580s	1.260ms	20	20	100.00
V2S	prim_count_check	rstmgr_sec_cm	28.290s	16.506ms	5	5	100.00
V2S	prim_fsm_check	rstmgr_sec_cm	28.290s	16.506ms	5	5	100.00
V2S	sec_cm_bus_integrity	rstmgr_tl_intg_err	3.580s	1.260ms	20	20	100.00
V2S	sec_cm_scan_intersig_mubi	rstmgr_sec_cm_scan_intersig_mubi	1.290s	178.070us	49	50	98.00
V2S	sec_cm_leaf_rst_bkgn_chk	rstmgr_leaf_rst_cnsty	8.500s	2.161ms	50	50	100.00
V2S	sec_cm_leaf_rst_shadow	rstmgr_leaf_rst_shadow_attack	1.220s	245.076us	50	50	100.00
V2S	sec_cm_leaf_fsm_sparse	rstmgr_sec_cm	28.290s	16.506ms	5	5	100.00
V2S	sec_cm_sw_rst_config_regwen	rstmgr_csr_rw	0.900s	76.608us	20	20	100.00
V2S	sec_cm_dump_ctrl_config_regwen	rstmgr_csr_rw	0.900s	76.608us	20	20	100.00
V2S		TOTAL			174	175	99.43
V3	stress_all_with_rand_reset	rstmgr_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			618	620	99.68

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	7	87.50
V2S	5	5	4	80.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.44	99.40	99.31	99.88	--	99.83	99.46	98.77

Failure Buckets

Job rstmgr-sim-vcs_run_default killed due to: Exit reason: Error: * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *] has 1 failures:
- Test rstmgr_sec_cm_scan_intersig_mubi has 1 failures.
  - 20.rstmgr_sec_cm_scan_intersig_mubi.63350142326279877758985153737020493023751301180882081988394189838559993918665
    Log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/20.rstmgr_sec_cm_scan_intersig_mubi/latest/run.log
```
  Job ID: smart:8757f537-0e26-449a-9f18-9c8c2b6e9775
```
Job rstmgr-sim-vcs_run_default killed due to: Exit reason: Error: * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *] has 1 failures:
- Test rstmgr_alert_test has 1 failures.
  - 48.rstmgr_alert_test.43437326045655740359231519027480001155142954028122635794343907423280443763980
    Log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/48.rstmgr_alert_test/latest/run.log
```
  Job ID: smart:1ee3ac6e-bd49-4d0a-988b-84c811115896
```

RSTMGR Simulation Results

Wednesday January 24 2024 20:02:24 UTC

GitHub Revision: 17d5a97c3b

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 111545506019531132515166311410934274348263845011639206515682989027305484635840

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `17d5a97c3b`