RSTMGR Simulation Results

Wednesday November 22 2023 20:02:38 UTC

GitHub Revision: 4002b28ec4

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56541452733628775295814943325285397402671097056517970046183331126493552547969

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rstmgr_smoke	1.590s	223.941us	50	50	100.00
V1	csr_hw_reset	rstmgr_csr_hw_reset	0.850s	108.023us	5	5	100.00
V1	csr_rw	rstmgr_csr_rw	0.780s	61.856us	20	20	100.00
V1	csr_bit_bash	rstmgr_csr_bit_bash	5.060s	1.018ms	5	5	100.00
V1	csr_aliasing	rstmgr_csr_aliasing	1.650s	222.441us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rstmgr_csr_mem_rw_with_rand_reset	1.020s	108.315us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rstmgr_csr_rw	0.780s	61.856us	20	20	100.00
		rstmgr_csr_aliasing	1.650s	222.441us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	reset_stretcher	rstmgr_por_stretcher	1.000s	230.358us	50	50	100.00
V2	sw_rst	rstmgr_sw_rst	2.880s	473.110us	50	50	100.00
V2	sw_rst_reset_race	rstmgr_sw_rst_reset_race	1.600s	241.233us	50	50	100.00
V2	reset_info	rstmgr_reset	7.290s	1.730ms	50	50	100.00
V2	cpu_info	rstmgr_reset	7.290s	1.730ms	50	50	100.00
V2	alert_info	rstmgr_reset	7.290s	1.730ms	50	50	100.00
V2	reset_info_capture	rstmgr_reset	7.290s	1.730ms	50	50	100.00
V2	stress_all	rstmgr_stress_all	41.500s	11.131ms	50	50	100.00
V2	alert_test	rstmgr_alert_test	0.920s	78.982us	50	50	100.00
V2	tl_d_oob_addr_access	rstmgr_tl_errors	2.410s	333.192us	20	20	100.00
V2	tl_d_illegal_access	rstmgr_tl_errors	2.410s	333.192us	20	20	100.00
V2	tl_d_outstanding_access	rstmgr_csr_hw_reset	0.850s	108.023us	5	5	100.00
		rstmgr_csr_rw	0.780s	61.856us	20	20	100.00
		rstmgr_csr_aliasing	1.650s	222.441us	5	5	100.00
		rstmgr_same_csr_outstanding	1.480s	148.107us	20	20	100.00
V2	tl_d_partial_access	rstmgr_csr_hw_reset	0.850s	108.023us	5	5	100.00
		rstmgr_csr_rw	0.780s	61.856us	20	20	100.00
		rstmgr_csr_aliasing	1.650s	222.441us	5	5	100.00
		rstmgr_same_csr_outstanding	1.480s	148.107us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	rstmgr_sec_cm	14.420s	8.295ms	5	5	100.00
		rstmgr_tl_intg_err	2.030s	486.526us	20	20	100.00
V2S	prim_count_check	rstmgr_sec_cm	14.420s	8.295ms	5	5	100.00
V2S	prim_fsm_check	rstmgr_sec_cm	14.420s	8.295ms	5	5	100.00
V2S	sec_cm_bus_integrity	rstmgr_tl_intg_err	2.030s	486.526us	20	20	100.00
V2S	sec_cm_scan_intersig_mubi	rstmgr_sec_cm_scan_intersig_mubi	1.270s	170.066us	50	50	100.00
V2S	sec_cm_leaf_rst_bkgn_chk	rstmgr_leaf_rst_cnsty	8.560s	2.163ms	50	50	100.00
V2S	sec_cm_leaf_rst_shadow	rstmgr_leaf_rst_shadow_attack	1.170s	243.816us	50	50	100.00
V2S	sec_cm_leaf_fsm_sparse	rstmgr_sec_cm	14.420s	8.295ms	5	5	100.00
V2S	sec_cm_sw_rst_config_regwen	rstmgr_csr_rw	0.780s	61.856us	20	20	100.00
V2S	sec_cm_dump_ctrl_config_regwen	rstmgr_csr_rw	0.780s	61.856us	20	20	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	rstmgr_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			620	620	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	5	5	5	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.57	99.40	98.27	99.05	--	99.83	99.33	95.57

Past Results

• Latest
• rstmgr_cnsty_chk
• lint
• 2023.11.02_03.46.44
• 2023.10.30_18.26.45
• 2023.10.26_03.09.22
• 2023.10.23_18.26.46
• 2023.10.19_02.26.15