Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9175

1

T1

8

T2

179

T3

236

auto[1]

12063

1

T1

1

T2

182

T3

209

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6477	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	7156	1			T1	1		T2	136		T3	144
reset_info_cp[2]	3330	1			T2	62		T3	63		T6	4
reset_info_cp[4]	4308	1			T2	75		T3	107		T6	16
reset_info_cp[8]	119	1			T2	3		T3	2		T6	1
reset_info_cp[16]	124	1			T2	1		T3	4		T12	2
reset_info_cp[32]	113	1			T3	4		T4	1		T6	1
reset_info_cp[64]	113	1			T1	1		T3	3		T6	1
reset_info_cp[128]	118	1			T1	1		T3	4		T13	2

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3426	1			T2	70		T3	76		T6	13
reset_info_cp[1]	auto[1]	3110	1			T2	65		T3	67		T6	10
reset_info_cp[2]	auto[0]	1082	1			T2	31		T3	31		T6	1
reset_info_cp[2]	auto[1]	2248	1			T2	31		T3	32		T6	3
reset_info_cp[4]	auto[0]	1595	1			T2	26		T3	55		T6	9
reset_info_cp[4]	auto[1]	2713	1			T2	49		T3	52		T6	7
reset_info_cp[8]	auto[0]	57	1			T2	2		T3	1		T30	1
reset_info_cp[8]	auto[1]	62	1			T2	1		T3	1		T6	1
reset_info_cp[16]	auto[0]	49	1			T3	1		T30	1		T132	1
reset_info_cp[16]	auto[1]	75	1			T2	1		T3	3		T12	2
reset_info_cp[32]	auto[0]	51	1			T3	3		T4	1		T6	1
reset_info_cp[32]	auto[1]	62	1			T3	1		T12	1		T46	1
reset_info_cp[64]	auto[0]	39	1			T1	1		T3	1		T6	1
reset_info_cp[64]	auto[1]	74	1			T3	2		T42	1		T47	1
reset_info_cp[128]	auto[0]	55	1			T1	1		T133	1		T128	1
reset_info_cp[128]	auto[1]	63	1			T3	4		T13	2		T32	1