Assertions
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Assertions by Category
ASSERTPROPERTIESSEQUENCES
Total733010
Category 0733010


Assertions by Severity
ASSERTPROPERTIESSEQUENCES
Total733010
Severity 0733010


Summary for Assertions
NUMBERPERCENT
Total Number733100.00
Uncovered40.55
Success72999.45
Failure00.00
Incomplete00.00
Without Attempts00.00


Summary for Cover Sequences
NUMBERPERCENT
Total Number10100.00
Uncovered00.00
All Matches10100.00
First Matches10100.00


Detail Report for Assertions

Assertions Uncovered:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorAonEnTracksRstPorAonActive_A 001697868000
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorEnTracksRstPorInactive_A 0055947315000
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoDiv4EnTracksRstPorIoDiv4Active_A 0013426987000
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoEnTracksRstPorIoInactive_A 0053707812000

Assertions Success:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
tb.dut.AlertsKnownO_A 0011790944699099500
tb.dut.FpvSecCmRegWeOnehotCheck_A 00117909446000
tb.dut.ParameterMatch_A 0050550500
tb.dut.PwrKnownO_A 0011790944699099500
tb.dut.ResetsKnownO_A 0011790944699099500
tb.dut.RstEnKnownO_A 0011790944699099500
tb.dut.TlAReadyKnownO_A 0011790944699099500
tb.dut.TlDValidKnownO_A 0011790944699099500
tb.dut.gen_d0_i2c0_assert.FpvSecCmD0I2c0FsmCheck_A 00117909446000
tb.dut.gen_d0_i2c1_assert.FpvSecCmD0I2c1FsmCheck_A 00117909446000
tb.dut.gen_d0_i2c2_assert.FpvSecCmD0I2c2FsmCheck_A 00117909446000
tb.dut.gen_d0_lc_assert.FpvSecCmD0LcFsmCheck_A 00117909446000
tb.dut.gen_d0_lc_io_assert.FpvSecCmD0LcIoFsmCheck_A 00117909446000
tb.dut.gen_d0_lc_io_div2_assert.FpvSecCmD0LcIoDiv2FsmCheck_A 00117909446000
tb.dut.gen_d0_lc_shadowed_assert.FpvSecCmD0LcShadowedFsmCheck_A 00117909446000
tb.dut.gen_d0_lc_usb_assert.FpvSecCmD0LcUsbFsmCheck_A 00117909446000
tb.dut.gen_d0_spi_device_assert.FpvSecCmD0SpiDeviceFsmCheck_A 00117909446000
tb.dut.gen_d0_spi_host0_assert.FpvSecCmD0SpiHost0FsmCheck_A 00117909446000
tb.dut.gen_d0_spi_host1_assert.FpvSecCmD0SpiHost1FsmCheck_A 00117909446000
tb.dut.gen_d0_sys_assert.FpvSecCmD0SysFsmCheck_A 00117909446000
tb.dut.gen_d0_usb_aon_assert.FpvSecCmD0UsbAonFsmCheck_A 00117909446000
tb.dut.gen_d0_usb_assert.FpvSecCmD0UsbFsmCheck_A 00117909446000
tb.dut.gen_daon_lc_aon_assert.FpvSecCmDAonLcAonFsmCheck_A 00117909446000
tb.dut.gen_daon_lc_assert.FpvSecCmDAonLcFsmCheck_A 00117909446000
tb.dut.gen_daon_lc_io_assert.FpvSecCmDAonLcIoFsmCheck_A 00117909446000
tb.dut.gen_daon_lc_io_div2_assert.FpvSecCmDAonLcIoDiv2FsmCheck_A 00117909446000
tb.dut.gen_daon_lc_shadowed_assert.FpvSecCmDAonLcShadowedFsmCheck_A 00117909446000
tb.dut.gen_daon_lc_usb_assert.FpvSecCmDAonLcUsbFsmCheck_A 00117909446000
tb.dut.gen_daon_por_assert.FpvSecCmDAonPorFsmCheck_A 00117909446000
tb.dut.gen_daon_por_io_assert.FpvSecCmDAonPorIoFsmCheck_A 00117909446000
tb.dut.gen_daon_por_io_div2_assert.FpvSecCmDAonPorIoDiv2FsmCheck_A 00117909446000
tb.dut.gen_daon_por_io_div4_assert.FpvSecCmDAonPorIoDiv4FsmCheck_A 00117909446000
tb.dut.gen_daon_por_usb_assert.FpvSecCmDAonPorUsbFsmCheck_A 00117909446000
tb.dut.gen_daon_sys_io_div4_assert.FpvSecCmDAonSysIoDiv4FsmCheck_A 00117909446000
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_prim_mubi4_sender.OutputsKnown_A 001697868105004100
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic.selKnown0 009421891600
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic.selKnown1 003082257700
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic.selKnown0 008967846200
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic.selKnown1 003082257700
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic.selKnown0 006884637900
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic.selKnown1 003082257700
tb.dut.gen_rst_por_aon[0].u_por_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.gen_rst_por_aon[0].u_por_scanmode_sync.OutputsKnown_A 0011790944699099500
tb.dut.gen_rst_por_aon[0].u_por_scanmode_sync.gen_no_flops.OutputDelay_A 0011790944699099500
tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic.selKnown0 008967846200
tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic.selKnown1 003082257700
tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_prim_mubi4_sender.OutputsKnown_A 001697868103115800
tb.dut.gen_rst_por_aon[1].u_por_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.gen_rst_por_aon[1].u_por_scanmode_sync.OutputsKnown_A 0011790944699099500
tb.dut.gen_rst_por_aon[1].u_por_scanmode_sync.gen_no_flops.OutputDelay_A 0011790944699099500
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[0].LcHandshakeOff_A 00117909441434700
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[0].LcHandshakeOn_A 001179094413210000
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[0].SysHandshakeOff_A 0011790944703322600
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[0].SysHandshakeOn_A 001179094421065600
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[1].LcHandshakeOff_A 00117909441434700
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[1].LcHandshakeOn_A 001179094413210000
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[1].SysHandshakeOff_A 0011790944703322600
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[1].SysHandshakeOn_A 001179094421065600
tb.dut.rstmgr_attrs_sva_if.AlertInfoAttr_A 0050550500
tb.dut.rstmgr_attrs_sva_if.CpuInfoAttr_A 0050550500
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorAboveFall_A 0055947315896700
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorAboveRise_A 0055947315896700
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoAboveFall_A 0053707812896700
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoAboveRise_A 0053707812896700
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoDiv2AboveFall_A 0026854629896700
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoDiv2AboveRise_A 0026854629896700
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoDiv4AboveFall_A 0013426987896700
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoDiv4AboveRise_A 0013426987896700
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorUcbAboveFall_A 0026854640896700
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorUcbAboveRise_A 0026854640896700
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcAboveFall_A 00559473152331400
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcAboveRise_A 00559473152331400
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcAonAboveFall_A 0016978682331400
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcAonAboveRise_A 0016978682331400
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcShadowedAboveFall_A 00559473152331400
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcShadowedAboveRise_A 00559473152331400
tb.dut.rstmgr_cascading_sva_if.CascadePorToAonAboveFall_A 001697868690200
tb.dut.rstmgr_cascading_sva_if.CascadeSysToSysAboveFall_A 00559473152331400
tb.dut.rstmgr_cascading_sva_if.CascadeSysToSysAboveRise_A 00559473152331400
tb.dut.rstmgr_cascading_sva_if.ScanRstToAonRise_A 00169786824100
tb.dut.rstmgr_cascading_sva_if.StablePorToAonRise_A 001697868896700
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].CascadeLcToSysAboveFall_A 00117909442331400
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].CascadeLcToSysAboveRise_A 00117909442331400
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].CascadeLocalRstToLcAboveFall_A 00117909442331400
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].CascadeLocalRstToLcAboveRise_A 00117909442331400
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A 00134269872331400
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A 00134269872331400
tb.dut.rstmgr_cascading_sva_if.g_power_domains[1].CascadeLcToSysAboveFall_A 00117909442331400
tb.dut.rstmgr_cascading_sva_if.g_power_domains[1].CascadeLcToSysAboveRise_A 00117909442331400
tb.dut.rstmgr_cascading_sva_if.g_power_domains[1].CascadeLocalRstToLcAboveFall_A 00117909442331400
tb.dut.rstmgr_cascading_sva_if.g_power_domains[1].CascadeLocalRstToLcAboveRise_A 00117909442331400
tb.dut.rstmgr_csr_assert.TlulOOBAddrErr_A 0012528607911300
tb.dut.rstmgr_csr_assert.alert_regwen_rd_A 0012528607586600
tb.dut.rstmgr_csr_assert.cpu_regwen_rd_A 0012528607590600
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_0_rd_A 0012528607988400
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_1_rd_A 0012528607971000
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_2_rd_A 0012528607978500
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_3_rd_A 0012528607972500
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_4_rd_A 0012528607967900
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_5_rd_A 00125286071003800
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_6_rd_A 0012528607977400
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_7_rd_A 0012528607976100
tb.dut.rstmgr_csr_assert.sw_rst_regwen_0_rd_A 0012528607599200
tb.dut.rstmgr_csr_assert.sw_rst_regwen_1_rd_A 0012528607617500
tb.dut.rstmgr_csr_assert.sw_rst_regwen_2_rd_A 0012528607626400
tb.dut.rstmgr_csr_assert.sw_rst_regwen_3_rd_A 0012528607611400
tb.dut.rstmgr_csr_assert.sw_rst_regwen_4_rd_A 0012528607604300
tb.dut.rstmgr_csr_assert.sw_rst_regwen_5_rd_A 0012528607603300
tb.dut.rstmgr_csr_assert.sw_rst_regwen_6_rd_A 0012528607598500
tb.dut.rstmgr_csr_assert.sw_rst_regwen_7_rd_A 0012528607614300
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c0EnTracksRstI2c0Active_A 00134269871568700
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c0EnTracksRstI2c0Inactive_A 00134269872454700
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c1EnTracksRstI2c1Active_A 00134269871576600
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c1EnTracksRstI2c1Inactive_A 00134269872461700
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c2EnTracksRstI2c2Active_A 00134269871581000
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c2EnTracksRstI2c2Inactive_A 00134269872465900
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoDiv2EnTracksRstLcIoDiv2Active_A 00268546291442000
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoDiv2EnTracksRstLcIoDiv2Inactive_A 00268546292331400
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoDiv4ShadowedEnTracksRstLcIoDiv4ShadowedActive_A 00134269871444700
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoDiv4ShadowedEnTracksRstLcIoDiv4ShadowedInactive_A 00134269872336400
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoEnTracksRstLcIoActive_A 00537078121441900
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoEnTracksRstLcIoInactive_A 00537078122331400
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcShadowedEnTracksRstLcShadowedActive_A 00559473151439700
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcShadowedEnTracksRstLcShadowedInactive_A 00559473152331400
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcUsbEnTracksRstLcUsbActive_A 00268546401442700
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcUsbEnTracksRstLcUsbInactive_A 00268546402331400
tb.dut.rstmgr_rst_en_track_sva_if.D0RstPorAonEnTracksRstPorAonActive_A 0016978685000
tb.dut.rstmgr_rst_en_track_sva_if.D0RstPorAonEnTracksRstPorAonInactive_A 001697868895100
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiDeviceEnTracksRstSpiDeviceActive_A 00134269871543600
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiDeviceEnTracksRstSpiDeviceInactive_A 00134269872429200
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiHost0EnTracksRstSpiHost0Active_A 00537078121550800
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiHost0EnTracksRstSpiHost0Inactive_A 00537078122435900
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiHost1EnTracksRstSpiHost1Active_A 00268546291554900
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiHost1EnTracksRstSpiHost1Inactive_A 00268546292439900
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSysEnTracksRstSysActive_A 00559473151441800
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSysEnTracksRstSysInactive_A 00559473152331400
tb.dut.rstmgr_rst_en_track_sva_if.D0RstUsbAonEnTracksRstUsbAonActive_A 0016978681511900
tb.dut.rstmgr_rst_en_track_sva_if.D0RstUsbAonEnTracksRstUsbAonInactive_A 0016978682354500
tb.dut.rstmgr_rst_en_track_sva_if.D0RstUsbEnTracksRstUsbActive_A 00268546401561100
tb.dut.rstmgr_rst_en_track_sva_if.D0RstUsbEnTracksRstUsbInactive_A 00268546402446900
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcAonEnTracksRstLcAonActive_A 0016978681437600
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcAonEnTracksRstLcAonInactive_A 0016978682329800
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoDiv2EnTracksRstLcIoDiv2Active_A 00268546291437700
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoDiv2EnTracksRstLcIoDiv2Inactive_A 00268546292331400
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoDiv4ShadowedEnTracksRstLcIoDiv4ShadowedActive_A 00134269871439700
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoDiv4ShadowedEnTracksRstLcIoDiv4ShadowedInactive_A 00134269872336400
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoEnTracksRstLcIoActive_A 00537078121436900
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoEnTracksRstLcIoInactive_A 00537078122331400
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcShadowedEnTracksRstLcShadowedActive_A 00559473151442200
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcShadowedEnTracksRstLcShadowedInactive_A 00559473152336400
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcUsbEnTracksRstLcUsbActive_A 00268546401437100
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcUsbEnTracksRstLcUsbInactive_A 00268546402331400
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorAonEnTracksRstPorAonInactive_A 001697868896700
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorEnTracksRstPorActive_A 00559473152400
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoDiv2EnTracksRstPorIoDiv2Active_A 00268546292500
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoDiv2EnTracksRstPorIoDiv2Inactive_A 0026854629225100
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoDiv4EnTracksRstPorIoDiv4Inactive_A 0013426987896700
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoEnTracksRstPorIoActive_A 00537078123100
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorUsbEnTracksRstPorUsbActive_A 00268546402800
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorUsbEnTracksRstPorUsbInactive_A 0026854640225100
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstSysIoDiv4EnTracksRstSysIoDiv4Active_A 00134269871437100
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstSysIoDiv4EnTracksRstSysIoDiv4Inactive_A 00134269872331400
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[0].RstEnOff_A 00134269871532100
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[0].RstEnOn_A 0013426987114900
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[0].RstNOff_A 00134269871532100
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[0].RstNOn_A 0013426987114900
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[1].RstEnOff_A 00537078121392600
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[1].RstEnOn_A 0053707812112600
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[1].RstNOff_A 00537078121392600
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[1].RstNOn_A 0053707812112600
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[2].RstEnOff_A 00268546291396400
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[2].RstEnOn_A 0026854629112800
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[2].RstNOff_A 00268546291396400
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[2].RstNOn_A 0026854629112800
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[3].RstEnOff_A 00268546401403400
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[3].RstEnOn_A 0026854640119100
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[3].RstNOff_A 00268546401403400
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[3].RstNOn_A 0026854640119100
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[4].RstEnOff_A 0016978682312300
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[4].RstEnOn_A 001697868124300
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[4].RstNOff_A 0016978682312300
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[4].RstNOn_A 001697868124300
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tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[5].RstEnOn_A 0013426987127400
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tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[7].RstNOn_A 0013426987138600
tb.dut.tlul_assert_device.aKnown_A 0012528607125439400
tb.dut.tlul_assert_device.aKnown_AKnownEnable 0012528607745534700
tb.dut.tlul_assert_device.aReadyKnown_A 0012528607745534700
tb.dut.tlul_assert_device.dKnown_A 0012528607218311800
tb.dut.tlul_assert_device.dKnown_AKnownEnable 0012528607745534700
tb.dut.tlul_assert_device.dReadyKnown_A 0012528607745534700
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tb.dut.tlul_assert_device.gen_assert_final[49].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[4].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[50].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[51].noOutstandingReqsAtEndOfSim_A 0062062000
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tb.dut.tlul_assert_device.gen_assert_final[53].noOutstandingReqsAtEndOfSim_A 0062062000
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tb.dut.tlul_assert_device.gen_assert_final[56].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[57].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[58].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[59].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[5].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[60].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[61].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[62].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[63].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[64].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[65].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[66].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[67].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[68].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[69].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[6].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[70].noOutstandingReqsAtEndOfSim_A 0062062000
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tb.dut.tlul_assert_device.gen_assert_final[72].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[73].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[74].noOutstandingReqsAtEndOfSim_A 0062062000
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tb.dut.tlul_assert_device.gen_assert_final[77].noOutstandingReqsAtEndOfSim_A 0062062000
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tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_device.aDataKnown_M 001252922754834700
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A 0012528607639100
tb.dut.tlul_assert_device.gen_device.contigMask_M 001252922792845300
tb.dut.tlul_assert_device.gen_device.dDataKnown_A 0012529227113585500
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A 0012528607696500
tb.dut.tlul_assert_device.gen_device.legalAParam_M 0012529227125454800
tb.dut.tlul_assert_device.gen_device.legalDParam_A 0012529227218324500
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M 0012529227125454800
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A 0012529227218324500
tb.dut.tlul_assert_device.gen_device.respOpcode_A 0012529227218324500
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A 0012529227218324500
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A 0012528607387700
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A 0012528607325900
tb.dut.tlul_assert_device.p_dbw.TlDbw_A 0062062000
tb.dut.u_alert_info.CntStoreSlot_A 0050550500
tb.dut.u_alert_info.CntWidth_A 0050550500
tb.dut.u_cpu_info.CntStoreSlot_A 0050550500
tb.dut.u_cpu_info.CntWidth_A 0050550500
tb.dut.u_ctrl_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_ctrl_scanmode_sync.OutputsKnown_A 0013426987821676900
tb.dut.u_ctrl_scanmode_sync.gen_no_flops.OutputDelay_A 0013426987821676900
tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00233642285900
tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 003082257700
tb.dut.u_d0_i2c0.u_prim_mubi4_sender.OutputsKnown_A 0013426987687942200
tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00245442403900
tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic.selKnown1 003082257700
tb.dut.u_d0_i2c0.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_d0_i2c0.u_scanmode_sync.OutputsKnown_A 0011790944699099500
tb.dut.u_d0_i2c0.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011790944699099500
tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00233642285900
tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 003082257700
tb.dut.u_d0_i2c1.u_prim_mubi4_sender.OutputsKnown_A 0013426987688156100
tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00246142410900
tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic.selKnown1 003082257700
tb.dut.u_d0_i2c1.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_d0_i2c1.u_scanmode_sync.OutputsKnown_A 0011790944699099500
tb.dut.u_d0_i2c1.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011790944699099500
tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00233642285900
tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 003082257700
tb.dut.u_d0_i2c2.u_prim_mubi4_sender.OutputsKnown_A 0013426987688429100
tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00246562415100
tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic.selKnown1 003082257700
tb.dut.u_d0_i2c2.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_d0_i2c2.u_scanmode_sync.OutputsKnown_A 0011790944699099500
tb.dut.u_d0_i2c2.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011790944699099500
tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00233642285900
tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 003082257700
tb.dut.u_d0_lc.u_prim_mubi4_sender.OutputsKnown_A 00559473152942287600
tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00233142280900
tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic.selKnown1 003082257700
tb.dut.u_d0_lc.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_d0_lc.u_scanmode_sync.OutputsKnown_A 0011790944699099500
tb.dut.u_d0_lc.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011790944699099500
tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00233642285900
tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 003082257700
tb.dut.u_d0_lc_io.u_prim_mubi4_sender.OutputsKnown_A 00537078122824397100
tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00233142280900
tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic.selKnown1 003082257700
tb.dut.u_d0_lc_io.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_d0_lc_io.u_scanmode_sync.OutputsKnown_A 0011790944699099500
tb.dut.u_d0_lc_io.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011790944699099500
tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00233642285900
tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 003082257700
tb.dut.u_d0_lc_io_div2.u_prim_mubi4_sender.OutputsKnown_A 00268546291411106300
tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00233142280900
tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown1 003082257700
tb.dut.u_d0_lc_io_div2.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_d0_lc_io_div2.u_scanmode_sync.OutputsKnown_A 0011790944699099500
tb.dut.u_d0_lc_io_div2.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011790944699099500
tb.dut.u_d0_lc_io_div4.u_prim_mubi4_sender.OutputsKnown_A 0013426987702602400
tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00233142280900
tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown1 003082257700
tb.dut.u_d0_lc_io_div4.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_d0_lc_io_div4.u_scanmode_sync.OutputsKnown_A 0011790944699099500
tb.dut.u_d0_lc_io_div4.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011790944699099500
tb.dut.u_d0_lc_io_div4_shadowed.u_prim_mubi4_sender.OutputsKnown_A 0013426987702602400
tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00233142280900
tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown1 003082257700
tb.dut.u_d0_lc_io_div4_shadowed.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_d0_lc_io_div4_shadowed.u_scanmode_sync.OutputsKnown_A 0011790944699099500
tb.dut.u_d0_lc_io_div4_shadowed.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011790944699099500
tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00233642285900
tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 003082257700
tb.dut.u_d0_lc_shadowed.u_prim_mubi4_sender.OutputsKnown_A 00559473152942409700
tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00233142280900
tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown1 003082257700
tb.dut.u_d0_lc_shadowed.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_d0_lc_shadowed.u_scanmode_sync.OutputsKnown_A 0011790944699099500
tb.dut.u_d0_lc_shadowed.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011790944699099500
tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00233642285900
tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 003082257700
tb.dut.u_d0_lc_usb.u_prim_mubi4_sender.OutputsKnown_A 00268546401411089100
tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00233142280900
tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown1 003082257700
tb.dut.u_d0_lc_usb.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_d0_lc_usb.u_scanmode_sync.OutputsKnown_A 0011790944699099500
tb.dut.u_d0_lc_usb.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011790944699099500
tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00233642285900
tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 003082257700
tb.dut.u_d0_spi_device.u_prim_mubi4_sender.OutputsKnown_A 0013426987687530600
tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00242882378300
tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic.selKnown1 003082257700
tb.dut.u_d0_spi_device.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_d0_spi_device.u_scanmode_sync.OutputsKnown_A 0011790944699099500
tb.dut.u_d0_spi_device.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011790944699099500
tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00233642285900
tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 003082257700
tb.dut.u_d0_spi_host0.u_prim_mubi4_sender.OutputsKnown_A 00537078122763976000
tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00243572385200
tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic.selKnown1 003082257700
tb.dut.u_d0_spi_host0.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_d0_spi_host0.u_scanmode_sync.OutputsKnown_A 0011790944699099500
tb.dut.u_d0_spi_host0.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011790944699099500
tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00233642285900
tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 003082257700
tb.dut.u_d0_spi_host1.u_prim_mubi4_sender.OutputsKnown_A 00268546291381562900
tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00243952389000
tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic.selKnown1 003082257700
tb.dut.u_d0_spi_host1.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_d0_spi_host1.u_scanmode_sync.OutputsKnown_A 0011790944699099500
tb.dut.u_d0_spi_host1.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011790944699099500
tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00233642285900
tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 003082257700
tb.dut.u_d0_sys.u_prim_mubi4_sender.OutputsKnown_A 00559473152909560600
tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00233142280900
tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic.selKnown1 003082257700
tb.dut.u_d0_sys.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_d0_sys.u_scanmode_sync.OutputsKnown_A 0011790944699099500
tb.dut.u_d0_sys.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011790944699099500
tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00233642285900
tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 003082257700
tb.dut.u_d0_usb.u_prim_mubi4_sender.OutputsKnown_A 00268546401381045900
tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00244652396000
tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown1 003082257700
tb.dut.u_d0_usb.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_d0_usb.u_scanmode_sync.OutputsKnown_A 0011790944699099500
tb.dut.u_d0_usb.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011790944699099500
tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00232482274300
tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 003082257700
tb.dut.u_d0_usb_aon.u_prim_mubi4_sender.OutputsKnown_A 00169786885674400
tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00245002399500
tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic.selKnown1 003082257700
tb.dut.u_d0_usb_aon.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_d0_usb_aon.u_scanmode_sync.OutputsKnown_A 0011790944699099500
tb.dut.u_d0_usb_aon.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011790944699099500
tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00233642285900
tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 003082257700
tb.dut.u_daon_lc.u_prim_mubi4_sender.OutputsKnown_A 00559473153016953800
tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00233142280900
tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic.selKnown1 003082257700
tb.dut.u_daon_lc.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_daon_lc.u_scanmode_sync.OutputsKnown_A 0011790944699099500
tb.dut.u_daon_lc.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011790944699099500
tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00232482274300
tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 003082257700
tb.dut.u_daon_lc_aon.u_prim_mubi4_sender.OutputsKnown_A 00169786889719800
tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00233142280900
tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic.selKnown1 003082257700
tb.dut.u_daon_lc_aon.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_daon_lc_aon.u_scanmode_sync.OutputsKnown_A 0011790944699099500
tb.dut.u_daon_lc_aon.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011790944699099500
tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00233642285900
tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 003082257700
tb.dut.u_daon_lc_io.u_prim_mubi4_sender.OutputsKnown_A 00537078122896294900
tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00233142280900
tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic.selKnown1 003082257700
tb.dut.u_daon_lc_io.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_daon_lc_io.u_scanmode_sync.OutputsKnown_A 0011790944699099500
tb.dut.u_daon_lc_io.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011790944699099500
tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00233642285900
tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 003082257700
tb.dut.u_daon_lc_io_div2.u_prim_mubi4_sender.OutputsKnown_A 00268546291447038300
tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00233142280900
tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown1 003082257700
tb.dut.u_daon_lc_io_div2.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_daon_lc_io_div2.u_scanmode_sync.OutputsKnown_A 0011790944699099500
tb.dut.u_daon_lc_io_div2.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011790944699099500
tb.dut.u_daon_lc_io_div4.u_prim_mubi4_sender.OutputsKnown_A 0013426987720578100
tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00233142280900
tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown1 003082257700
tb.dut.u_daon_lc_io_div4.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_daon_lc_io_div4.u_scanmode_sync.OutputsKnown_A 0011790944699099500
tb.dut.u_daon_lc_io_div4.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011790944699099500
tb.dut.u_daon_lc_io_div4_shadowed.u_prim_mubi4_sender.OutputsKnown_A 0013426987720578100
tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00233142280900
tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown1 003082257700
tb.dut.u_daon_lc_io_div4_shadowed.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_daon_lc_io_div4_shadowed.u_scanmode_sync.OutputsKnown_A 0011790944699099500
tb.dut.u_daon_lc_io_div4_shadowed.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011790944699099500
tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00233642285900
tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 003082257700
tb.dut.u_daon_lc_shadowed.u_prim_mubi4_sender.OutputsKnown_A 00559473153016957300
tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00233142280900
tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown1 003082257700
tb.dut.u_daon_lc_shadowed.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_daon_lc_shadowed.u_scanmode_sync.OutputsKnown_A 0011790944699099500
tb.dut.u_daon_lc_shadowed.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011790944699099500
tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00233642285900
tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 003082257700
tb.dut.u_daon_lc_usb.u_prim_mubi4_sender.OutputsKnown_A 00268546401447054100
tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00233142280900
tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown1 003082257700
tb.dut.u_daon_lc_usb.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_daon_lc_usb.u_scanmode_sync.OutputsKnown_A 0011790944699099500
tb.dut.u_daon_lc_usb.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011790944699099500
tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00233642285900
tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 003082257700
tb.dut.u_daon_por.u_prim_mubi4_sender.OutputsKnown_A 00559473153425955700
tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic.selKnown0 008967846200
tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic.selKnown1 003082257700
tb.dut.u_daon_por.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_daon_por.u_scanmode_sync.OutputsKnown_A 0011790944699099500
tb.dut.u_daon_por.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011790944699099500
tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00233642285900
tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 003082257700
tb.dut.u_daon_por_io.u_prim_mubi4_sender.OutputsKnown_A 00537078123288732100
tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic.selKnown0 008967846200
tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic.selKnown1 003082257700
tb.dut.u_daon_por_io.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_daon_por_io.u_scanmode_sync.OutputsKnown_A 0011790944699099500
tb.dut.u_daon_por_io.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011790944699099500
tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00233642285900
tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 003082257700
tb.dut.u_daon_por_io_div2.u_prim_mubi4_sender.OutputsKnown_A 00268546291644003300
tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown0 008967846200
tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown1 003082257700
tb.dut.u_daon_por_io_div2.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_daon_por_io_div2.u_scanmode_sync.OutputsKnown_A 0011790944699099500
tb.dut.u_daon_por_io_div2.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011790944699099500
tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00233642285900
tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 003082257700
tb.dut.u_daon_por_io_div4.u_prim_mubi4_sender.OutputsKnown_A 0013426987821676900
tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown0 008967846200
tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown1 003082257700
tb.dut.u_daon_por_io_div4.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_daon_por_io_div4.u_scanmode_sync.OutputsKnown_A 0011790944699099500
tb.dut.u_daon_por_io_div4.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011790944699099500
tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00233642285900
tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 003082257700
tb.dut.u_daon_por_usb.u_prim_mubi4_sender.OutputsKnown_A 00268546401643992700
tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown0 008967846200
tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown1 003082257700
tb.dut.u_daon_por_usb.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_daon_por_usb.u_scanmode_sync.OutputsKnown_A 0011790944699099500
tb.dut.u_daon_por_usb.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011790944699099500
tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00233642285900
tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 003082257700
tb.dut.u_daon_sys_io_div4.u_prim_mubi4_sender.OutputsKnown_A 0013426987712739700
tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00233142280900
tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown1 003082257700
tb.dut.u_daon_sys_io_div4.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_daon_sys_io_div4.u_scanmode_sync.OutputsKnown_A 0011790944699099500
tb.dut.u_daon_sys_io_div4.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011790944699099500
tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic.selKnown0 00233142280900
tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic.selKnown1 003082257700
tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic.selKnown0 00233142280900
tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic.selKnown1 003082257700
tb.dut.u_reg.en2addrHit 0012528607107818500
tb.dut.u_reg.reAfterRv 0012528607107808100
tb.dut.u_reg.rePulse 001252860757970800
tb.dut.u_reg.u_chk.PayLoadWidthCheck 0062062000
tb.dut.u_reg.u_reg_if.AllowedLatency_A 0062062000
tb.dut.u_reg.u_reg_if.MatchedWidthAssert 0062062000
tb.dut.u_reg.u_reg_if.u_err.dataWidthOnly32_A 0062062000
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A 0062062000
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck 0062062000
tb.dut.u_reg.u_rsp_intg_gen.DataWidthCheck_A 0062062000
tb.dut.u_reg.u_rsp_intg_gen.PayLoadWidthCheck 0062062000
tb.dut.u_reg.wePulse 001252860749837300
tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic.selKnown0 00233142280900
tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic.selKnown1 003082257700
tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic.selKnown0 00233142280900
tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic.selKnown1 003082257700


Detail Report for Cover Sequences

Cover Sequences All Matches:
COVER SEQUENCESCATEGORYSEVERITYATTEMPTSALL MATCHESFIRST MATCHESINCOMPLETESRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C 0012529227767676760
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C 0012529227319631960
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C 0012529227319931990
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C 0012529227223922390
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C 00125292271291290
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C 0012529227176117610
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C 0012529227113311330
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C 0012529227310331030
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C 001252922764162641620
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C 0012529227535961535961455

Cover Sequences First Matches:
COVER SEQUENCESCATEGORYSEVERITYATTEMPTSALL MATCHESFIRST MATCHESINCOMPLETESRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C 0012529227767676760
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C 0012529227319631960
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C 0012529227319931990
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C 0012529227223922390
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C 00125292271291290
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C 0012529227176117610
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C 0012529227113311330
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C 0012529227310331030
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C 001252922764162641620
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C 0012529227535961535961455

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