Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
9193 |
1 |
|
|
T1 |
8 |
|
T2 |
157 |
|
T3 |
235 |
auto[1] |
12045 |
1 |
|
|
T1 |
1 |
|
T2 |
204 |
|
T3 |
210 |
Summary for Variable reset_info_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for reset_info_cp
Excluded/Illegal bins
NAME | COUNT | STATUS |
others |
6477 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
reset_info_cp[1] |
7156 |
1 |
|
|
T1 |
1 |
|
T2 |
136 |
|
T3 |
144 |
reset_info_cp[2] |
3330 |
1 |
|
|
T2 |
62 |
|
T3 |
63 |
|
T6 |
4 |
reset_info_cp[4] |
4308 |
1 |
|
|
T2 |
75 |
|
T3 |
107 |
|
T6 |
16 |
reset_info_cp[8] |
119 |
1 |
|
|
T2 |
3 |
|
T3 |
2 |
|
T6 |
1 |
reset_info_cp[16] |
124 |
1 |
|
|
T2 |
1 |
|
T3 |
4 |
|
T12 |
2 |
reset_info_cp[32] |
113 |
1 |
|
|
T3 |
4 |
|
T4 |
1 |
|
T6 |
1 |
reset_info_cp[64] |
113 |
1 |
|
|
T1 |
1 |
|
T3 |
3 |
|
T6 |
1 |
reset_info_cp[128] |
118 |
1 |
|
|
T1 |
1 |
|
T3 |
4 |
|
T13 |
2 |
Summary for Cross capture_cross
Samples crossed: reset_info_cp enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
16 |
0 |
16 |
100.00 |
|
Automatically Generated Cross Bins for capture_cross
Bins
reset_info_cp | enable_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
reset_info_cp[1] |
auto[0] |
3438 |
1 |
|
|
T2 |
64 |
|
T3 |
81 |
|
T6 |
13 |
reset_info_cp[1] |
auto[1] |
3098 |
1 |
|
|
T2 |
71 |
|
T3 |
62 |
|
T6 |
10 |
reset_info_cp[2] |
auto[0] |
1064 |
1 |
|
|
T2 |
19 |
|
T3 |
27 |
|
T6 |
1 |
reset_info_cp[2] |
auto[1] |
2266 |
1 |
|
|
T2 |
43 |
|
T3 |
36 |
|
T6 |
3 |
reset_info_cp[4] |
auto[0] |
1624 |
1 |
|
|
T2 |
33 |
|
T3 |
59 |
|
T6 |
6 |
reset_info_cp[4] |
auto[1] |
2684 |
1 |
|
|
T2 |
42 |
|
T3 |
48 |
|
T6 |
10 |
reset_info_cp[8] |
auto[0] |
50 |
1 |
|
|
T2 |
1 |
|
T3 |
1 |
|
T12 |
1 |
reset_info_cp[8] |
auto[1] |
69 |
1 |
|
|
T2 |
2 |
|
T3 |
1 |
|
T6 |
1 |
reset_info_cp[16] |
auto[0] |
47 |
1 |
|
|
T3 |
1 |
|
T12 |
1 |
|
T132 |
1 |
reset_info_cp[16] |
auto[1] |
77 |
1 |
|
|
T2 |
1 |
|
T3 |
3 |
|
T12 |
1 |
reset_info_cp[32] |
auto[0] |
51 |
1 |
|
|
T3 |
2 |
|
T4 |
1 |
|
T6 |
1 |
reset_info_cp[32] |
auto[1] |
62 |
1 |
|
|
T3 |
2 |
|
T101 |
1 |
|
T102 |
1 |
reset_info_cp[64] |
auto[0] |
34 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T6 |
1 |
reset_info_cp[64] |
auto[1] |
79 |
1 |
|
|
T3 |
2 |
|
T42 |
1 |
|
T47 |
1 |
reset_info_cp[128] |
auto[0] |
50 |
1 |
|
|
T1 |
1 |
|
T13 |
1 |
|
T133 |
1 |
reset_info_cp[128] |
auto[1] |
68 |
1 |
|
|
T3 |
4 |
|
T13 |
1 |
|
T32 |
1 |