Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_access_cg
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Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_access_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv



Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_access_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00


Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_access_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
index_cp 8 0 8 100.00 100 1 1 0


Summary for Variable index_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for index_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
others 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid[0] 46100 1 T2 948 T3 1082 T6 172
valid[1] 37702 1 T2 718 T3 850 T6 132
valid[2] 37702 1 T2 718 T3 850 T6 132
valid[3] 37702 1 T2 718 T3 850 T6 132
valid[4] 37702 1 T2 718 T3 850 T6 132
valid[5] 37702 1 T2 718 T3 850 T6 132
valid[6] 37702 1 T2 718 T3 850 T6 132
valid[7] 37702 1 T2 718 T3 850 T6 132

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