Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.88 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T502 /workspace/coverage/default/43.rstmgr_stress_all.126029863 Dec 20 12:41:43 PM PST 23 Dec 20 12:43:09 PM PST 23 5774410241 ps
T503 /workspace/coverage/default/18.rstmgr_sw_rst.3645822835 Dec 20 12:41:14 PM PST 23 Dec 20 12:42:20 PM PST 23 369452882 ps
T504 /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.327831834 Dec 20 12:41:37 PM PST 23 Dec 20 12:42:42 PM PST 23 244822559 ps
T505 /workspace/coverage/default/36.rstmgr_stress_all.2773875690 Dec 20 12:41:24 PM PST 23 Dec 20 12:42:32 PM PST 23 732904319 ps
T506 /workspace/coverage/default/10.rstmgr_por_stretcher.1857507772 Dec 20 12:40:42 PM PST 23 Dec 20 12:41:46 PM PST 23 137362194 ps
T507 /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.3273549694 Dec 20 12:41:52 PM PST 23 Dec 20 12:42:54 PM PST 23 144489663 ps
T508 /workspace/coverage/default/12.rstmgr_smoke.2341446372 Dec 20 12:40:56 PM PST 23 Dec 20 12:42:02 PM PST 23 255869717 ps
T509 /workspace/coverage/default/41.rstmgr_reset.4019441213 Dec 20 12:43:29 PM PST 23 Dec 20 12:43:38 PM PST 23 1766502245 ps
T510 /workspace/coverage/default/1.rstmgr_sw_rst.990441805 Dec 20 12:41:33 PM PST 23 Dec 20 12:42:39 PM PST 23 365829173 ps
T511 /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.36874341 Dec 20 12:41:21 PM PST 23 Dec 20 12:42:27 PM PST 23 66857746 ps
T512 /workspace/coverage/default/23.rstmgr_alert_test.4287801984 Dec 20 12:41:12 PM PST 23 Dec 20 12:42:15 PM PST 23 62364400 ps
T513 /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.1436889112 Dec 20 12:40:29 PM PST 23 Dec 20 12:41:38 PM PST 23 1228241614 ps
T514 /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.2651213517 Dec 20 12:41:45 PM PST 23 Dec 20 12:42:49 PM PST 23 244651175 ps
T515 /workspace/coverage/default/21.rstmgr_sw_rst.4039877543 Dec 20 12:41:12 PM PST 23 Dec 20 12:42:17 PM PST 23 121830144 ps
T516 /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.1264103513 Dec 20 12:40:22 PM PST 23 Dec 20 12:41:24 PM PST 23 243700756 ps
T517 /workspace/coverage/default/16.rstmgr_alert_test.4007030461 Dec 20 12:43:15 PM PST 23 Dec 20 12:43:29 PM PST 23 59371287 ps
T518 /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.3361650370 Dec 20 12:41:14 PM PST 23 Dec 20 12:42:18 PM PST 23 157367507 ps
T519 /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.1703587647 Dec 20 12:41:37 PM PST 23 Dec 20 12:42:48 PM PST 23 2347428556 ps
T520 /workspace/coverage/default/32.rstmgr_stress_all.3908981893 Dec 20 12:41:17 PM PST 23 Dec 20 12:42:40 PM PST 23 5295447519 ps
T521 /workspace/coverage/default/48.rstmgr_alert_test.2590286910 Dec 20 12:41:40 PM PST 23 Dec 20 12:42:43 PM PST 23 63606657 ps
T522 /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.3594894224 Dec 20 12:40:51 PM PST 23 Dec 20 12:41:56 PM PST 23 175368439 ps
T523 /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.2194136836 Dec 20 12:41:10 PM PST 23 Dec 20 12:42:14 PM PST 23 101329146 ps
T524 /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.1795143299 Dec 20 12:40:48 PM PST 23 Dec 20 12:41:53 PM PST 23 84356957 ps
T525 /workspace/coverage/default/1.rstmgr_alert_test.2414709737 Dec 20 12:40:57 PM PST 23 Dec 20 12:42:03 PM PST 23 55896565 ps
T526 /workspace/coverage/default/20.rstmgr_sw_rst.1880204049 Dec 20 12:41:06 PM PST 23 Dec 20 12:42:11 PM PST 23 333493304 ps
T527 /workspace/coverage/default/5.rstmgr_reset.2258127807 Dec 20 12:40:47 PM PST 23 Dec 20 12:41:58 PM PST 23 1661011387 ps
T528 /workspace/coverage/default/1.rstmgr_stress_all.2081112961 Dec 20 12:41:01 PM PST 23 Dec 20 12:42:47 PM PST 23 13772397138 ps
T529 /workspace/coverage/default/18.rstmgr_smoke.101467423 Dec 20 12:41:14 PM PST 23 Dec 20 12:42:18 PM PST 23 256997026 ps
T530 /workspace/coverage/default/17.rstmgr_stress_all.3846435250 Dec 20 12:41:13 PM PST 23 Dec 20 12:42:24 PM PST 23 1551498140 ps
T531 /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.2355409510 Dec 20 12:40:48 PM PST 23 Dec 20 12:41:59 PM PST 23 2395847351 ps
T532 /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.1846706751 Dec 20 12:41:33 PM PST 23 Dec 20 12:42:44 PM PST 23 1907667477 ps
T533 /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.1126823608 Dec 20 12:41:09 PM PST 23 Dec 20 12:42:13 PM PST 23 243574005 ps
T534 /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.2753334160 Dec 20 12:41:33 PM PST 23 Dec 20 12:42:37 PM PST 23 142664280 ps
T535 /workspace/coverage/default/29.rstmgr_sw_rst.4073321547 Dec 20 12:41:26 PM PST 23 Dec 20 12:42:32 PM PST 23 242745157 ps
T536 /workspace/coverage/default/6.rstmgr_smoke.3181565120 Dec 20 12:40:59 PM PST 23 Dec 20 12:42:05 PM PST 23 227940688 ps
T537 /workspace/coverage/default/16.rstmgr_sw_rst.3087284312 Dec 20 12:43:14 PM PST 23 Dec 20 12:43:30 PM PST 23 283569349 ps
T538 /workspace/coverage/default/38.rstmgr_smoke.256828502 Dec 20 12:41:32 PM PST 23 Dec 20 12:42:38 PM PST 23 128456545 ps
T539 /workspace/coverage/default/39.rstmgr_reset.2034670522 Dec 20 12:41:35 PM PST 23 Dec 20 12:42:42 PM PST 23 897702002 ps
T540 /workspace/coverage/default/41.rstmgr_alert_test.3463162936 Dec 20 12:41:39 PM PST 23 Dec 20 12:42:43 PM PST 23 68456643 ps
T541 /workspace/coverage/default/48.rstmgr_smoke.1837500253 Dec 20 12:41:37 PM PST 23 Dec 20 12:42:43 PM PST 23 255237077 ps
T542 /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.588604108 Dec 20 12:40:22 PM PST 23 Dec 20 12:41:24 PM PST 23 243740627 ps
T543 /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.3151849222 Dec 20 12:40:52 PM PST 23 Dec 20 12:41:57 PM PST 23 110498444 ps
T544 /workspace/coverage/default/33.rstmgr_por_stretcher.267404154 Dec 20 12:41:16 PM PST 23 Dec 20 12:42:21 PM PST 23 214082867 ps
T545 /workspace/coverage/default/43.rstmgr_reset.1073302284 Dec 20 12:41:33 PM PST 23 Dec 20 12:42:42 PM PST 23 1744380122 ps
T546 /workspace/coverage/default/21.rstmgr_por_stretcher.1029287245 Dec 20 12:43:38 PM PST 23 Dec 20 12:43:40 PM PST 23 209375441 ps
T547 /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.2673370053 Dec 20 12:41:46 PM PST 23 Dec 20 12:42:50 PM PST 23 181158676 ps
T548 /workspace/coverage/default/26.rstmgr_alert_test.3299253749 Dec 20 12:41:14 PM PST 23 Dec 20 12:42:18 PM PST 23 62406174 ps
T549 /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.1892562648 Dec 20 12:40:46 PM PST 23 Dec 20 12:41:51 PM PST 23 229401103 ps
T550 /workspace/coverage/default/31.rstmgr_reset.797867142 Dec 20 12:41:08 PM PST 23 Dec 20 12:42:16 PM PST 23 807711016 ps
T551 /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.1461700285 Dec 20 12:41:13 PM PST 23 Dec 20 12:42:17 PM PST 23 174790038 ps
T552 /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.220894914 Dec 20 12:43:33 PM PST 23 Dec 20 12:43:37 PM PST 23 150818790 ps
T553 /workspace/coverage/default/12.rstmgr_alert_test.2768572307 Dec 20 12:41:03 PM PST 23 Dec 20 12:42:07 PM PST 23 72913043 ps
T554 /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.198741206 Dec 20 12:41:05 PM PST 23 Dec 20 12:42:14 PM PST 23 1224922252 ps
T555 /workspace/coverage/default/25.rstmgr_stress_all.3193492634 Dec 20 12:41:01 PM PST 23 Dec 20 12:42:13 PM PST 23 1363793953 ps
T556 /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.699533926 Dec 20 12:43:48 PM PST 23 Dec 20 12:43:56 PM PST 23 1904838591 ps
T557 /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.1187598478 Dec 20 12:41:34 PM PST 23 Dec 20 12:42:40 PM PST 23 148116276 ps
T558 /workspace/coverage/default/5.rstmgr_alert_test.471916250 Dec 20 12:41:05 PM PST 23 Dec 20 12:42:10 PM PST 23 81896807 ps
T559 /workspace/coverage/default/0.rstmgr_smoke.659861802 Dec 20 12:40:20 PM PST 23 Dec 20 12:41:22 PM PST 23 203708171 ps
T560 /workspace/coverage/default/39.rstmgr_stress_all.432063512 Dec 20 12:41:36 PM PST 23 Dec 20 12:43:03 PM PST 23 5201494083 ps
T561 /workspace/coverage/default/0.rstmgr_sw_rst.3339930165 Dec 20 12:40:35 PM PST 23 Dec 20 12:41:42 PM PST 23 341364740 ps
T562 /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.3946571719 Dec 20 12:40:55 PM PST 23 Dec 20 12:42:01 PM PST 23 114608649 ps
T563 /workspace/coverage/default/8.rstmgr_por_stretcher.2021771051 Dec 20 12:43:23 PM PST 23 Dec 20 12:43:30 PM PST 23 147370319 ps
T564 /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.183312906 Dec 20 12:41:01 PM PST 23 Dec 20 12:42:06 PM PST 23 66854701 ps
T565 /workspace/coverage/default/22.rstmgr_por_stretcher.3292451097 Dec 20 12:41:04 PM PST 23 Dec 20 12:42:08 PM PST 23 189359324 ps
T566 /workspace/coverage/default/30.rstmgr_sw_rst.3075034776 Dec 20 12:41:07 PM PST 23 Dec 20 12:42:12 PM PST 23 139200207 ps
T567 /workspace/coverage/default/24.rstmgr_stress_all.3593842932 Dec 20 12:41:12 PM PST 23 Dec 20 12:42:44 PM PST 23 6288165527 ps
T568 /workspace/coverage/default/28.rstmgr_smoke.2822332499 Dec 20 12:41:12 PM PST 23 Dec 20 12:42:16 PM PST 23 122367730 ps
T569 /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.1326797132 Dec 20 12:41:39 PM PST 23 Dec 20 12:42:49 PM PST 23 2189001461 ps
T570 /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.3126956389 Dec 20 12:41:19 PM PST 23 Dec 20 12:42:25 PM PST 23 243902525 ps
T571 /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.2424563935 Dec 20 12:41:33 PM PST 23 Dec 20 12:42:42 PM PST 23 1219077267 ps
T572 /workspace/coverage/default/20.rstmgr_smoke.2676414797 Dec 20 12:41:09 PM PST 23 Dec 20 12:42:13 PM PST 23 115989054 ps
T573 /workspace/coverage/default/17.rstmgr_reset.1337446448 Dec 20 12:41:10 PM PST 23 Dec 20 12:42:19 PM PST 23 759447648 ps
T574 /workspace/coverage/default/14.rstmgr_smoke.2424110230 Dec 20 12:40:54 PM PST 23 Dec 20 12:42:00 PM PST 23 124949575 ps
T575 /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.3897649090 Dec 20 12:41:36 PM PST 23 Dec 20 12:42:40 PM PST 23 108489939 ps
T576 /workspace/coverage/default/14.rstmgr_reset.182260907 Dec 20 12:40:54 PM PST 23 Dec 20 12:42:02 PM PST 23 719823526 ps
T577 /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.3442281360 Dec 20 12:41:49 PM PST 23 Dec 20 12:42:54 PM PST 23 243440208 ps
T578 /workspace/coverage/default/47.rstmgr_alert_test.1404478212 Dec 20 12:41:36 PM PST 23 Dec 20 12:42:40 PM PST 23 81914636 ps
T579 /workspace/coverage/default/38.rstmgr_alert_test.1440990221 Dec 20 12:41:54 PM PST 23 Dec 20 12:42:55 PM PST 23 72952105 ps
T580 /workspace/coverage/default/30.rstmgr_por_stretcher.3119910210 Dec 20 12:41:12 PM PST 23 Dec 20 12:42:15 PM PST 23 240033146 ps
T581 /workspace/coverage/default/37.rstmgr_reset.24600866 Dec 20 12:41:39 PM PST 23 Dec 20 12:42:48 PM PST 23 1837542474 ps
T582 /workspace/coverage/default/46.rstmgr_alert_test.4055492133 Dec 20 12:41:37 PM PST 23 Dec 20 12:42:43 PM PST 23 80486312 ps
T583 /workspace/coverage/default/29.rstmgr_stress_all.3115487239 Dec 20 12:41:27 PM PST 23 Dec 20 12:42:50 PM PST 23 4800652351 ps
T584 /workspace/coverage/default/42.rstmgr_stress_all.3535941880 Dec 20 12:41:38 PM PST 23 Dec 20 12:43:30 PM PST 23 15679656607 ps
T585 /workspace/coverage/default/13.rstmgr_stress_all.431688466 Dec 20 12:40:50 PM PST 23 Dec 20 12:41:56 PM PST 23 322125182 ps
T586 /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.3724853598 Dec 20 12:40:52 PM PST 23 Dec 20 12:41:58 PM PST 23 165652037 ps
T587 /workspace/coverage/default/35.rstmgr_reset.2097398110 Dec 20 12:41:33 PM PST 23 Dec 20 12:42:43 PM PST 23 1674492871 ps
T588 /workspace/coverage/default/47.rstmgr_smoke.1429954981 Dec 20 12:43:28 PM PST 23 Dec 20 12:43:32 PM PST 23 258579287 ps
T589 /workspace/coverage/default/1.rstmgr_por_stretcher.1943262340 Dec 20 12:41:00 PM PST 23 Dec 20 12:42:04 PM PST 23 191650056 ps
T590 /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.2207334599 Dec 20 12:43:27 PM PST 23 Dec 20 12:43:37 PM PST 23 1229758667 ps
T591 /workspace/coverage/default/48.rstmgr_stress_all.3599277115 Dec 20 12:43:52 PM PST 23 Dec 20 12:44:10 PM PST 23 4215734392 ps
T592 /workspace/coverage/default/13.rstmgr_smoke.4148188503 Dec 20 12:42:58 PM PST 23 Dec 20 12:43:28 PM PST 23 241956930 ps
T593 /workspace/coverage/default/29.rstmgr_smoke.219877721 Dec 20 12:41:13 PM PST 23 Dec 20 12:42:18 PM PST 23 250530554 ps
T594 /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.393214757 Dec 20 12:41:36 PM PST 23 Dec 20 12:42:40 PM PST 23 244162769 ps
T595 /workspace/coverage/default/38.rstmgr_stress_all.507467940 Dec 20 12:41:34 PM PST 23 Dec 20 12:43:33 PM PST 23 14556442325 ps
T596 /workspace/coverage/default/3.rstmgr_reset.3030351682 Dec 20 12:41:48 PM PST 23 Dec 20 12:42:55 PM PST 23 884586883 ps
T597 /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.2927868266 Dec 20 12:40:42 PM PST 23 Dec 20 12:41:51 PM PST 23 1229621175 ps
T598 /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.4191573066 Dec 20 12:41:18 PM PST 23 Dec 20 12:42:24 PM PST 23 213121216 ps
T599 /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.245254846 Dec 20 12:41:42 PM PST 23 Dec 20 12:42:55 PM PST 23 2367174767 ps
T600 /workspace/coverage/default/40.rstmgr_reset.1256172967 Dec 20 12:43:29 PM PST 23 Dec 20 12:43:37 PM PST 23 1356256400 ps
T601 /workspace/coverage/default/43.rstmgr_alert_test.1927902273 Dec 20 12:41:39 PM PST 23 Dec 20 12:42:43 PM PST 23 70702473 ps
T602 /workspace/coverage/default/16.rstmgr_por_stretcher.655455586 Dec 20 12:40:34 PM PST 23 Dec 20 12:41:36 PM PST 23 83858243 ps
T77 /workspace/coverage/default/1.rstmgr_sec_cm.680857122 Dec 20 12:41:33 PM PST 23 Dec 20 12:42:49 PM PST 23 8543104173 ps
T603 /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.2017696324 Dec 20 12:41:17 PM PST 23 Dec 20 12:42:28 PM PST 23 1886509117 ps
T604 /workspace/coverage/default/4.rstmgr_por_stretcher.3446605349 Dec 20 12:40:27 PM PST 23 Dec 20 12:41:29 PM PST 23 120578651 ps
T605 /workspace/coverage/default/34.rstmgr_alert_test.1913224947 Dec 20 12:41:35 PM PST 23 Dec 20 12:42:40 PM PST 23 76288802 ps
T606 /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.3053430891 Dec 20 12:40:51 PM PST 23 Dec 20 12:41:56 PM PST 23 184789545 ps
T607 /workspace/coverage/default/6.rstmgr_sw_rst.1710248744 Dec 20 12:40:33 PM PST 23 Dec 20 12:41:37 PM PST 23 149065644 ps
T608 /workspace/coverage/default/42.rstmgr_por_stretcher.3217803318 Dec 20 12:41:37 PM PST 23 Dec 20 12:42:41 PM PST 23 149534732 ps
T609 /workspace/coverage/default/10.rstmgr_reset.3646304785 Dec 20 12:40:45 PM PST 23 Dec 20 12:41:53 PM PST 23 792408887 ps
T610 /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.1908797009 Dec 20 12:41:07 PM PST 23 Dec 20 12:42:21 PM PST 23 2344809195 ps
T611 /workspace/coverage/default/8.rstmgr_stress_all.2417264922 Dec 20 12:40:53 PM PST 23 Dec 20 12:42:13 PM PST 23 3984639640 ps
T612 /workspace/coverage/default/33.rstmgr_alert_test.848396629 Dec 20 12:41:32 PM PST 23 Dec 20 12:42:35 PM PST 23 66483475 ps
T613 /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.398731738 Dec 20 12:41:35 PM PST 23 Dec 20 12:42:40 PM PST 23 245411830 ps
T614 /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.382349650 Dec 20 12:41:03 PM PST 23 Dec 20 12:42:14 PM PST 23 1875043065 ps
T615 /workspace/coverage/default/45.rstmgr_stress_all.3658765640 Dec 20 12:41:36 PM PST 23 Dec 20 12:43:02 PM PST 23 5531232001 ps
T616 /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.4251301782 Dec 20 12:43:48 PM PST 23 Dec 20 12:43:50 PM PST 23 67537236 ps
T617 /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.510692875 Dec 20 12:41:35 PM PST 23 Dec 20 12:42:39 PM PST 23 164996059 ps
T618 /workspace/coverage/default/12.rstmgr_reset.1636102501 Dec 20 12:40:48 PM PST 23 Dec 20 12:41:59 PM PST 23 1835620075 ps
T619 /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.2864713122 Dec 20 12:41:02 PM PST 23 Dec 20 12:42:07 PM PST 23 156985729 ps
T620 /workspace/coverage/default/17.rstmgr_sw_rst.665334544 Dec 20 12:41:10 PM PST 23 Dec 20 12:42:17 PM PST 23 292457918 ps

Test location /workspace/coverage/default/19.rstmgr_stress_all.3151021838
Short name T3
Test name
Test status
Simulation time 7260181166 ps
CPU time 34.03 seconds
Started Dec 20 12:41:02 PM PST 23
Finished Dec 20 12:42:41 PM PST 23
Peak memory 199568 kb
Host smart-e07ee879-409e-41ba-8a86-b31e5f143074
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151021838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.3151021838
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.1007498254
Short name T62
Test name
Test status
Simulation time 493124613 ps
CPU time 2.41 seconds
Started Dec 20 12:40:35 PM PST 23
Finished Dec 20 12:41:40 PM PST 23
Peak memory 199340 kb
Host smart-a7b77b21-b543-4b01-a30f-d36f3eaed631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007498254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.1007498254
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.1102971154
Short name T65
Test name
Test status
Simulation time 474572240 ps
CPU time 1.86 seconds
Started Dec 20 12:23:29 PM PST 23
Finished Dec 20 12:24:08 PM PST 23
Peak memory 199596 kb
Host smart-40be08fe-39ca-4d72-a3c4-d52f91569cf9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102971154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.1102971154
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.1866541738
Short name T73
Test name
Test status
Simulation time 8328384477 ps
CPU time 12.87 seconds
Started Dec 20 12:40:25 PM PST 23
Finished Dec 20 12:41:37 PM PST 23
Peak memory 217140 kb
Host smart-32840050-2826-453c-9ca9-6abff943ce19
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866541738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.1866541738
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.91966531
Short name T91
Test name
Test status
Simulation time 158824824 ps
CPU time 1.97 seconds
Started Dec 20 12:23:29 PM PST 23
Finished Dec 20 12:24:08 PM PST 23
Peak memory 199720 kb
Host smart-e5c280c8-0a1f-4df5-9898-14807efe331e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91966531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.91966531
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.303910585
Short name T32
Test name
Test status
Simulation time 1226505646 ps
CPU time 5.47 seconds
Started Dec 20 12:41:01 PM PST 23
Finished Dec 20 12:42:11 PM PST 23
Peak memory 217320 kb
Host smart-5f168dac-1e3b-4181-b572-a20249c0c486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303910585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.303910585
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.2177453258
Short name T75
Test name
Test status
Simulation time 61731991 ps
CPU time 0.7 seconds
Started Dec 20 12:41:12 PM PST 23
Finished Dec 20 12:42:16 PM PST 23
Peak memory 199064 kb
Host smart-d626deae-a674-42ea-85b3-a270e65abbc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177453258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.2177453258
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.178802593
Short name T26
Test name
Test status
Simulation time 104291083 ps
CPU time 1.01 seconds
Started Dec 20 12:42:58 PM PST 23
Finished Dec 20 12:43:27 PM PST 23
Peak memory 197960 kb
Host smart-2e2c7438-fc9e-4f56-a392-e1782311640a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178802593 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.178802593
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_reset.1321335476
Short name T126
Test name
Test status
Simulation time 1727000783 ps
CPU time 6.86 seconds
Started Dec 20 12:41:13 PM PST 23
Finished Dec 20 12:42:24 PM PST 23
Peak memory 199640 kb
Host smart-fbff5284-c445-4645-955d-88d62fc168c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321335476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.1321335476
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.805204312
Short name T38
Test name
Test status
Simulation time 1227455759 ps
CPU time 4.94 seconds
Started Dec 20 12:40:48 PM PST 23
Finished Dec 20 12:41:57 PM PST 23
Peak memory 217084 kb
Host smart-cf9eff2d-49b1-4c65-8d13-1ad4bee80766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805204312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.805204312
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.3538592398
Short name T68
Test name
Test status
Simulation time 792285151 ps
CPU time 2.59 seconds
Started Dec 20 12:23:36 PM PST 23
Finished Dec 20 12:24:17 PM PST 23
Peak memory 199752 kb
Host smart-73d3be8b-a1ce-47fa-8a11-058a97f7aaf2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538592398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.3538592398
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2482896733
Short name T99
Test name
Test status
Simulation time 132898206 ps
CPU time 1.09 seconds
Started Dec 20 12:23:36 PM PST 23
Finished Dec 20 12:24:14 PM PST 23
Peak memory 199736 kb
Host smart-eb47dd31-d829-4220-b565-2f8393ad3e23
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482896733 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.2482896733
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.2531007100
Short name T130
Test name
Test status
Simulation time 894043566 ps
CPU time 3.34 seconds
Started Dec 20 12:23:37 PM PST 23
Finished Dec 20 12:24:18 PM PST 23
Peak memory 199752 kb
Host smart-c0b5cb11-133f-4481-81f7-fac18ef567d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531007100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.2531007100
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.3864267261
Short name T59
Test name
Test status
Simulation time 1220948418 ps
CPU time 5.26 seconds
Started Dec 20 12:41:14 PM PST 23
Finished Dec 20 12:42:23 PM PST 23
Peak memory 216304 kb
Host smart-aa83afaf-f810-4aa9-a0a4-72cbbc5fad88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864267261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.3864267261
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.3003904637
Short name T93
Test name
Test status
Simulation time 181659112 ps
CPU time 2.4 seconds
Started Dec 20 12:23:13 PM PST 23
Finished Dec 20 12:23:41 PM PST 23
Peak memory 199804 kb
Host smart-bfe24eec-30bc-4c8d-afff-ed2b030d3f68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003904637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.3003904637
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.2278125508
Short name T64
Test name
Test status
Simulation time 134945376 ps
CPU time 1.16 seconds
Started Dec 20 12:23:24 PM PST 23
Finished Dec 20 12:24:01 PM PST 23
Peak memory 199768 kb
Host smart-6ca61db0-103d-4d58-a6fa-b36f17efb652
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278125508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.2278125508
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.3111254032
Short name T21
Test name
Test status
Simulation time 159068079 ps
CPU time 0.8 seconds
Started Dec 20 12:40:54 PM PST 23
Finished Dec 20 12:41:59 PM PST 23
Peak memory 198916 kb
Host smart-0894d258-6f41-4bc7-93c2-81c17c337b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111254032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.3111254032
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.144796149
Short name T5
Test name
Test status
Simulation time 244621198 ps
CPU time 1.1 seconds
Started Dec 20 12:41:00 PM PST 23
Finished Dec 20 12:42:05 PM PST 23
Peak memory 216484 kb
Host smart-7eb17fba-7665-498f-ae97-1a1605119170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144796149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.144796149
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.1767227706
Short name T116
Test name
Test status
Simulation time 430912396 ps
CPU time 1.83 seconds
Started Dec 20 12:23:10 PM PST 23
Finished Dec 20 12:23:38 PM PST 23
Peak memory 199628 kb
Host smart-16725034-3b30-4d27-8d5a-24237b017f8d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767227706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.1767227706
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3055848689
Short name T86
Test name
Test status
Simulation time 911115266 ps
CPU time 2.93 seconds
Started Dec 20 12:25:06 PM PST 23
Finished Dec 20 12:25:29 PM PST 23
Peak memory 197880 kb
Host smart-ecf279a4-f273-4c2e-a394-da927ce055de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055848689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.3055848689
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.3339838757
Short name T120
Test name
Test status
Simulation time 424613837 ps
CPU time 1.75 seconds
Started Dec 20 12:23:24 PM PST 23
Finished Dec 20 12:23:59 PM PST 23
Peak memory 199752 kb
Host smart-b4dfd480-6a87-49ad-adcd-01be1a56ba3d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339838757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.3339838757
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2511343781
Short name T221
Test name
Test status
Simulation time 344030805 ps
CPU time 2.55 seconds
Started Dec 20 12:22:53 PM PST 23
Finished Dec 20 12:23:26 PM PST 23
Peak memory 199728 kb
Host smart-d5662a20-1d26-441d-94f8-ef38244eb850
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511343781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.2
511343781
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.4266869486
Short name T243
Test name
Test status
Simulation time 278573220 ps
CPU time 2.94 seconds
Started Dec 20 12:22:59 PM PST 23
Finished Dec 20 12:23:30 PM PST 23
Peak memory 199740 kb
Host smart-b6722c24-5e86-4dcc-82eb-768d57a07c92
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266869486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.4
266869486
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.4075760497
Short name T246
Test name
Test status
Simulation time 101872223 ps
CPU time 0.8 seconds
Started Dec 20 12:23:01 PM PST 23
Finished Dec 20 12:23:30 PM PST 23
Peak memory 199648 kb
Host smart-2034fc83-1e04-4c46-941d-0cf79a488123
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075760497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.4
075760497
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.161187527
Short name T190
Test name
Test status
Simulation time 123773639 ps
CPU time 1.04 seconds
Started Dec 20 12:23:21 PM PST 23
Finished Dec 20 12:23:53 PM PST 23
Peak memory 199764 kb
Host smart-f3757043-5736-4003-997b-8b6c9674a561
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161187527 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.161187527
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.3413691161
Short name T224
Test name
Test status
Simulation time 62941477 ps
CPU time 0.7 seconds
Started Dec 20 12:22:59 PM PST 23
Finished Dec 20 12:23:37 PM PST 23
Peak memory 199672 kb
Host smart-16089a49-3918-4776-bd0b-d124e6e43716
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413691161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.3413691161
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3740329248
Short name T247
Test name
Test status
Simulation time 222649733 ps
CPU time 1.44 seconds
Started Dec 20 12:22:58 PM PST 23
Finished Dec 20 12:23:29 PM PST 23
Peak memory 199792 kb
Host smart-7876434c-1ef0-42fe-8102-0ad810ba0169
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740329248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.3740329248
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.1841691046
Short name T226
Test name
Test status
Simulation time 159566356 ps
CPU time 2.29 seconds
Started Dec 20 12:23:20 PM PST 23
Finished Dec 20 12:23:51 PM PST 23
Peak memory 199760 kb
Host smart-c7f9b772-99e0-4480-9fad-267dbc6ba01b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841691046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.1841691046
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.738146710
Short name T209
Test name
Test status
Simulation time 954997847 ps
CPU time 3.23 seconds
Started Dec 20 12:23:13 PM PST 23
Finished Dec 20 12:23:42 PM PST 23
Peak memory 199832 kb
Host smart-b1876e01-c6e1-4a65-8f33-bef09996ad74
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738146710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err.
738146710
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.2752840575
Short name T194
Test name
Test status
Simulation time 256731193 ps
CPU time 1.6 seconds
Started Dec 20 12:23:24 PM PST 23
Finished Dec 20 12:24:01 PM PST 23
Peak memory 199740 kb
Host smart-208a201a-fa8d-410a-a186-aa73d7febd54
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752840575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.2
752840575
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.2340946019
Short name T219
Test name
Test status
Simulation time 482734514 ps
CPU time 5.58 seconds
Started Dec 20 12:23:27 PM PST 23
Finished Dec 20 12:24:08 PM PST 23
Peak memory 199796 kb
Host smart-a4777ff6-26cf-44a0-9e8f-f9cbe80b0ee3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340946019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.2
340946019
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.4122553697
Short name T63
Test name
Test status
Simulation time 152485785 ps
CPU time 1.02 seconds
Started Dec 20 12:23:28 PM PST 23
Finished Dec 20 12:24:07 PM PST 23
Peak memory 199620 kb
Host smart-56978588-9054-4637-a040-75ab6c4c784b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122553697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.4
122553697
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3821949949
Short name T67
Test name
Test status
Simulation time 132990234 ps
CPU time 1.01 seconds
Started Dec 20 12:23:22 PM PST 23
Finished Dec 20 12:23:56 PM PST 23
Peak memory 199736 kb
Host smart-40b319b6-8961-49ba-a1e9-5f309dbc55f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821949949 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.3821949949
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.1254109041
Short name T238
Test name
Test status
Simulation time 85484603 ps
CPU time 0.83 seconds
Started Dec 20 12:23:07 PM PST 23
Finished Dec 20 12:23:36 PM PST 23
Peak memory 199604 kb
Host smart-c8740a69-31dc-4e78-8756-bb6e20d52b14
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254109041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.1254109041
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.2641013970
Short name T213
Test name
Test status
Simulation time 419531700 ps
CPU time 2.76 seconds
Started Dec 20 12:23:24 PM PST 23
Finished Dec 20 12:24:01 PM PST 23
Peak memory 215940 kb
Host smart-e73a2cc9-271c-4916-9735-995b645df50e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641013970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.2641013970
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.874279981
Short name T186
Test name
Test status
Simulation time 106785164 ps
CPU time 1.04 seconds
Started Dec 20 12:23:38 PM PST 23
Finished Dec 20 12:24:17 PM PST 23
Peak memory 199632 kb
Host smart-616a56c2-054f-44df-983c-ce4025e40028
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874279981 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.874279981
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.3957927132
Short name T241
Test name
Test status
Simulation time 70575429 ps
CPU time 0.73 seconds
Started Dec 20 12:23:36 PM PST 23
Finished Dec 20 12:24:14 PM PST 23
Peak memory 199632 kb
Host smart-ca936715-851b-416d-99b7-057763945c63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957927132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.3957927132
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.3365884269
Short name T200
Test name
Test status
Simulation time 225195343 ps
CPU time 1.54 seconds
Started Dec 20 12:23:37 PM PST 23
Finished Dec 20 12:24:17 PM PST 23
Peak memory 199800 kb
Host smart-9b96b04d-5fd0-43b5-91a0-35f1580ec0d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365884269 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.3365884269
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.897201452
Short name T215
Test name
Test status
Simulation time 196200080 ps
CPU time 2.82 seconds
Started Dec 20 12:23:50 PM PST 23
Finished Dec 20 12:24:34 PM PST 23
Peak memory 199704 kb
Host smart-1e5ad160-f008-42d7-bc67-757e1066bcf4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897201452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.897201452
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.1575764612
Short name T195
Test name
Test status
Simulation time 439200562 ps
CPU time 1.71 seconds
Started Dec 20 12:23:27 PM PST 23
Finished Dec 20 12:24:06 PM PST 23
Peak memory 199784 kb
Host smart-8e8d1386-5a04-46a2-9138-ccb7f7c358b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575764612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.1575764612
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.3114630645
Short name T96
Test name
Test status
Simulation time 150118591 ps
CPU time 0.98 seconds
Started Dec 20 12:23:22 PM PST 23
Finished Dec 20 12:23:56 PM PST 23
Peak memory 199708 kb
Host smart-960cdaf3-efa1-4ef1-968b-1cd8a8ad543b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114630645 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.3114630645
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.2893689824
Short name T127
Test name
Test status
Simulation time 66903067 ps
CPU time 0.77 seconds
Started Dec 20 12:23:30 PM PST 23
Finished Dec 20 12:24:08 PM PST 23
Peak memory 199568 kb
Host smart-83004b3b-1d30-43a9-ae6d-15200ce83f9a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893689824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.2893689824
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.3969194090
Short name T228
Test name
Test status
Simulation time 160564888 ps
CPU time 1.08 seconds
Started Dec 20 12:23:36 PM PST 23
Finished Dec 20 12:24:14 PM PST 23
Peak memory 199608 kb
Host smart-5d8c7fcb-6efa-458f-9697-d0d9af62676e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969194090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.3969194090
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.2121620946
Short name T122
Test name
Test status
Simulation time 255984844 ps
CPU time 1.79 seconds
Started Dec 20 12:23:29 PM PST 23
Finished Dec 20 12:24:08 PM PST 23
Peak memory 207984 kb
Host smart-45fd0f39-9969-47c1-ba35-c12373410868
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121620946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.2121620946
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.2106331068
Short name T211
Test name
Test status
Simulation time 113285181 ps
CPU time 1.04 seconds
Started Dec 20 12:24:00 PM PST 23
Finished Dec 20 12:24:40 PM PST 23
Peak memory 199700 kb
Host smart-7c754c6e-137f-47a5-ad92-2a79ed8dbe47
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106331068 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.2106331068
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.2687282137
Short name T203
Test name
Test status
Simulation time 88816982 ps
CPU time 0.84 seconds
Started Dec 20 12:23:18 PM PST 23
Finished Dec 20 12:23:46 PM PST 23
Peak memory 199672 kb
Host smart-b37435bf-36b1-435f-9b6a-8499ae360bd1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687282137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.2687282137
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.3633017301
Short name T222
Test name
Test status
Simulation time 98620785 ps
CPU time 1.1 seconds
Started Dec 20 12:23:11 PM PST 23
Finished Dec 20 12:23:37 PM PST 23
Peak memory 199664 kb
Host smart-f3fe0c71-7936-4aae-b8b9-4d6bf48a15c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633017301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.3633017301
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.1523679324
Short name T69
Test name
Test status
Simulation time 207208874 ps
CPU time 2.79 seconds
Started Dec 20 12:23:37 PM PST 23
Finished Dec 20 12:24:18 PM PST 23
Peak memory 199744 kb
Host smart-4cf04a58-d9d9-4fcb-abe9-6c547709909b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523679324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.1523679324
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.2175744612
Short name T183
Test name
Test status
Simulation time 201401588 ps
CPU time 1.32 seconds
Started Dec 20 12:23:35 PM PST 23
Finished Dec 20 12:24:13 PM PST 23
Peak memory 199752 kb
Host smart-7da123f8-c0f6-43c0-9f08-32a3479d68b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175744612 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.2175744612
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.1419010407
Short name T202
Test name
Test status
Simulation time 62565261 ps
CPU time 0.77 seconds
Started Dec 20 12:23:30 PM PST 23
Finished Dec 20 12:24:08 PM PST 23
Peak memory 199672 kb
Host smart-be0968d2-21d8-43a9-b849-abbf3a64e95d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419010407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.1419010407
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.1116845963
Short name T237
Test name
Test status
Simulation time 226160357 ps
CPU time 1.42 seconds
Started Dec 20 12:23:36 PM PST 23
Finished Dec 20 12:24:16 PM PST 23
Peak memory 199736 kb
Host smart-849c06f9-c24c-4eed-819a-7c9b10f6f602
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116845963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.1116845963
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.2878542202
Short name T225
Test name
Test status
Simulation time 621542315 ps
CPU time 3.68 seconds
Started Dec 20 12:23:52 PM PST 23
Finished Dec 20 12:24:40 PM PST 23
Peak memory 199656 kb
Host smart-711e368e-485c-4a03-ace4-83a90fd4d31a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878542202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.2878542202
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.556974767
Short name T131
Test name
Test status
Simulation time 909045780 ps
CPU time 2.91 seconds
Started Dec 20 12:23:29 PM PST 23
Finished Dec 20 12:24:09 PM PST 23
Peak memory 199872 kb
Host smart-25f5bbfb-f892-4038-83a3-7a59df4323cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556974767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_err
.556974767
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.3131935670
Short name T214
Test name
Test status
Simulation time 101902164 ps
CPU time 0.85 seconds
Started Dec 20 12:23:24 PM PST 23
Finished Dec 20 12:23:58 PM PST 23
Peak memory 199788 kb
Host smart-57fc2ef7-7abf-425c-a5a1-6d9ebbb88cb7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131935670 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.3131935670
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.2061963748
Short name T179
Test name
Test status
Simulation time 72580646 ps
CPU time 0.79 seconds
Started Dec 20 12:23:26 PM PST 23
Finished Dec 20 12:24:03 PM PST 23
Peak memory 199616 kb
Host smart-abf63105-6b20-47a7-8f7c-05cba48179ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061963748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.2061963748
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2839138369
Short name T223
Test name
Test status
Simulation time 220573488 ps
CPU time 1.41 seconds
Started Dec 20 12:23:27 PM PST 23
Finished Dec 20 12:24:05 PM PST 23
Peak memory 199716 kb
Host smart-aa1d5868-b7ca-4591-b9b1-bfc4885a3151
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839138369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.2839138369
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.4099187409
Short name T192
Test name
Test status
Simulation time 799834757 ps
CPU time 2.94 seconds
Started Dec 20 12:23:39 PM PST 23
Finished Dec 20 12:24:20 PM PST 23
Peak memory 199756 kb
Host smart-7d825ac0-d7a9-42d3-bed7-c20f408dfe06
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099187409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.4099187409
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.1469899205
Short name T233
Test name
Test status
Simulation time 120910829 ps
CPU time 1.01 seconds
Started Dec 20 12:24:03 PM PST 23
Finished Dec 20 12:24:43 PM PST 23
Peak memory 199760 kb
Host smart-769fa151-2673-446e-97b9-072399d8d5d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469899205 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.1469899205
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.2774494984
Short name T199
Test name
Test status
Simulation time 65072976 ps
CPU time 0.72 seconds
Started Dec 20 12:23:16 PM PST 23
Finished Dec 20 12:23:43 PM PST 23
Peak memory 199576 kb
Host smart-c49c4ff5-34f6-49b1-852f-edaaae811e03
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774494984 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.2774494984
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.1047838430
Short name T206
Test name
Test status
Simulation time 140074596 ps
CPU time 1.06 seconds
Started Dec 20 12:23:38 PM PST 23
Finished Dec 20 12:24:17 PM PST 23
Peak memory 199716 kb
Host smart-9827666c-6580-4667-9483-489c9e1a4459
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047838430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.1047838430
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.3737737797
Short name T236
Test name
Test status
Simulation time 214156992 ps
CPU time 2.93 seconds
Started Dec 20 12:23:33 PM PST 23
Finished Dec 20 12:24:13 PM PST 23
Peak memory 208000 kb
Host smart-c2e1af16-915b-4ac2-b910-da9fd49d8510
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737737797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.3737737797
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3409573386
Short name T220
Test name
Test status
Simulation time 484653898 ps
CPU time 1.8 seconds
Started Dec 20 12:23:39 PM PST 23
Finished Dec 20 12:24:19 PM PST 23
Peak memory 199756 kb
Host smart-1ce17853-e0bc-48e6-b524-bf019f2d4b97
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409573386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.3409573386
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.621886896
Short name T197
Test name
Test status
Simulation time 205663642 ps
CPU time 1.27 seconds
Started Dec 20 12:23:28 PM PST 23
Finished Dec 20 12:24:06 PM PST 23
Peak memory 199700 kb
Host smart-e201ea25-89b0-4d74-9398-db68eb487f5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621886896 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.621886896
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.2400952086
Short name T109
Test name
Test status
Simulation time 66491560 ps
CPU time 0.77 seconds
Started Dec 20 12:23:36 PM PST 23
Finished Dec 20 12:24:14 PM PST 23
Peak memory 199644 kb
Host smart-406f444f-356f-4d65-b4b3-c9976f21b262
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400952086 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.2400952086
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.220279216
Short name T114
Test name
Test status
Simulation time 200617133 ps
CPU time 1.33 seconds
Started Dec 20 12:23:34 PM PST 23
Finished Dec 20 12:24:12 PM PST 23
Peak memory 199752 kb
Host smart-835513e9-e3f9-43f9-91e0-101a096414c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220279216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_sa
me_csr_outstanding.220279216
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.4202057036
Short name T187
Test name
Test status
Simulation time 196690527 ps
CPU time 2.5 seconds
Started Dec 20 12:23:23 PM PST 23
Finished Dec 20 12:23:59 PM PST 23
Peak memory 208052 kb
Host smart-23bf1d23-6f56-4c26-a83d-50961a3e7736
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202057036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.4202057036
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.2520984122
Short name T207
Test name
Test status
Simulation time 435285609 ps
CPU time 1.82 seconds
Started Dec 20 12:23:31 PM PST 23
Finished Dec 20 12:24:10 PM PST 23
Peak memory 199772 kb
Host smart-316b7e1e-28f1-485c-8c72-2d7ac6cae1bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520984122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.2520984122
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.1729193386
Short name T124
Test name
Test status
Simulation time 180818718 ps
CPU time 1.25 seconds
Started Dec 20 12:24:09 PM PST 23
Finished Dec 20 12:24:48 PM PST 23
Peak memory 199760 kb
Host smart-8bc0a750-f119-4197-abee-51a3d002c9a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729193386 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.1729193386
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.2870192773
Short name T217
Test name
Test status
Simulation time 78913957 ps
CPU time 0.72 seconds
Started Dec 20 12:23:30 PM PST 23
Finished Dec 20 12:24:08 PM PST 23
Peak memory 199596 kb
Host smart-128a7c59-2f8a-4d0e-ad49-2dd3f4e30a65
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870192773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.2870192773
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.571224936
Short name T107
Test name
Test status
Simulation time 139828666 ps
CPU time 1.08 seconds
Started Dec 20 12:23:48 PM PST 23
Finished Dec 20 12:24:30 PM PST 23
Peak memory 199624 kb
Host smart-597088a1-b168-4807-a82b-7476399c6aef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571224936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_sa
me_csr_outstanding.571224936
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.1549357433
Short name T191
Test name
Test status
Simulation time 198827513 ps
CPU time 2.79 seconds
Started Dec 20 12:23:35 PM PST 23
Finished Dec 20 12:24:14 PM PST 23
Peak memory 199788 kb
Host smart-81bb1c91-a209-4267-a949-2910292c4171
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549357433 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.1549357433
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.932853900
Short name T198
Test name
Test status
Simulation time 435320621 ps
CPU time 1.85 seconds
Started Dec 20 12:23:33 PM PST 23
Finished Dec 20 12:24:11 PM PST 23
Peak memory 199752 kb
Host smart-d24ac188-46b1-4d39-a449-791300b96dae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932853900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_err
.932853900
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3491563044
Short name T242
Test name
Test status
Simulation time 108201809 ps
CPU time 0.94 seconds
Started Dec 20 12:23:38 PM PST 23
Finished Dec 20 12:24:17 PM PST 23
Peak memory 199736 kb
Host smart-0630127d-2279-45b4-b1a1-fa116332a8ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491563044 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.3491563044
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.897562830
Short name T105
Test name
Test status
Simulation time 83289581 ps
CPU time 0.81 seconds
Started Dec 20 12:23:22 PM PST 23
Finished Dec 20 12:23:56 PM PST 23
Peak memory 199612 kb
Host smart-fb4051b4-3d1e-46d8-9b03-1cee3301b7c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897562830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.897562830
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.1920686410
Short name T216
Test name
Test status
Simulation time 120565112 ps
CPU time 1.16 seconds
Started Dec 20 12:24:10 PM PST 23
Finished Dec 20 12:24:48 PM PST 23
Peak memory 199768 kb
Host smart-cff57a93-8169-40e7-86b7-5b8b7e9ab2ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920686410 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.1920686410
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.2372502070
Short name T205
Test name
Test status
Simulation time 323815074 ps
CPU time 2.05 seconds
Started Dec 20 12:23:37 PM PST 23
Finished Dec 20 12:24:17 PM PST 23
Peak memory 199676 kb
Host smart-80de63f5-a905-4ced-a2d0-bfe4d7efec80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372502070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.2372502070
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.4102070954
Short name T117
Test name
Test status
Simulation time 943169810 ps
CPU time 3.13 seconds
Started Dec 20 12:23:39 PM PST 23
Finished Dec 20 12:24:19 PM PST 23
Peak memory 199828 kb
Host smart-ae904c6f-7b38-4ee5-a1af-cd6a05fdb153
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102070954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.4102070954
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.3217128799
Short name T196
Test name
Test status
Simulation time 122278745 ps
CPU time 1.01 seconds
Started Dec 20 12:23:32 PM PST 23
Finished Dec 20 12:24:10 PM PST 23
Peak memory 199752 kb
Host smart-d0844ede-adbd-4eb6-be4e-25a7af754f8d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217128799 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.3217128799
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2542583664
Short name T184
Test name
Test status
Simulation time 62074401 ps
CPU time 0.77 seconds
Started Dec 20 12:23:45 PM PST 23
Finished Dec 20 12:24:25 PM PST 23
Peak memory 199544 kb
Host smart-deb5f3be-1dac-4903-bd61-e45836d8baf0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542583664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.2542583664
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.1348525916
Short name T204
Test name
Test status
Simulation time 141289198 ps
CPU time 0.98 seconds
Started Dec 20 12:23:20 PM PST 23
Finished Dec 20 12:23:51 PM PST 23
Peak memory 199628 kb
Host smart-fd236359-3272-46d3-9145-a83085073d02
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348525916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.1348525916
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.616151459
Short name T244
Test name
Test status
Simulation time 114330066 ps
CPU time 1.68 seconds
Started Dec 20 12:23:37 PM PST 23
Finished Dec 20 12:24:17 PM PST 23
Peak memory 199720 kb
Host smart-459652a2-c386-47f4-81ad-4b259e0e2c8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616151459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.616151459
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.427335308
Short name T240
Test name
Test status
Simulation time 160536543 ps
CPU time 1.95 seconds
Started Dec 20 12:23:38 PM PST 23
Finished Dec 20 12:24:24 PM PST 23
Peak memory 199808 kb
Host smart-e8e5595f-8849-4884-ade9-ba435b3cfd20
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427335308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.427335308
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.1809764164
Short name T180
Test name
Test status
Simulation time 491211261 ps
CPU time 5.31 seconds
Started Dec 20 12:23:53 PM PST 23
Finished Dec 20 12:24:39 PM PST 23
Peak memory 199740 kb
Host smart-8f10d9d2-461f-491b-8da2-dfcab302ac5e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809764164 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.1
809764164
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.3211276444
Short name T111
Test name
Test status
Simulation time 95203781 ps
CPU time 0.76 seconds
Started Dec 20 12:23:29 PM PST 23
Finished Dec 20 12:24:07 PM PST 23
Peak memory 199596 kb
Host smart-4eee5874-18f2-41d7-82a5-7de36025b7e6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211276444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.3
211276444
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.610987774
Short name T227
Test name
Test status
Simulation time 77734843 ps
CPU time 0.83 seconds
Started Dec 20 12:23:27 PM PST 23
Finished Dec 20 12:24:05 PM PST 23
Peak memory 199636 kb
Host smart-d0e7d8dd-5e5b-40d9-8b76-62b292a9a587
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610987774 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.610987774
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.3882709863
Short name T185
Test name
Test status
Simulation time 85536787 ps
CPU time 0.93 seconds
Started Dec 20 12:24:07 PM PST 23
Finished Dec 20 12:24:45 PM PST 23
Peak memory 199740 kb
Host smart-13fedaec-6d38-4be2-bb80-35018f993542
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882709863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.3882709863
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.4107750190
Short name T245
Test name
Test status
Simulation time 211787589 ps
CPU time 1.73 seconds
Started Dec 20 12:23:35 PM PST 23
Finished Dec 20 12:24:13 PM PST 23
Peak memory 199648 kb
Host smart-0d8f8e4e-a873-4f8b-aaf5-9ccd32037f8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107750190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.4107750190
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3431632266
Short name T95
Test name
Test status
Simulation time 507119939 ps
CPU time 2.1 seconds
Started Dec 20 12:23:41 PM PST 23
Finished Dec 20 12:24:24 PM PST 23
Peak memory 199796 kb
Host smart-8bd795a0-363b-4a6c-897b-2a09f6db9c88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431632266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.3431632266
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.1167106619
Short name T193
Test name
Test status
Simulation time 352081598 ps
CPU time 2.43 seconds
Started Dec 20 12:23:32 PM PST 23
Finished Dec 20 12:24:11 PM PST 23
Peak memory 199688 kb
Host smart-bbe87562-3f73-4ffe-8adb-0430e4dd843b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167106619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.1
167106619
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.3487476074
Short name T189
Test name
Test status
Simulation time 792367412 ps
CPU time 4.38 seconds
Started Dec 20 12:25:06 PM PST 23
Finished Dec 20 12:25:31 PM PST 23
Peak memory 197792 kb
Host smart-bebffe01-107a-47a6-9cd4-bed42d0fd78f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487476074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.3
487476074
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.900302517
Short name T177
Test name
Test status
Simulation time 92314210 ps
CPU time 0.78 seconds
Started Dec 20 12:23:32 PM PST 23
Finished Dec 20 12:24:09 PM PST 23
Peak memory 199596 kb
Host smart-52e43a91-bb2d-4b5a-9b4f-334686e053f7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900302517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.900302517
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.1478035036
Short name T218
Test name
Test status
Simulation time 182791524 ps
CPU time 1.18 seconds
Started Dec 20 12:23:29 PM PST 23
Finished Dec 20 12:24:08 PM PST 23
Peak memory 199584 kb
Host smart-d73cdde1-5379-42d0-b369-337bbd4dcddb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478035036 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.1478035036
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.1177680419
Short name T229
Test name
Test status
Simulation time 64992721 ps
CPU time 0.71 seconds
Started Dec 20 12:25:22 PM PST 23
Finished Dec 20 12:25:47 PM PST 23
Peak memory 199092 kb
Host smart-3722c4bc-2e3d-4ff6-867b-6463a58a86df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177680419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.1177680419
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.334739922
Short name T98
Test name
Test status
Simulation time 265872486 ps
CPU time 1.52 seconds
Started Dec 20 12:23:28 PM PST 23
Finished Dec 20 12:24:07 PM PST 23
Peak memory 199776 kb
Host smart-0e0b5ab8-ed01-4291-a661-1183db68bee9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334739922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sam
e_csr_outstanding.334739922
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.1973478277
Short name T230
Test name
Test status
Simulation time 324069570 ps
CPU time 1.98 seconds
Started Dec 20 12:23:35 PM PST 23
Finished Dec 20 12:24:13 PM PST 23
Peak memory 199808 kb
Host smart-fe7355cd-1f4e-43d9-8b27-aa7dbd4f840b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973478277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.1973478277
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.3466530332
Short name T175
Test name
Test status
Simulation time 161654720 ps
CPU time 2.01 seconds
Started Dec 20 12:23:23 PM PST 23
Finished Dec 20 12:23:58 PM PST 23
Peak memory 199528 kb
Host smart-6f6317ab-0d46-457c-a361-b7b3741d30be
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466530332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.3
466530332
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.2446650793
Short name T182
Test name
Test status
Simulation time 2290963542 ps
CPU time 9.32 seconds
Started Dec 20 12:23:28 PM PST 23
Finished Dec 20 12:24:15 PM PST 23
Peak memory 199848 kb
Host smart-576fda6c-8cad-4720-bce7-6a7fd3fd41ae
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446650793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.2
446650793
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.758168439
Short name T188
Test name
Test status
Simulation time 127275526 ps
CPU time 0.87 seconds
Started Dec 20 12:23:35 PM PST 23
Finished Dec 20 12:24:12 PM PST 23
Peak memory 199448 kb
Host smart-732224c4-2000-4ec4-a618-b09e96bcdfc9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758168439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.758168439
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.3219295408
Short name T248
Test name
Test status
Simulation time 104278804 ps
CPU time 0.89 seconds
Started Dec 20 12:23:23 PM PST 23
Finished Dec 20 12:23:57 PM PST 23
Peak memory 199584 kb
Host smart-4c0ee6b0-565c-470b-b958-ea6e5c989737
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219295408 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.3219295408
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.2242309188
Short name T176
Test name
Test status
Simulation time 85276846 ps
CPU time 0.85 seconds
Started Dec 20 12:23:26 PM PST 23
Finished Dec 20 12:24:02 PM PST 23
Peak memory 199608 kb
Host smart-27f78ccc-468f-4634-a7c6-bfe6b6dbd213
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242309188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.2242309188
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.2280887244
Short name T239
Test name
Test status
Simulation time 116412964 ps
CPU time 0.94 seconds
Started Dec 20 12:23:25 PM PST 23
Finished Dec 20 12:24:02 PM PST 23
Peak memory 199620 kb
Host smart-2386955d-1459-4860-b99a-48d1ff4dbd65
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280887244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.2280887244
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.427063970
Short name T201
Test name
Test status
Simulation time 108565639 ps
CPU time 1.47 seconds
Started Dec 20 12:23:35 PM PST 23
Finished Dec 20 12:24:13 PM PST 23
Peak memory 199792 kb
Host smart-a1250277-13f0-45d7-ba24-5c0c8ec53825
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427063970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.427063970
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.3417988334
Short name T100
Test name
Test status
Simulation time 430415509 ps
CPU time 1.76 seconds
Started Dec 20 12:23:36 PM PST 23
Finished Dec 20 12:24:16 PM PST 23
Peak memory 199740 kb
Host smart-16d6f2f4-c3d3-4976-9004-0e5f24b5c646
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417988334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.3417988334
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.3148546418
Short name T66
Test name
Test status
Simulation time 120202703 ps
CPU time 0.97 seconds
Started Dec 20 12:23:20 PM PST 23
Finished Dec 20 12:23:50 PM PST 23
Peak memory 199640 kb
Host smart-ed02663b-8601-4308-be5f-69792fab8f66
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148546418 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.3148546418
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.4018911902
Short name T212
Test name
Test status
Simulation time 62373073 ps
CPU time 0.71 seconds
Started Dec 20 12:23:56 PM PST 23
Finished Dec 20 12:24:37 PM PST 23
Peak memory 199576 kb
Host smart-ff3db97d-0a6e-4e39-a0af-79178a37a965
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018911902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.4018911902
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.1382930254
Short name T108
Test name
Test status
Simulation time 91692125 ps
CPU time 1.14 seconds
Started Dec 20 12:23:35 PM PST 23
Finished Dec 20 12:24:13 PM PST 23
Peak memory 199748 kb
Host smart-17a19d97-c8dd-4540-906b-45be9c4d147b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382930254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.1382930254
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.2504455328
Short name T210
Test name
Test status
Simulation time 492124841 ps
CPU time 3.07 seconds
Started Dec 20 12:23:23 PM PST 23
Finished Dec 20 12:23:58 PM PST 23
Peak memory 199820 kb
Host smart-e4e2fc52-a43b-45b9-a0b4-7820bac35b13
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504455328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.2504455328
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.2273751730
Short name T115
Test name
Test status
Simulation time 797156743 ps
CPU time 2.65 seconds
Started Dec 20 12:23:36 PM PST 23
Finished Dec 20 12:24:17 PM PST 23
Peak memory 199788 kb
Host smart-10f382b6-6f58-4ec4-b424-d84fe23592d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273751730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.2273751730
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.3549001111
Short name T231
Test name
Test status
Simulation time 178861587 ps
CPU time 1.19 seconds
Started Dec 20 12:23:21 PM PST 23
Finished Dec 20 12:23:52 PM PST 23
Peak memory 199736 kb
Host smart-19d1a09c-4405-4ad9-93d9-9ccaf44e91d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549001111 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.3549001111
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.3627337748
Short name T235
Test name
Test status
Simulation time 77155506 ps
CPU time 0.81 seconds
Started Dec 20 12:23:25 PM PST 23
Finished Dec 20 12:24:01 PM PST 23
Peak memory 199644 kb
Host smart-d9eb7891-9ba3-4f6a-bfd7-4e5eef93a2ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627337748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.3627337748
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.549231027
Short name T110
Test name
Test status
Simulation time 82404834 ps
CPU time 0.93 seconds
Started Dec 20 12:25:38 PM PST 23
Finished Dec 20 12:26:08 PM PST 23
Peak memory 199380 kb
Host smart-72faba6b-9f14-4f1d-94fa-a6a5fb7c5f06
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549231027 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sam
e_csr_outstanding.549231027
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.4191389090
Short name T94
Test name
Test status
Simulation time 523067669 ps
CPU time 3.6 seconds
Started Dec 20 12:23:33 PM PST 23
Finished Dec 20 12:24:14 PM PST 23
Peak memory 199772 kb
Host smart-67986815-e580-400c-8f31-45b8a4bd924e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191389090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.4191389090
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.3895256720
Short name T181
Test name
Test status
Simulation time 204872921 ps
CPU time 1.36 seconds
Started Dec 20 12:23:29 PM PST 23
Finished Dec 20 12:24:07 PM PST 23
Peak memory 199832 kb
Host smart-20b63440-4097-45e1-bea6-1400fec9e361
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895256720 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.3895256720
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.1457502173
Short name T174
Test name
Test status
Simulation time 91572381 ps
CPU time 0.8 seconds
Started Dec 20 12:24:00 PM PST 23
Finished Dec 20 12:24:41 PM PST 23
Peak memory 199632 kb
Host smart-c27aef74-4b5f-44cb-813c-c56f30c63a41
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457502173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.1457502173
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3397350391
Short name T208
Test name
Test status
Simulation time 104665241 ps
CPU time 1.14 seconds
Started Dec 20 12:24:18 PM PST 23
Finished Dec 20 12:24:58 PM PST 23
Peak memory 199688 kb
Host smart-d64fdb85-95ff-4a98-8504-cd5a684c2eef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397350391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.3397350391
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.3044967326
Short name T232
Test name
Test status
Simulation time 167946280 ps
CPU time 2.33 seconds
Started Dec 20 12:23:31 PM PST 23
Finished Dec 20 12:24:10 PM PST 23
Peak memory 199760 kb
Host smart-cb2ed302-b7fd-4241-9fba-880bd2868ab6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044967326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.3044967326
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.1693425876
Short name T118
Test name
Test status
Simulation time 412157676 ps
CPU time 1.88 seconds
Started Dec 20 12:25:42 PM PST 23
Finished Dec 20 12:26:12 PM PST 23
Peak memory 199468 kb
Host smart-61449f2f-9085-451b-bf84-fea51ba39825
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693425876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.1693425876
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1541535016
Short name T178
Test name
Test status
Simulation time 110987877 ps
CPU time 0.92 seconds
Started Dec 20 12:23:35 PM PST 23
Finished Dec 20 12:24:12 PM PST 23
Peak memory 199668 kb
Host smart-b8906ed2-c071-4156-b007-afccd269cc4f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541535016 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.1541535016
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.3593817830
Short name T113
Test name
Test status
Simulation time 65784541 ps
CPU time 0.74 seconds
Started Dec 20 12:24:03 PM PST 23
Finished Dec 20 12:24:43 PM PST 23
Peak memory 199528 kb
Host smart-1ddc91f8-b44f-4752-9ca7-927ed8884e5d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593817830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.3593817830
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.623208918
Short name T97
Test name
Test status
Simulation time 180907728 ps
CPU time 1.2 seconds
Started Dec 20 12:23:28 PM PST 23
Finished Dec 20 12:24:06 PM PST 23
Peak memory 199768 kb
Host smart-802ced98-2cc4-452c-a58f-c2cecbf16f49
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623208918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sam
e_csr_outstanding.623208918
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.1709818890
Short name T123
Test name
Test status
Simulation time 202737023 ps
CPU time 2.58 seconds
Started Dec 20 12:23:30 PM PST 23
Finished Dec 20 12:24:11 PM PST 23
Peak memory 208000 kb
Host smart-a3174b61-dd13-4baf-8d4d-e7c3e0c20f0e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709818890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.1709818890
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.2105509609
Short name T121
Test name
Test status
Simulation time 486817649 ps
CPU time 1.88 seconds
Started Dec 20 12:23:26 PM PST 23
Finished Dec 20 12:24:03 PM PST 23
Peak memory 199752 kb
Host smart-1385c1f3-8cfd-4a1a-8eb3-c32d15ab986c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105509609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.2105509609
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2258814631
Short name T92
Test name
Test status
Simulation time 124241199 ps
CPU time 0.99 seconds
Started Dec 20 12:23:36 PM PST 23
Finished Dec 20 12:24:13 PM PST 23
Peak memory 199760 kb
Host smart-aa3c58ef-ea57-4f8d-a62f-0f08749603bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258814631 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.2258814631
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.702594512
Short name T234
Test name
Test status
Simulation time 70403816 ps
CPU time 0.78 seconds
Started Dec 20 12:24:03 PM PST 23
Finished Dec 20 12:24:43 PM PST 23
Peak memory 199628 kb
Host smart-b69abb8e-696a-427f-a0b0-f9f06593d969
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702594512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.702594512
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.945069075
Short name T112
Test name
Test status
Simulation time 229989206 ps
CPU time 1.4 seconds
Started Dec 20 12:24:00 PM PST 23
Finished Dec 20 12:24:41 PM PST 23
Peak memory 199696 kb
Host smart-31e003ea-052f-4bf2-9902-fe7892c40e5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945069075 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sam
e_csr_outstanding.945069075
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.2547293019
Short name T119
Test name
Test status
Simulation time 855503156 ps
CPU time 2.74 seconds
Started Dec 20 12:23:23 PM PST 23
Finished Dec 20 12:23:59 PM PST 23
Peak memory 199768 kb
Host smart-a558ac9a-34d1-4ab1-893e-88875603dcb3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547293019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.2547293019
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.2759561765
Short name T249
Test name
Test status
Simulation time 87860078 ps
CPU time 0.8 seconds
Started Dec 20 12:40:57 PM PST 23
Finished Dec 20 12:42:04 PM PST 23
Peak memory 199224 kb
Host smart-c8286951-7ea5-4411-8127-0b0778b9bce7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759561765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.2759561765
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.952635239
Short name T41
Test name
Test status
Simulation time 1230866499 ps
CPU time 5.71 seconds
Started Dec 20 12:40:36 PM PST 23
Finished Dec 20 12:41:45 PM PST 23
Peak memory 220588 kb
Host smart-70fd61fd-d616-425e-8a80-6e49cd2fe718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952635239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.952635239
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.3233515673
Short name T357
Test name
Test status
Simulation time 243986321 ps
CPU time 1.08 seconds
Started Dec 20 12:40:57 PM PST 23
Finished Dec 20 12:42:03 PM PST 23
Peak memory 216504 kb
Host smart-a96e1bc3-cfe7-461b-83c7-bdac7facfb3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233515673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.3233515673
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_reset.3279211423
Short name T499
Test name
Test status
Simulation time 1645508928 ps
CPU time 6.7 seconds
Started Dec 20 12:40:58 PM PST 23
Finished Dec 20 12:42:09 PM PST 23
Peak memory 199588 kb
Host smart-37397ece-00c8-4a46-94ed-3b8e1473a93d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279211423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.3279211423
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.3594894224
Short name T522
Test name
Test status
Simulation time 175368439 ps
CPU time 1.18 seconds
Started Dec 20 12:40:51 PM PST 23
Finished Dec 20 12:41:56 PM PST 23
Peak memory 199492 kb
Host smart-780ec47b-1563-412b-b20c-0ac142a53c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594894224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.3594894224
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.659861802
Short name T559
Test name
Test status
Simulation time 203708171 ps
CPU time 1.46 seconds
Started Dec 20 12:40:20 PM PST 23
Finished Dec 20 12:41:22 PM PST 23
Peak memory 199560 kb
Host smart-8f4bea09-049d-4459-86d6-5ddfde7ec788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659861802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.659861802
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.1886089232
Short name T6
Test name
Test status
Simulation time 2434422957 ps
CPU time 7.77 seconds
Started Dec 20 12:41:33 PM PST 23
Finished Dec 20 12:42:44 PM PST 23
Peak memory 197660 kb
Host smart-1e116f97-924d-45df-8688-1bd9fe7a3bd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886089232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.1886089232
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.3339930165
Short name T561
Test name
Test status
Simulation time 341364740 ps
CPU time 1.93 seconds
Started Dec 20 12:40:35 PM PST 23
Finished Dec 20 12:41:42 PM PST 23
Peak memory 199444 kb
Host smart-f16515c9-31a0-4b80-b246-4d053d6f5309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339930165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.3339930165
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.1892562648
Short name T549
Test name
Test status
Simulation time 229401103 ps
CPU time 1.29 seconds
Started Dec 20 12:40:46 PM PST 23
Finished Dec 20 12:41:51 PM PST 23
Peak memory 199484 kb
Host smart-941e1d57-fbf6-421e-b27e-68c28315c723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892562648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.1892562648
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.2414709737
Short name T525
Test name
Test status
Simulation time 55896565 ps
CPU time 0.69 seconds
Started Dec 20 12:40:57 PM PST 23
Finished Dec 20 12:42:03 PM PST 23
Peak memory 199272 kb
Host smart-63bbfe3e-0b7b-477b-a5ce-f98c74cf2dd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414709737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.2414709737
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.3705244320
Short name T474
Test name
Test status
Simulation time 1232537945 ps
CPU time 5.01 seconds
Started Dec 20 12:41:33 PM PST 23
Finished Dec 20 12:42:42 PM PST 23
Peak memory 213984 kb
Host smart-b17c8cc1-ced9-4c33-ac59-8589bfa9bf57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705244320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.3705244320
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.1389002632
Short name T360
Test name
Test status
Simulation time 244538252 ps
CPU time 1 seconds
Started Dec 20 12:41:34 PM PST 23
Finished Dec 20 12:42:38 PM PST 23
Peak memory 216096 kb
Host smart-90143325-66cc-46e9-8ae9-c3154139dfa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389002632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.1389002632
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.1943262340
Short name T589
Test name
Test status
Simulation time 191650056 ps
CPU time 0.87 seconds
Started Dec 20 12:41:00 PM PST 23
Finished Dec 20 12:42:04 PM PST 23
Peak memory 199256 kb
Host smart-89fc4a0c-9906-4b8b-ab2e-644617f7de78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943262340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.1943262340
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.3067320149
Short name T370
Test name
Test status
Simulation time 2088376231 ps
CPU time 8.62 seconds
Started Dec 20 12:40:47 PM PST 23
Finished Dec 20 12:41:59 PM PST 23
Peak memory 199560 kb
Host smart-9c6946dc-e8d2-488e-b192-15af671e9a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067320149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.3067320149
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.680857122
Short name T77
Test name
Test status
Simulation time 8543104173 ps
CPU time 12.33 seconds
Started Dec 20 12:41:33 PM PST 23
Finished Dec 20 12:42:49 PM PST 23
Peak memory 214244 kb
Host smart-0c10ea17-6840-41c9-bcca-d6cb7f94671d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680857122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.680857122
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.1461700285
Short name T551
Test name
Test status
Simulation time 174790038 ps
CPU time 1.1 seconds
Started Dec 20 12:41:13 PM PST 23
Finished Dec 20 12:42:17 PM PST 23
Peak memory 199460 kb
Host smart-f0621045-83c6-4400-9b1b-8f9b4b12ac63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461700285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.1461700285
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.3448508458
Short name T151
Test name
Test status
Simulation time 115817720 ps
CPU time 1.24 seconds
Started Dec 20 12:41:33 PM PST 23
Finished Dec 20 12:42:38 PM PST 23
Peak memory 197116 kb
Host smart-6a4a2c46-de70-4e8c-94b1-54ce62dc940d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448508458 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.3448508458
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.2081112961
Short name T528
Test name
Test status
Simulation time 13772397138 ps
CPU time 42.04 seconds
Started Dec 20 12:41:01 PM PST 23
Finished Dec 20 12:42:47 PM PST 23
Peak memory 199584 kb
Host smart-3db98a1f-1efc-40e5-980a-c0a2044d792e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081112961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.2081112961
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.990441805
Short name T510
Test name
Test status
Simulation time 365829173 ps
CPU time 2.34 seconds
Started Dec 20 12:41:33 PM PST 23
Finished Dec 20 12:42:39 PM PST 23
Peak memory 196756 kb
Host smart-1242a319-14a2-4410-914a-a3e678889b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990441805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.990441805
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.2686301422
Short name T257
Test name
Test status
Simulation time 113494209 ps
CPU time 0.99 seconds
Started Dec 20 12:41:33 PM PST 23
Finished Dec 20 12:42:37 PM PST 23
Peak memory 197276 kb
Host smart-ba49889d-b99c-40ec-a48e-7415c7f74ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686301422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.2686301422
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.3476572224
Short name T50
Test name
Test status
Simulation time 1232287276 ps
CPU time 5.18 seconds
Started Dec 20 12:41:00 PM PST 23
Finished Dec 20 12:42:09 PM PST 23
Peak memory 216776 kb
Host smart-ab2c8068-e9e2-4e7b-8ac8-21002b3667e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476572224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.3476572224
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.476408532
Short name T325
Test name
Test status
Simulation time 244703560 ps
CPU time 1 seconds
Started Dec 20 12:40:34 PM PST 23
Finished Dec 20 12:41:38 PM PST 23
Peak memory 216364 kb
Host smart-5ea2e210-bdd4-4cdf-a7f2-89ee5d1b72d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476408532 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.476408532
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.1857507772
Short name T506
Test name
Test status
Simulation time 137362194 ps
CPU time 0.77 seconds
Started Dec 20 12:40:42 PM PST 23
Finished Dec 20 12:41:46 PM PST 23
Peak memory 199312 kb
Host smart-b764af11-9aef-490c-8856-20889baaa5d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857507772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.1857507772
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.3646304785
Short name T609
Test name
Test status
Simulation time 792408887 ps
CPU time 4.09 seconds
Started Dec 20 12:40:45 PM PST 23
Finished Dec 20 12:41:53 PM PST 23
Peak memory 199604 kb
Host smart-64bf35fc-03de-482f-a6cd-c8c66cd532dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646304785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.3646304785
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.2930975284
Short name T423
Test name
Test status
Simulation time 151780961 ps
CPU time 1.08 seconds
Started Dec 20 12:43:23 PM PST 23
Finished Dec 20 12:43:30 PM PST 23
Peak memory 198884 kb
Host smart-b3b33274-df8b-4e9d-b26c-e848f984aaf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930975284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.2930975284
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.636589624
Short name T268
Test name
Test status
Simulation time 261373048 ps
CPU time 1.54 seconds
Started Dec 20 12:43:23 PM PST 23
Finished Dec 20 12:43:31 PM PST 23
Peak memory 198624 kb
Host smart-3144c7a9-02ff-4751-9d7d-dce4f4f46952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636589624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.636589624
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.578442761
Short name T479
Test name
Test status
Simulation time 8889062730 ps
CPU time 35.68 seconds
Started Dec 20 12:40:43 PM PST 23
Finished Dec 20 12:42:22 PM PST 23
Peak memory 199684 kb
Host smart-2b78f72a-b8bc-4a8d-bffb-dde020f7612b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578442761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.578442761
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.3349168593
Short name T255
Test name
Test status
Simulation time 344871002 ps
CPU time 2.14 seconds
Started Dec 20 12:40:42 PM PST 23
Finished Dec 20 12:41:46 PM PST 23
Peak memory 199372 kb
Host smart-f8d85f87-8d99-4fe3-bf29-6bfa122ab4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349168593 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.3349168593
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.486963334
Short name T461
Test name
Test status
Simulation time 285490511 ps
CPU time 1.45 seconds
Started Dec 20 12:41:00 PM PST 23
Finished Dec 20 12:42:06 PM PST 23
Peak memory 199576 kb
Host smart-a4649c5a-65f0-4914-b5ac-267c968f527c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486963334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.486963334
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.2869529991
Short name T252
Test name
Test status
Simulation time 76866130 ps
CPU time 0.76 seconds
Started Dec 20 12:41:00 PM PST 23
Finished Dec 20 12:42:05 PM PST 23
Peak memory 199360 kb
Host smart-f2982047-76ab-402a-87bf-3d2e7d1822a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869529991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.2869529991
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.2355409510
Short name T531
Test name
Test status
Simulation time 2395847351 ps
CPU time 7.89 seconds
Started Dec 20 12:40:48 PM PST 23
Finished Dec 20 12:41:59 PM PST 23
Peak memory 221476 kb
Host smart-4dd03e82-564e-42cb-b458-e8e4042e6a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355409510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.2355409510
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.2379597408
Short name T394
Test name
Test status
Simulation time 243872392 ps
CPU time 1.16 seconds
Started Dec 20 12:43:21 PM PST 23
Finished Dec 20 12:43:30 PM PST 23
Peak memory 216128 kb
Host smart-c9053eb0-2c14-4a7c-9538-577e00931970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379597408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.2379597408
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.225121888
Short name T259
Test name
Test status
Simulation time 91906818 ps
CPU time 0.7 seconds
Started Dec 20 12:40:43 PM PST 23
Finished Dec 20 12:41:47 PM PST 23
Peak memory 199208 kb
Host smart-23a1feaa-3d8a-4be2-8e90-e4076db1ad6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225121888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.225121888
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.412593848
Short name T441
Test name
Test status
Simulation time 777915235 ps
CPU time 3.71 seconds
Started Dec 20 12:40:47 PM PST 23
Finished Dec 20 12:41:55 PM PST 23
Peak memory 199520 kb
Host smart-9bd43f65-0e35-48e4-82bc-d64fefe15aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412593848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.412593848
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.3946571719
Short name T562
Test name
Test status
Simulation time 114608649 ps
CPU time 0.96 seconds
Started Dec 20 12:40:55 PM PST 23
Finished Dec 20 12:42:01 PM PST 23
Peak memory 199404 kb
Host smart-0f1f916f-fb03-4c01-9002-8ad0b2aaa814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946571719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.3946571719
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.570693096
Short name T264
Test name
Test status
Simulation time 186613477 ps
CPU time 1.35 seconds
Started Dec 20 12:40:38 PM PST 23
Finished Dec 20 12:41:42 PM PST 23
Peak memory 199620 kb
Host smart-0a7851fb-7641-4480-a416-6098057239e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570693096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.570693096
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.3501661154
Short name T417
Test name
Test status
Simulation time 830459927 ps
CPU time 3.83 seconds
Started Dec 20 12:43:22 PM PST 23
Finished Dec 20 12:43:33 PM PST 23
Peak memory 199036 kb
Host smart-4cefd9b9-88ba-4900-94d0-c5f234541c91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501661154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.3501661154
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.1795143299
Short name T524
Test name
Test status
Simulation time 84356957 ps
CPU time 0.79 seconds
Started Dec 20 12:40:48 PM PST 23
Finished Dec 20 12:41:53 PM PST 23
Peak memory 199168 kb
Host smart-de5229eb-4ba5-437e-b442-56b3f51c3c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795143299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.1795143299
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.2768572307
Short name T553
Test name
Test status
Simulation time 72913043 ps
CPU time 0.72 seconds
Started Dec 20 12:41:03 PM PST 23
Finished Dec 20 12:42:07 PM PST 23
Peak memory 199252 kb
Host smart-3e07be3f-4784-42f4-accd-1b64321e2da6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768572307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.2768572307
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.2003016611
Short name T481
Test name
Test status
Simulation time 244787460 ps
CPU time 1 seconds
Started Dec 20 12:40:47 PM PST 23
Finished Dec 20 12:41:53 PM PST 23
Peak memory 216444 kb
Host smart-83321160-2b85-46d0-8385-3aa4ec3bcc05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003016611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.2003016611
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.1768763886
Short name T437
Test name
Test status
Simulation time 189855851 ps
CPU time 0.86 seconds
Started Dec 20 12:40:45 PM PST 23
Finished Dec 20 12:41:49 PM PST 23
Peak memory 199000 kb
Host smart-e65cb4ea-c1b8-45e4-85eb-8d507d545159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768763886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.1768763886
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.1636102501
Short name T618
Test name
Test status
Simulation time 1835620075 ps
CPU time 6.62 seconds
Started Dec 20 12:40:48 PM PST 23
Finished Dec 20 12:41:59 PM PST 23
Peak memory 199604 kb
Host smart-bbc7e4dc-bd89-4c0e-83a7-8e1de58b841c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636102501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.1636102501
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.2341446372
Short name T508
Test name
Test status
Simulation time 255869717 ps
CPU time 1.43 seconds
Started Dec 20 12:40:56 PM PST 23
Finished Dec 20 12:42:02 PM PST 23
Peak memory 199588 kb
Host smart-76c80bc1-5279-4638-bfd3-0d4376264df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341446372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.2341446372
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.2387519872
Short name T456
Test name
Test status
Simulation time 5968040649 ps
CPU time 21.61 seconds
Started Dec 20 12:43:15 PM PST 23
Finished Dec 20 12:43:50 PM PST 23
Peak memory 198340 kb
Host smart-b4b96541-f363-4df2-985e-d81773df3bc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387519872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.2387519872
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.2101987158
Short name T460
Test name
Test status
Simulation time 544952753 ps
CPU time 2.85 seconds
Started Dec 20 12:41:10 PM PST 23
Finished Dec 20 12:42:16 PM PST 23
Peak memory 199200 kb
Host smart-0576169e-77df-4105-884b-f118d1207d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101987158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.2101987158
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.3050324776
Short name T455
Test name
Test status
Simulation time 154994548 ps
CPU time 1.01 seconds
Started Dec 20 12:43:14 PM PST 23
Finished Dec 20 12:43:29 PM PST 23
Peak memory 198784 kb
Host smart-1388c23a-cf12-47ba-bb0a-c3b7e7335b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050324776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.3050324776
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.2695240596
Short name T380
Test name
Test status
Simulation time 65614353 ps
CPU time 0.74 seconds
Started Dec 20 12:40:51 PM PST 23
Finished Dec 20 12:41:56 PM PST 23
Peak memory 199328 kb
Host smart-413f858f-d06d-4482-9781-99212c45240a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695240596 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.2695240596
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.2110833103
Short name T36
Test name
Test status
Simulation time 1889967536 ps
CPU time 6.69 seconds
Started Dec 20 12:40:55 PM PST 23
Finished Dec 20 12:42:06 PM PST 23
Peak memory 228744 kb
Host smart-e3e606ba-8a18-499d-9100-6c90f327b93a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110833103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.2110833103
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.3386938612
Short name T415
Test name
Test status
Simulation time 244825770 ps
CPU time 0.98 seconds
Started Dec 20 12:40:49 PM PST 23
Finished Dec 20 12:41:54 PM PST 23
Peak memory 216732 kb
Host smart-40c61399-1106-4a14-b809-f3be0699d44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386938612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.3386938612
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.2494399024
Short name T16
Test name
Test status
Simulation time 92659450 ps
CPU time 0.72 seconds
Started Dec 20 12:40:54 PM PST 23
Finished Dec 20 12:41:59 PM PST 23
Peak memory 199280 kb
Host smart-f1ade265-da4d-4e9f-affd-8e4a51db8a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494399024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.2494399024
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.2120875773
Short name T313
Test name
Test status
Simulation time 2092086165 ps
CPU time 6.98 seconds
Started Dec 20 12:41:09 PM PST 23
Finished Dec 20 12:42:19 PM PST 23
Peak memory 199528 kb
Host smart-06fa0be4-fa96-4809-80cc-60f678a4f473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120875773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.2120875773
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.2347396763
Short name T134
Test name
Test status
Simulation time 107080114 ps
CPU time 0.94 seconds
Started Dec 20 12:43:14 PM PST 23
Finished Dec 20 12:43:29 PM PST 23
Peak memory 198892 kb
Host smart-c6a305cc-f635-4753-b3b9-3f116f625e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347396763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.2347396763
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.4148188503
Short name T592
Test name
Test status
Simulation time 241956930 ps
CPU time 1.58 seconds
Started Dec 20 12:42:58 PM PST 23
Finished Dec 20 12:43:28 PM PST 23
Peak memory 198408 kb
Host smart-c1d8c9de-f9c2-46f5-ac1e-1ba31e4ca2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148188503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.4148188503
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.431688466
Short name T585
Test name
Test status
Simulation time 322125182 ps
CPU time 1.81 seconds
Started Dec 20 12:40:50 PM PST 23
Finished Dec 20 12:41:56 PM PST 23
Peak memory 199600 kb
Host smart-2b78fd93-7e7d-48ff-8fcb-5e7e677a4e4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431688466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.431688466
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.2879691365
Short name T342
Test name
Test status
Simulation time 399495474 ps
CPU time 2.2 seconds
Started Dec 20 12:40:53 PM PST 23
Finished Dec 20 12:41:59 PM PST 23
Peak memory 199384 kb
Host smart-3ce08d85-81f3-4143-b87a-f7aa6064b237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879691365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.2879691365
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.3724853598
Short name T586
Test name
Test status
Simulation time 165652037 ps
CPU time 1.13 seconds
Started Dec 20 12:40:52 PM PST 23
Finished Dec 20 12:41:58 PM PST 23
Peak memory 199472 kb
Host smart-0669effd-022a-4ea8-aa86-6d289e612939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724853598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.3724853598
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.4233449104
Short name T428
Test name
Test status
Simulation time 82367094 ps
CPU time 0.75 seconds
Started Dec 20 12:40:52 PM PST 23
Finished Dec 20 12:41:56 PM PST 23
Peak memory 199048 kb
Host smart-24df53dc-8e64-47be-b1d5-314d0de5fae5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233449104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.4233449104
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.227243068
Short name T33
Test name
Test status
Simulation time 2175501020 ps
CPU time 8.13 seconds
Started Dec 20 12:41:04 PM PST 23
Finished Dec 20 12:42:15 PM PST 23
Peak memory 221200 kb
Host smart-3958dc86-f996-400c-8b96-079424229f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227243068 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.227243068
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.2935242731
Short name T363
Test name
Test status
Simulation time 244357117 ps
CPU time 1 seconds
Started Dec 20 12:40:50 PM PST 23
Finished Dec 20 12:41:55 PM PST 23
Peak memory 216528 kb
Host smart-9e4aff3f-ec6e-46fc-a954-1c630c0caf35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935242731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.2935242731
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.3512508471
Short name T269
Test name
Test status
Simulation time 181022505 ps
CPU time 0.83 seconds
Started Dec 20 12:40:56 PM PST 23
Finished Dec 20 12:42:02 PM PST 23
Peak memory 199236 kb
Host smart-3711c5b3-a67c-4872-b855-91d0c9db8358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512508471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.3512508471
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.182260907
Short name T576
Test name
Test status
Simulation time 719823526 ps
CPU time 3.74 seconds
Started Dec 20 12:40:54 PM PST 23
Finished Dec 20 12:42:02 PM PST 23
Peak memory 199624 kb
Host smart-48be2037-970e-4a0a-967c-6b7dc95db0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182260907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.182260907
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.1261452662
Short name T135
Test name
Test status
Simulation time 141791628 ps
CPU time 1.01 seconds
Started Dec 20 12:41:04 PM PST 23
Finished Dec 20 12:42:08 PM PST 23
Peak memory 199456 kb
Host smart-de0f04a3-aca1-43ff-aa1b-e216c64de278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261452662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.1261452662
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.2424110230
Short name T574
Test name
Test status
Simulation time 124949575 ps
CPU time 1.09 seconds
Started Dec 20 12:40:54 PM PST 23
Finished Dec 20 12:42:00 PM PST 23
Peak memory 199624 kb
Host smart-611d0a3c-e020-42dd-9908-052097136b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424110230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.2424110230
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.3177940311
Short name T335
Test name
Test status
Simulation time 6536124723 ps
CPU time 27.3 seconds
Started Dec 20 12:40:51 PM PST 23
Finished Dec 20 12:42:22 PM PST 23
Peak memory 199700 kb
Host smart-71ffbedc-e1dc-4e2f-8382-d9a10dc2fcb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177940311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.3177940311
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.1275787293
Short name T389
Test name
Test status
Simulation time 127872505 ps
CPU time 1.54 seconds
Started Dec 20 12:40:59 PM PST 23
Finished Dec 20 12:42:05 PM PST 23
Peak memory 199356 kb
Host smart-96998dc3-5cca-4ec1-8464-0f074fc83bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275787293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.1275787293
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.3053430891
Short name T606
Test name
Test status
Simulation time 184789545 ps
CPU time 1.14 seconds
Started Dec 20 12:40:51 PM PST 23
Finished Dec 20 12:41:56 PM PST 23
Peak memory 199404 kb
Host smart-e6641aba-a8bb-433d-8e97-1857c7c6c24d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053430891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.3053430891
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.3950727253
Short name T158
Test name
Test status
Simulation time 94691799 ps
CPU time 0.81 seconds
Started Dec 20 12:41:06 PM PST 23
Finished Dec 20 12:42:11 PM PST 23
Peak memory 199212 kb
Host smart-3ca9344f-16b7-44d2-8618-21995386fb52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950727253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.3950727253
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.294942084
Short name T486
Test name
Test status
Simulation time 1234076739 ps
CPU time 5.29 seconds
Started Dec 20 12:41:05 PM PST 23
Finished Dec 20 12:42:15 PM PST 23
Peak memory 216676 kb
Host smart-e05c23e0-20c4-4edb-9d26-b07ebf1e911c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294942084 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.294942084
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.316993090
Short name T281
Test name
Test status
Simulation time 206078140 ps
CPU time 0.89 seconds
Started Dec 20 12:43:15 PM PST 23
Finished Dec 20 12:43:29 PM PST 23
Peak memory 198696 kb
Host smart-33f2307d-d340-4ba0-94b1-d4b30104df07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316993090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.316993090
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.146095528
Short name T287
Test name
Test status
Simulation time 1194574471 ps
CPU time 5.15 seconds
Started Dec 20 12:43:15 PM PST 23
Finished Dec 20 12:43:34 PM PST 23
Peak memory 199116 kb
Host smart-3b2db459-c397-4972-8db1-b6520fdf5329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146095528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.146095528
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.1736206070
Short name T322
Test name
Test status
Simulation time 142530239 ps
CPU time 1.02 seconds
Started Dec 20 12:40:46 PM PST 23
Finished Dec 20 12:41:51 PM PST 23
Peak memory 199476 kb
Host smart-790c4d11-5521-4d84-a8ca-5e757bbe6e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736206070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.1736206070
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.2200015289
Short name T79
Test name
Test status
Simulation time 197109128 ps
CPU time 1.28 seconds
Started Dec 20 12:40:56 PM PST 23
Finished Dec 20 12:42:02 PM PST 23
Peak memory 199352 kb
Host smart-134f683c-f7af-47c5-80b7-21bd1fb441b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200015289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.2200015289
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.3090477199
Short name T328
Test name
Test status
Simulation time 2228053893 ps
CPU time 9.74 seconds
Started Dec 20 12:40:47 PM PST 23
Finished Dec 20 12:42:00 PM PST 23
Peak memory 199616 kb
Host smart-822b07cd-7db3-4d83-9f3e-5284a1613c70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090477199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.3090477199
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.190166958
Short name T436
Test name
Test status
Simulation time 156287209 ps
CPU time 1.88 seconds
Started Dec 20 12:40:45 PM PST 23
Finished Dec 20 12:41:50 PM PST 23
Peak memory 199336 kb
Host smart-364626ea-f981-4448-8283-df0677a82403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190166958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.190166958
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.1407392096
Short name T425
Test name
Test status
Simulation time 270282533 ps
CPU time 1.43 seconds
Started Dec 20 12:40:50 PM PST 23
Finished Dec 20 12:41:55 PM PST 23
Peak memory 199460 kb
Host smart-21bdfe6f-323e-4f63-9ab5-0ee5506816a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407392096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.1407392096
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.4007030461
Short name T517
Test name
Test status
Simulation time 59371287 ps
CPU time 0.7 seconds
Started Dec 20 12:43:15 PM PST 23
Finished Dec 20 12:43:29 PM PST 23
Peak memory 197940 kb
Host smart-03e65b27-e37a-447d-b6d1-6d72cf7f2620
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007030461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.4007030461
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.2750240364
Short name T52
Test name
Test status
Simulation time 2356095450 ps
CPU time 9.31 seconds
Started Dec 20 12:40:44 PM PST 23
Finished Dec 20 12:41:56 PM PST 23
Peak memory 217060 kb
Host smart-66637dd1-71e5-45de-b5d7-621b6e589a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750240364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.2750240364
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.1559543472
Short name T160
Test name
Test status
Simulation time 244112358 ps
CPU time 1.03 seconds
Started Dec 20 12:40:45 PM PST 23
Finished Dec 20 12:41:49 PM PST 23
Peak memory 216524 kb
Host smart-43ec6f3c-1d60-4c66-b85c-2eb91831af62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559543472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.1559543472
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.655455586
Short name T602
Test name
Test status
Simulation time 83858243 ps
CPU time 0.72 seconds
Started Dec 20 12:40:34 PM PST 23
Finished Dec 20 12:41:36 PM PST 23
Peak memory 199196 kb
Host smart-c51578ce-9aa6-4487-ae11-5c52b8d1bcf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655455586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.655455586
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.3185306797
Short name T485
Test name
Test status
Simulation time 1570373284 ps
CPU time 6.13 seconds
Started Dec 20 12:41:06 PM PST 23
Finished Dec 20 12:42:16 PM PST 23
Peak memory 199556 kb
Host smart-44fc1d5f-8cb9-4a0e-89bf-836cb670e4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185306797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.3185306797
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.410970645
Short name T501
Test name
Test status
Simulation time 145909304 ps
CPU time 1.06 seconds
Started Dec 20 12:43:23 PM PST 23
Finished Dec 20 12:43:30 PM PST 23
Peak memory 198936 kb
Host smart-a04d41c9-5f7b-40e4-90c0-184ac11b9786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410970645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.410970645
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.134059799
Short name T89
Test name
Test status
Simulation time 197689827 ps
CPU time 1.31 seconds
Started Dec 20 12:40:37 PM PST 23
Finished Dec 20 12:41:41 PM PST 23
Peak memory 199604 kb
Host smart-d768a758-6518-461d-9cc7-290ee8ca6e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134059799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.134059799
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.2939990501
Short name T457
Test name
Test status
Simulation time 4783067832 ps
CPU time 16.4 seconds
Started Dec 20 12:40:43 PM PST 23
Finished Dec 20 12:42:02 PM PST 23
Peak memory 199740 kb
Host smart-5a595526-bd38-4763-ae89-e6eb71d92737
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939990501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.2939990501
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.3087284312
Short name T537
Test name
Test status
Simulation time 283569349 ps
CPU time 1.9 seconds
Started Dec 20 12:43:14 PM PST 23
Finished Dec 20 12:43:30 PM PST 23
Peak memory 198772 kb
Host smart-d0d33d08-eb93-4e81-a659-f3b38ddc98d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087284312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.3087284312
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.1978427417
Short name T344
Test name
Test status
Simulation time 246565241 ps
CPU time 1.36 seconds
Started Dec 20 12:40:56 PM PST 23
Finished Dec 20 12:42:02 PM PST 23
Peak memory 199588 kb
Host smart-085b9f8f-fda0-42e5-8f2b-64382ede975d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978427417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.1978427417
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.2122649136
Short name T288
Test name
Test status
Simulation time 67022577 ps
CPU time 0.75 seconds
Started Dec 20 12:41:12 PM PST 23
Finished Dec 20 12:42:19 PM PST 23
Peak memory 199232 kb
Host smart-86fe5d79-67c3-4633-8957-3ee08a580f2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122649136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.2122649136
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.2072857443
Short name T60
Test name
Test status
Simulation time 2180842323 ps
CPU time 8.25 seconds
Started Dec 20 12:41:11 PM PST 23
Finished Dec 20 12:42:22 PM PST 23
Peak memory 217000 kb
Host smart-0b4d071c-efd2-4372-94fe-8c0e49d7cd54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072857443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.2072857443
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.1048408772
Short name T81
Test name
Test status
Simulation time 244531567 ps
CPU time 1.16 seconds
Started Dec 20 12:41:02 PM PST 23
Finished Dec 20 12:42:07 PM PST 23
Peak memory 216624 kb
Host smart-7c2b6601-ddf5-4702-801e-2c1744d4962e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048408772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.1048408772
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.4041847755
Short name T336
Test name
Test status
Simulation time 113365187 ps
CPU time 0.8 seconds
Started Dec 20 12:40:46 PM PST 23
Finished Dec 20 12:41:51 PM PST 23
Peak memory 199236 kb
Host smart-4ef8798a-a192-4e54-b5c1-e55ebec806de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041847755 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.4041847755
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.1337446448
Short name T573
Test name
Test status
Simulation time 759447648 ps
CPU time 3.83 seconds
Started Dec 20 12:41:10 PM PST 23
Finished Dec 20 12:42:19 PM PST 23
Peak memory 199372 kb
Host smart-d4dbef99-c8c7-46c8-a494-4f2abc370965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337446448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.1337446448
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.2864713122
Short name T619
Test name
Test status
Simulation time 156985729 ps
CPU time 1.09 seconds
Started Dec 20 12:41:02 PM PST 23
Finished Dec 20 12:42:07 PM PST 23
Peak memory 199556 kb
Host smart-2689724f-871a-40b1-a194-29de9ab2d3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864713122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.2864713122
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.4181328355
Short name T494
Test name
Test status
Simulation time 203106866 ps
CPU time 1.29 seconds
Started Dec 20 12:40:43 PM PST 23
Finished Dec 20 12:41:47 PM PST 23
Peak memory 199272 kb
Host smart-8f85ea69-d5ed-41fb-b4ad-ef94d2d785be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181328355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.4181328355
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.3846435250
Short name T530
Test name
Test status
Simulation time 1551498140 ps
CPU time 7.19 seconds
Started Dec 20 12:41:13 PM PST 23
Finished Dec 20 12:42:24 PM PST 23
Peak memory 199584 kb
Host smart-2836f7d5-ad4a-466a-accf-c2acc7ed666e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846435250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.3846435250
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.665334544
Short name T620
Test name
Test status
Simulation time 292457918 ps
CPU time 1.81 seconds
Started Dec 20 12:41:10 PM PST 23
Finished Dec 20 12:42:17 PM PST 23
Peak memory 199480 kb
Host smart-88417cae-4682-4faa-8edb-217d411cfbaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665334544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.665334544
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.1024246403
Short name T316
Test name
Test status
Simulation time 224404716 ps
CPU time 1.28 seconds
Started Dec 20 12:40:59 PM PST 23
Finished Dec 20 12:42:05 PM PST 23
Peak memory 199368 kb
Host smart-83692ca1-e7fe-4ade-9efc-e0f7b38bb578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024246403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.1024246403
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.3844005478
Short name T379
Test name
Test status
Simulation time 59815962 ps
CPU time 0.7 seconds
Started Dec 20 12:41:00 PM PST 23
Finished Dec 20 12:42:04 PM PST 23
Peak memory 199308 kb
Host smart-1761a3df-541c-4282-8df7-6d66c2a5cf3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844005478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.3844005478
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.1653551710
Short name T84
Test name
Test status
Simulation time 243987012 ps
CPU time 1.02 seconds
Started Dec 20 12:41:12 PM PST 23
Finished Dec 20 12:42:16 PM PST 23
Peak memory 216656 kb
Host smart-565ff14b-4a88-4249-982f-89cc720b0c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653551710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.1653551710
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.403617438
Short name T15
Test name
Test status
Simulation time 167328481 ps
CPU time 0.81 seconds
Started Dec 20 12:41:12 PM PST 23
Finished Dec 20 12:42:15 PM PST 23
Peak memory 199232 kb
Host smart-7ddc2608-afbc-4246-a1f1-cb8890f009d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403617438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.403617438
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.3172573185
Short name T350
Test name
Test status
Simulation time 1550547724 ps
CPU time 6.52 seconds
Started Dec 20 12:41:14 PM PST 23
Finished Dec 20 12:42:24 PM PST 23
Peak memory 199400 kb
Host smart-0deb82ff-c53a-4785-b59c-06372f127b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172573185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.3172573185
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.313792030
Short name T468
Test name
Test status
Simulation time 169082867 ps
CPU time 1.08 seconds
Started Dec 20 12:41:16 PM PST 23
Finished Dec 20 12:42:21 PM PST 23
Peak memory 199172 kb
Host smart-9d2e7ed3-0975-4523-8e2a-a4b0c7d9d668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313792030 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.313792030
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.101467423
Short name T529
Test name
Test status
Simulation time 256997026 ps
CPU time 1.4 seconds
Started Dec 20 12:41:14 PM PST 23
Finished Dec 20 12:42:18 PM PST 23
Peak memory 199584 kb
Host smart-ac3b78d3-962c-418c-8b55-96183cc900e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101467423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.101467423
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.2354632903
Short name T418
Test name
Test status
Simulation time 13167056658 ps
CPU time 42.06 seconds
Started Dec 20 12:41:11 PM PST 23
Finished Dec 20 12:42:56 PM PST 23
Peak memory 199704 kb
Host smart-3b927d8b-885b-4ed4-afc8-a0bb40ac5d07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354632903 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.2354632903
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.3645822835
Short name T503
Test name
Test status
Simulation time 369452882 ps
CPU time 2.33 seconds
Started Dec 20 12:41:14 PM PST 23
Finished Dec 20 12:42:20 PM PST 23
Peak memory 199472 kb
Host smart-2506b571-e011-4243-a465-d27093144bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645822835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.3645822835
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.2522973743
Short name T294
Test name
Test status
Simulation time 61404462 ps
CPU time 0.74 seconds
Started Dec 20 12:41:07 PM PST 23
Finished Dec 20 12:42:14 PM PST 23
Peak memory 199456 kb
Host smart-5deffc52-5eb6-427b-a10a-b38550bc71d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522973743 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.2522973743
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.2720904896
Short name T372
Test name
Test status
Simulation time 91905199 ps
CPU time 0.82 seconds
Started Dec 20 12:41:13 PM PST 23
Finished Dec 20 12:42:17 PM PST 23
Peak memory 199200 kb
Host smart-52c7b4dd-c633-4e47-b359-d7292cb1b805
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720904896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.2720904896
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.4044183577
Short name T34
Test name
Test status
Simulation time 2348339575 ps
CPU time 8.18 seconds
Started Dec 20 12:41:15 PM PST 23
Finished Dec 20 12:42:27 PM PST 23
Peak memory 217456 kb
Host smart-1af6a74c-f32b-491b-a790-e4fc1ee2427e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044183577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.4044183577
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.600635984
Short name T329
Test name
Test status
Simulation time 244912675 ps
CPU time 1.01 seconds
Started Dec 20 12:41:11 PM PST 23
Finished Dec 20 12:42:15 PM PST 23
Peak memory 216692 kb
Host smart-0f572c59-92fa-4115-9454-117bf074ad5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600635984 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.600635984
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.156737546
Short name T307
Test name
Test status
Simulation time 213949670 ps
CPU time 0.88 seconds
Started Dec 20 12:41:14 PM PST 23
Finished Dec 20 12:42:19 PM PST 23
Peak memory 199288 kb
Host smart-b2e5a217-441a-4d60-94b0-7999e5640140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156737546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.156737546
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.2669573061
Short name T138
Test name
Test status
Simulation time 155613505 ps
CPU time 1.1 seconds
Started Dec 20 12:41:04 PM PST 23
Finished Dec 20 12:42:08 PM PST 23
Peak memory 199424 kb
Host smart-768aa56c-6d14-4a48-a31b-7ed6dfbceb22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669573061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.2669573061
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.3415003605
Short name T153
Test name
Test status
Simulation time 109995214 ps
CPU time 1.06 seconds
Started Dec 20 12:41:18 PM PST 23
Finished Dec 20 12:42:24 PM PST 23
Peak memory 199308 kb
Host smart-219cd5e8-0827-4675-aa04-a89c088fb413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415003605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.3415003605
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.811146981
Short name T315
Test name
Test status
Simulation time 148193573 ps
CPU time 1.72 seconds
Started Dec 20 12:41:15 PM PST 23
Finished Dec 20 12:42:20 PM PST 23
Peak memory 199460 kb
Host smart-bc61999b-3435-4cd1-b413-e229e3bcde70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811146981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.811146981
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.1959568906
Short name T431
Test name
Test status
Simulation time 198941903 ps
CPU time 1.27 seconds
Started Dec 20 12:41:01 PM PST 23
Finished Dec 20 12:42:06 PM PST 23
Peak memory 199436 kb
Host smart-6eb68ba2-d228-4d85-a1f3-3eb332c91981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959568906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.1959568906
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.1944686707
Short name T159
Test name
Test status
Simulation time 77360829 ps
CPU time 0.73 seconds
Started Dec 20 12:40:44 PM PST 23
Finished Dec 20 12:41:47 PM PST 23
Peak memory 199240 kb
Host smart-9c0ffd9d-d3d0-4cd6-9302-b06d754a6198
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944686707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.1944686707
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.2410939090
Short name T490
Test name
Test status
Simulation time 2369542550 ps
CPU time 7.38 seconds
Started Dec 20 12:42:02 PM PST 23
Finished Dec 20 12:43:10 PM PST 23
Peak memory 216856 kb
Host smart-0c50da5f-3be0-4ede-acf9-3b4c7f88017d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410939090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.2410939090
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.1051133634
Short name T28
Test name
Test status
Simulation time 244447556 ps
CPU time 1.12 seconds
Started Dec 20 12:40:23 PM PST 23
Finished Dec 20 12:41:25 PM PST 23
Peak memory 216676 kb
Host smart-e8a32d18-5e16-4c52-b1a9-e1633fc3b8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051133634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.1051133634
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.2421877618
Short name T330
Test name
Test status
Simulation time 186778713 ps
CPU time 0.84 seconds
Started Dec 20 12:40:23 PM PST 23
Finished Dec 20 12:41:24 PM PST 23
Peak memory 199248 kb
Host smart-d8a16270-0c8f-48a2-a107-9ddbec5729e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421877618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.2421877618
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.791386154
Short name T477
Test name
Test status
Simulation time 1288085677 ps
CPU time 4.83 seconds
Started Dec 20 12:42:01 PM PST 23
Finished Dec 20 12:43:07 PM PST 23
Peak memory 199076 kb
Host smart-1c7e0c42-9557-432e-ab6b-13ccdb6ff2c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791386154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.791386154
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.2428596341
Short name T72
Test name
Test status
Simulation time 8546971049 ps
CPU time 13.21 seconds
Started Dec 20 12:40:47 PM PST 23
Finished Dec 20 12:42:04 PM PST 23
Peak memory 216372 kb
Host smart-88bbfbb0-893d-4307-8c89-a687f18cea69
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428596341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.2428596341
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.4187075923
Short name T260
Test name
Test status
Simulation time 104823639 ps
CPU time 0.93 seconds
Started Dec 20 12:41:34 PM PST 23
Finished Dec 20 12:42:40 PM PST 23
Peak memory 198940 kb
Host smart-511e87a8-e346-4b0f-b640-bad99a4bb614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187075923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.4187075923
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.3561686312
Short name T406
Test name
Test status
Simulation time 201572019 ps
CPU time 1.37 seconds
Started Dec 20 12:41:48 PM PST 23
Finished Dec 20 12:42:52 PM PST 23
Peak memory 197828 kb
Host smart-4c1003b0-5343-4c7e-b2ee-986313360f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561686312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.3561686312
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.4182182601
Short name T440
Test name
Test status
Simulation time 7017328456 ps
CPU time 24.01 seconds
Started Dec 20 12:40:57 PM PST 23
Finished Dec 20 12:42:26 PM PST 23
Peak memory 199672 kb
Host smart-95b8af5f-d675-446b-80c4-285b2e6ad4a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182182601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.4182182601
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.1726094698
Short name T302
Test name
Test status
Simulation time 319165919 ps
CPU time 2.06 seconds
Started Dec 20 12:41:07 PM PST 23
Finished Dec 20 12:42:15 PM PST 23
Peak memory 199460 kb
Host smart-597b7466-edb6-40fb-954f-39f342385262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726094698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.1726094698
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.1187598478
Short name T557
Test name
Test status
Simulation time 148116276 ps
CPU time 1.04 seconds
Started Dec 20 12:41:34 PM PST 23
Finished Dec 20 12:42:40 PM PST 23
Peak memory 198936 kb
Host smart-dd887cfa-8a46-4c58-b5ab-65f81c7ce7df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187598478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.1187598478
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.3215671474
Short name T295
Test name
Test status
Simulation time 94027045 ps
CPU time 0.87 seconds
Started Dec 20 12:41:00 PM PST 23
Finished Dec 20 12:42:05 PM PST 23
Peak memory 198980 kb
Host smart-615bcc02-2a73-46ee-8435-b1732e03502b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215671474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.3215671474
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.1249771787
Short name T35
Test name
Test status
Simulation time 1227786417 ps
CPU time 5.37 seconds
Started Dec 20 12:41:04 PM PST 23
Finished Dec 20 12:42:12 PM PST 23
Peak memory 217460 kb
Host smart-1b0fd2ed-785c-48ac-a198-c0929b2a06a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249771787 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.1249771787
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.344697130
Short name T346
Test name
Test status
Simulation time 245076705 ps
CPU time 1.11 seconds
Started Dec 20 12:41:04 PM PST 23
Finished Dec 20 12:42:08 PM PST 23
Peak memory 216724 kb
Host smart-c084d490-26d9-4c48-81c4-0be271988864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344697130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.344697130
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.3292603017
Short name T414
Test name
Test status
Simulation time 163065921 ps
CPU time 0.88 seconds
Started Dec 20 12:42:58 PM PST 23
Finished Dec 20 12:43:27 PM PST 23
Peak memory 197940 kb
Host smart-b9e7a8b5-4b57-41a4-a7e2-815c4e6a62ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292603017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.3292603017
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.1413712356
Short name T348
Test name
Test status
Simulation time 1517135691 ps
CPU time 5.37 seconds
Started Dec 20 12:41:12 PM PST 23
Finished Dec 20 12:42:23 PM PST 23
Peak memory 199356 kb
Host smart-eea16ae8-9d20-4ca8-8ed9-1a91d58419cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413712356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.1413712356
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.2401360231
Short name T429
Test name
Test status
Simulation time 97861433 ps
CPU time 0.93 seconds
Started Dec 20 12:41:05 PM PST 23
Finished Dec 20 12:42:10 PM PST 23
Peak memory 199396 kb
Host smart-d98b368f-a660-4aee-b9bc-5723ea3d7769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401360231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.2401360231
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.2676414797
Short name T572
Test name
Test status
Simulation time 115989054 ps
CPU time 1.07 seconds
Started Dec 20 12:41:09 PM PST 23
Finished Dec 20 12:42:13 PM PST 23
Peak memory 199556 kb
Host smart-7b602c97-7714-4d3a-9f6a-464915e6703e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676414797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.2676414797
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.1506471493
Short name T444
Test name
Test status
Simulation time 3860601400 ps
CPU time 16.32 seconds
Started Dec 20 12:41:03 PM PST 23
Finished Dec 20 12:42:23 PM PST 23
Peak memory 199572 kb
Host smart-4d2b2587-5fc5-42cb-948d-2aee7b8fbdff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506471493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.1506471493
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.1880204049
Short name T526
Test name
Test status
Simulation time 333493304 ps
CPU time 2.02 seconds
Started Dec 20 12:41:06 PM PST 23
Finished Dec 20 12:42:11 PM PST 23
Peak memory 199112 kb
Host smart-04fad677-6526-42df-ad82-ecf5aa9325a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880204049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.1880204049
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.183312906
Short name T564
Test name
Test status
Simulation time 66854701 ps
CPU time 0.76 seconds
Started Dec 20 12:41:01 PM PST 23
Finished Dec 20 12:42:06 PM PST 23
Peak memory 199488 kb
Host smart-0b7d7459-5f85-4b8d-b541-05efe8b2761f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183312906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.183312906
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.3898031304
Short name T164
Test name
Test status
Simulation time 74398705 ps
CPU time 0.73 seconds
Started Dec 20 12:41:14 PM PST 23
Finished Dec 20 12:42:18 PM PST 23
Peak memory 199252 kb
Host smart-64b676f1-9811-4f8e-87d1-cfef57b3ecb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898031304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.3898031304
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.1477579329
Short name T488
Test name
Test status
Simulation time 2345425214 ps
CPU time 7.41 seconds
Started Dec 20 12:41:03 PM PST 23
Finished Dec 20 12:42:14 PM PST 23
Peak memory 221028 kb
Host smart-89b39c96-0b42-4696-921d-de92a6694cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477579329 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.1477579329
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.1126823608
Short name T533
Test name
Test status
Simulation time 243574005 ps
CPU time 1.09 seconds
Started Dec 20 12:41:09 PM PST 23
Finished Dec 20 12:42:13 PM PST 23
Peak memory 216616 kb
Host smart-8aeb4058-bf52-4a21-8aea-f51d998852f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126823608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.1126823608
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.1029287245
Short name T546
Test name
Test status
Simulation time 209375441 ps
CPU time 0.86 seconds
Started Dec 20 12:43:38 PM PST 23
Finished Dec 20 12:43:40 PM PST 23
Peak memory 199004 kb
Host smart-8e255281-2300-4bb5-a745-d9f36d115052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029287245 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.1029287245
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.4157978679
Short name T251
Test name
Test status
Simulation time 1599970161 ps
CPU time 5.57 seconds
Started Dec 20 12:41:03 PM PST 23
Finished Dec 20 12:42:12 PM PST 23
Peak memory 198500 kb
Host smart-365e7e90-85b0-487c-90fb-41a2a0a1b6af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157978679 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.4157978679
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.2194136836
Short name T523
Test name
Test status
Simulation time 101329146 ps
CPU time 0.96 seconds
Started Dec 20 12:41:10 PM PST 23
Finished Dec 20 12:42:14 PM PST 23
Peak memory 199480 kb
Host smart-5352ab2a-1477-4a40-81b5-612dbf7ccf6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194136836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.2194136836
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.2530320238
Short name T9
Test name
Test status
Simulation time 192357526 ps
CPU time 1.28 seconds
Started Dec 20 12:43:14 PM PST 23
Finished Dec 20 12:43:30 PM PST 23
Peak memory 199068 kb
Host smart-ab031f3d-83c9-4940-aa2f-8a1989c20f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530320238 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.2530320238
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.2815855289
Short name T13
Test name
Test status
Simulation time 8455049126 ps
CPU time 28.02 seconds
Started Dec 20 12:41:08 PM PST 23
Finished Dec 20 12:42:39 PM PST 23
Peak memory 199692 kb
Host smart-5095f52d-0c63-4a5f-9009-a59b20e4d061
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815855289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.2815855289
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.4039877543
Short name T515
Test name
Test status
Simulation time 121830144 ps
CPU time 1.36 seconds
Started Dec 20 12:41:12 PM PST 23
Finished Dec 20 12:42:17 PM PST 23
Peak memory 199164 kb
Host smart-4e3d91d1-c432-476e-90c8-71aa53c56cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039877543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.4039877543
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.36874341
Short name T511
Test name
Test status
Simulation time 66857746 ps
CPU time 0.7 seconds
Started Dec 20 12:41:21 PM PST 23
Finished Dec 20 12:42:27 PM PST 23
Peak memory 199304 kb
Host smart-fa2efc6d-8aae-4aa2-882f-ef0e2b646ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36874341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.36874341
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.4169547861
Short name T157
Test name
Test status
Simulation time 67321175 ps
CPU time 0.75 seconds
Started Dec 20 12:41:13 PM PST 23
Finished Dec 20 12:42:17 PM PST 23
Peak memory 199268 kb
Host smart-d6ae66e4-6bf9-46f2-ad7c-6180d14bba67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169547861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.4169547861
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.3185749973
Short name T37
Test name
Test status
Simulation time 2352677932 ps
CPU time 8.09 seconds
Started Dec 20 12:41:10 PM PST 23
Finished Dec 20 12:42:21 PM PST 23
Peak memory 218208 kb
Host smart-29477fcb-a188-4198-ac6e-1ced33024095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185749973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.3185749973
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.4076563414
Short name T292
Test name
Test status
Simulation time 249823469 ps
CPU time 1.04 seconds
Started Dec 20 12:41:22 PM PST 23
Finished Dec 20 12:42:28 PM PST 23
Peak memory 216660 kb
Host smart-546ecfd6-4f5a-4695-9be2-abc95014fdc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076563414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.4076563414
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.3292451097
Short name T565
Test name
Test status
Simulation time 189359324 ps
CPU time 0.82 seconds
Started Dec 20 12:41:04 PM PST 23
Finished Dec 20 12:42:08 PM PST 23
Peak memory 199288 kb
Host smart-a70b5080-b374-49d5-aefd-ea2094c1f3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292451097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.3292451097
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.2124601066
Short name T402
Test name
Test status
Simulation time 773656995 ps
CPU time 3.76 seconds
Started Dec 20 12:41:09 PM PST 23
Finished Dec 20 12:42:16 PM PST 23
Peak memory 199568 kb
Host smart-73e8b67c-c166-4a96-a617-227b2e3fa96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124601066 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.2124601066
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.403933290
Short name T345
Test name
Test status
Simulation time 151986150 ps
CPU time 1.05 seconds
Started Dec 20 12:41:06 PM PST 23
Finished Dec 20 12:42:11 PM PST 23
Peak memory 199392 kb
Host smart-411258c7-8eb2-49bb-960f-4b4c48a6831a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403933290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.403933290
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.2099381557
Short name T353
Test name
Test status
Simulation time 119068852 ps
CPU time 1.11 seconds
Started Dec 20 12:41:10 PM PST 23
Finished Dec 20 12:42:14 PM PST 23
Peak memory 199620 kb
Host smart-de921f20-1ba7-4351-a026-11a8b628aafd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099381557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.2099381557
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.2379550331
Short name T104
Test name
Test status
Simulation time 8687804700 ps
CPU time 31.92 seconds
Started Dec 20 12:41:10 PM PST 23
Finished Dec 20 12:42:45 PM PST 23
Peak memory 199624 kb
Host smart-c791af36-424f-4c9b-836d-634a43cf69b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379550331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.2379550331
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.3569715607
Short name T139
Test name
Test status
Simulation time 144237469 ps
CPU time 1.7 seconds
Started Dec 20 12:41:10 PM PST 23
Finished Dec 20 12:42:15 PM PST 23
Peak memory 199384 kb
Host smart-ffa4cbd6-ad4d-45c9-8879-45c07e380d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569715607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.3569715607
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.4191573066
Short name T598
Test name
Test status
Simulation time 213121216 ps
CPU time 1.18 seconds
Started Dec 20 12:41:18 PM PST 23
Finished Dec 20 12:42:24 PM PST 23
Peak memory 199412 kb
Host smart-cc29a88e-0464-4d93-8bee-cd20808061ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191573066 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.4191573066
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.4287801984
Short name T512
Test name
Test status
Simulation time 62364400 ps
CPU time 0.72 seconds
Started Dec 20 12:41:12 PM PST 23
Finished Dec 20 12:42:15 PM PST 23
Peak memory 199296 kb
Host smart-91217969-e3d4-41a6-9b5b-4739ff274bc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287801984 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.4287801984
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.1908797009
Short name T610
Test name
Test status
Simulation time 2344809195 ps
CPU time 7.71 seconds
Started Dec 20 12:41:07 PM PST 23
Finished Dec 20 12:42:21 PM PST 23
Peak memory 217204 kb
Host smart-f047c356-e887-400f-a973-5159fb0fa85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908797009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.1908797009
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.1581759672
Short name T143
Test name
Test status
Simulation time 243909110 ps
CPU time 1.07 seconds
Started Dec 20 12:41:33 PM PST 23
Finished Dec 20 12:42:37 PM PST 23
Peak memory 216560 kb
Host smart-aff6fcdd-6483-47e5-829b-c567026b395c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581759672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.1581759672
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.2568017234
Short name T24
Test name
Test status
Simulation time 143079587 ps
CPU time 0.78 seconds
Started Dec 20 12:41:16 PM PST 23
Finished Dec 20 12:42:21 PM PST 23
Peak memory 199172 kb
Host smart-6978e3a2-d1db-4964-8720-a0df384398e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568017234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.2568017234
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.791600461
Short name T140
Test name
Test status
Simulation time 1396791639 ps
CPU time 5.69 seconds
Started Dec 20 12:41:24 PM PST 23
Finished Dec 20 12:42:34 PM PST 23
Peak memory 199668 kb
Host smart-cef8c476-f381-4e7f-b7ea-e83ad8284fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791600461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.791600461
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.3361650370
Short name T518
Test name
Test status
Simulation time 157367507 ps
CPU time 1.08 seconds
Started Dec 20 12:41:14 PM PST 23
Finished Dec 20 12:42:18 PM PST 23
Peak memory 199412 kb
Host smart-b5a74189-9987-490f-9778-86b7100e1509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361650370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.3361650370
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.1709883514
Short name T166
Test name
Test status
Simulation time 202541760 ps
CPU time 1.3 seconds
Started Dec 20 12:41:15 PM PST 23
Finished Dec 20 12:42:20 PM PST 23
Peak memory 199660 kb
Host smart-cb98337a-511a-4a8d-a5fd-7ab08bd6be41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709883514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.1709883514
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.1432356657
Short name T339
Test name
Test status
Simulation time 3567185085 ps
CPU time 13.26 seconds
Started Dec 20 12:41:37 PM PST 23
Finished Dec 20 12:42:55 PM PST 23
Peak memory 199660 kb
Host smart-34ffdba7-8286-4fd5-92b8-78dd8695d86b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432356657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.1432356657
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.543701476
Short name T450
Test name
Test status
Simulation time 119650930 ps
CPU time 1.36 seconds
Started Dec 20 12:41:09 PM PST 23
Finished Dec 20 12:42:13 PM PST 23
Peak memory 199444 kb
Host smart-08f6116c-f18f-4da1-814f-c469b53aedf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543701476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.543701476
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.200214474
Short name T421
Test name
Test status
Simulation time 231531782 ps
CPU time 1.34 seconds
Started Dec 20 12:41:05 PM PST 23
Finished Dec 20 12:42:08 PM PST 23
Peak memory 199472 kb
Host smart-9720f8cf-af7f-478d-b323-c214a166c6e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200214474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.200214474
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.1534393525
Short name T74
Test name
Test status
Simulation time 76080447 ps
CPU time 0.75 seconds
Started Dec 20 12:41:12 PM PST 23
Finished Dec 20 12:42:19 PM PST 23
Peak memory 199244 kb
Host smart-148816e5-c765-4b42-a905-45ad272bb80e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534393525 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.1534393525
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.2017696324
Short name T603
Test name
Test status
Simulation time 1886509117 ps
CPU time 6.91 seconds
Started Dec 20 12:41:17 PM PST 23
Finished Dec 20 12:42:28 PM PST 23
Peak memory 217320 kb
Host smart-fd6b36cc-1582-465f-a9c8-0e7560970119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017696324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.2017696324
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.2506896414
Short name T331
Test name
Test status
Simulation time 244397907 ps
CPU time 1.03 seconds
Started Dec 20 12:41:07 PM PST 23
Finished Dec 20 12:42:14 PM PST 23
Peak memory 216720 kb
Host smart-a58e563d-4680-43df-8b07-03a6357871bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506896414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.2506896414
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.3817121339
Short name T289
Test name
Test status
Simulation time 192076099 ps
CPU time 0.83 seconds
Started Dec 20 12:41:22 PM PST 23
Finished Dec 20 12:42:28 PM PST 23
Peak memory 199228 kb
Host smart-93480756-7918-48af-9b33-55ea199c889e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817121339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.3817121339
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.668636153
Short name T46
Test name
Test status
Simulation time 778625460 ps
CPU time 3.71 seconds
Started Dec 20 12:41:15 PM PST 23
Finished Dec 20 12:42:23 PM PST 23
Peak memory 199596 kb
Host smart-22549115-34b3-4bd9-85b7-7fa2dea2a996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668636153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.668636153
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.903235941
Short name T351
Test name
Test status
Simulation time 175447152 ps
CPU time 1.11 seconds
Started Dec 20 12:41:11 PM PST 23
Finished Dec 20 12:42:15 PM PST 23
Peak memory 199484 kb
Host smart-bfd2c94c-a9c1-4086-9a23-d19424d43e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903235941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.903235941
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.1277440894
Short name T137
Test name
Test status
Simulation time 195525953 ps
CPU time 1.23 seconds
Started Dec 20 12:41:20 PM PST 23
Finished Dec 20 12:42:26 PM PST 23
Peak memory 199328 kb
Host smart-eefb2cc9-2283-443b-a219-169c99f39ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277440894 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.1277440894
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.3593842932
Short name T567
Test name
Test status
Simulation time 6288165527 ps
CPU time 28.35 seconds
Started Dec 20 12:41:12 PM PST 23
Finished Dec 20 12:42:44 PM PST 23
Peak memory 199620 kb
Host smart-f8618a41-29f9-45b4-865f-ac521e98c291
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593842932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.3593842932
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.1794712297
Short name T495
Test name
Test status
Simulation time 138533951 ps
CPU time 1.59 seconds
Started Dec 20 12:41:17 PM PST 23
Finished Dec 20 12:42:23 PM PST 23
Peak memory 199424 kb
Host smart-878e1286-2a02-442c-85b2-463b943caf83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794712297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.1794712297
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.3267807945
Short name T156
Test name
Test status
Simulation time 128247934 ps
CPU time 1.04 seconds
Started Dec 20 12:41:10 PM PST 23
Finished Dec 20 12:42:15 PM PST 23
Peak memory 199516 kb
Host smart-9c414106-d2fa-4dbd-a9b9-9796fcbd0b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267807945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.3267807945
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.1642380995
Short name T31
Test name
Test status
Simulation time 76030613 ps
CPU time 0.73 seconds
Started Dec 20 12:41:02 PM PST 23
Finished Dec 20 12:42:06 PM PST 23
Peak memory 199320 kb
Host smart-1cb37976-7ef2-4737-be07-36eeadc80afc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642380995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.1642380995
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.3940442219
Short name T47
Test name
Test status
Simulation time 2336674373 ps
CPU time 7.99 seconds
Started Dec 20 12:43:14 PM PST 23
Finished Dec 20 12:43:37 PM PST 23
Peak memory 219060 kb
Host smart-148f462f-83d2-4046-b8ff-e01817b8114e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940442219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.3940442219
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.3890978399
Short name T465
Test name
Test status
Simulation time 244237955 ps
CPU time 0.99 seconds
Started Dec 20 12:41:02 PM PST 23
Finished Dec 20 12:42:07 PM PST 23
Peak memory 216344 kb
Host smart-e28b68fd-6dea-4d99-a105-475e75f4903b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890978399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.3890978399
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.718289339
Short name T261
Test name
Test status
Simulation time 117911286 ps
CPU time 0.75 seconds
Started Dec 20 12:41:17 PM PST 23
Finished Dec 20 12:42:23 PM PST 23
Peak memory 199208 kb
Host smart-6e83f16e-c3e0-4da5-9eaa-9d668fbdc25a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718289339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.718289339
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.2205449836
Short name T25
Test name
Test status
Simulation time 1361407136 ps
CPU time 5.23 seconds
Started Dec 20 12:41:04 PM PST 23
Finished Dec 20 12:42:12 PM PST 23
Peak memory 199564 kb
Host smart-96ff2dcc-d20a-4585-9cf0-55b5860018a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205449836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.2205449836
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.1867185867
Short name T11
Test name
Test status
Simulation time 99981542 ps
CPU time 0.97 seconds
Started Dec 20 12:41:03 PM PST 23
Finished Dec 20 12:42:08 PM PST 23
Peak memory 198388 kb
Host smart-5e013fa8-21dc-469c-bf4e-f948a218ae8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867185867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.1867185867
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.3894101003
Short name T312
Test name
Test status
Simulation time 117666412 ps
CPU time 1.12 seconds
Started Dec 20 12:41:27 PM PST 23
Finished Dec 20 12:42:32 PM PST 23
Peak memory 199584 kb
Host smart-8de72b8d-e19a-4be7-a7a0-1f0475ffd8c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894101003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.3894101003
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.3193492634
Short name T555
Test name
Test status
Simulation time 1363793953 ps
CPU time 7.42 seconds
Started Dec 20 12:41:01 PM PST 23
Finished Dec 20 12:42:13 PM PST 23
Peak memory 199616 kb
Host smart-935cd959-3afb-478f-9b1a-77a41fd50691
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193492634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.3193492634
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.3421072820
Short name T10
Test name
Test status
Simulation time 139025599 ps
CPU time 1.63 seconds
Started Dec 20 12:43:35 PM PST 23
Finished Dec 20 12:43:39 PM PST 23
Peak memory 199184 kb
Host smart-e506256f-7c3f-4f82-9014-5cae692347f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421072820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.3421072820
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.3483502689
Short name T326
Test name
Test status
Simulation time 90157106 ps
CPU time 0.81 seconds
Started Dec 20 12:43:33 PM PST 23
Finished Dec 20 12:43:37 PM PST 23
Peak memory 199204 kb
Host smart-758a35e0-b2e4-4e86-a9da-7b4b3253771d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483502689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.3483502689
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.3299253749
Short name T548
Test name
Test status
Simulation time 62406174 ps
CPU time 0.72 seconds
Started Dec 20 12:41:14 PM PST 23
Finished Dec 20 12:42:18 PM PST 23
Peak memory 199224 kb
Host smart-7700ffeb-4f42-4f41-af83-9b83956436fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299253749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.3299253749
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.382349650
Short name T614
Test name
Test status
Simulation time 1875043065 ps
CPU time 7 seconds
Started Dec 20 12:41:03 PM PST 23
Finished Dec 20 12:42:14 PM PST 23
Peak memory 217416 kb
Host smart-35840678-ffa6-4bec-ac21-2060260aead4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382349650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.382349650
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.3127845218
Short name T136
Test name
Test status
Simulation time 245248193 ps
CPU time 1.12 seconds
Started Dec 20 12:43:33 PM PST 23
Finished Dec 20 12:43:37 PM PST 23
Peak memory 216288 kb
Host smart-8ac34ce2-4510-440b-a85d-9f2ebd4575a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127845218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.3127845218
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.1885600898
Short name T22
Test name
Test status
Simulation time 130400220 ps
CPU time 0.8 seconds
Started Dec 20 12:41:04 PM PST 23
Finished Dec 20 12:42:08 PM PST 23
Peak memory 199288 kb
Host smart-5a4330d0-9392-4d6e-b2e2-d749669df724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885600898 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.1885600898
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.1724365797
Short name T458
Test name
Test status
Simulation time 1636589632 ps
CPU time 5.73 seconds
Started Dec 20 12:43:35 PM PST 23
Finished Dec 20 12:43:43 PM PST 23
Peak memory 199376 kb
Host smart-4a98626e-dee8-46d3-a11b-7d9ad2c08241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724365797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.1724365797
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.1077858473
Short name T165
Test name
Test status
Simulation time 141197767 ps
CPU time 1.02 seconds
Started Dec 20 12:41:06 PM PST 23
Finished Dec 20 12:42:10 PM PST 23
Peak memory 199488 kb
Host smart-c3894cb8-40f8-46b6-8c70-acfe83659347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077858473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.1077858473
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.3930884444
Short name T82
Test name
Test status
Simulation time 256575371 ps
CPU time 1.38 seconds
Started Dec 20 12:41:02 PM PST 23
Finished Dec 20 12:42:08 PM PST 23
Peak memory 199540 kb
Host smart-bf34e7d8-c5aa-4789-9e8e-ce41f7016e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930884444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.3930884444
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.3457196851
Short name T354
Test name
Test status
Simulation time 4363521563 ps
CPU time 17.19 seconds
Started Dec 20 12:41:14 PM PST 23
Finished Dec 20 12:42:35 PM PST 23
Peak memory 199600 kb
Host smart-8dd70f41-1e83-4a55-bb19-ed57ecb2cbeb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457196851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.3457196851
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.3854625056
Short name T371
Test name
Test status
Simulation time 124189339 ps
CPU time 1.38 seconds
Started Dec 20 12:43:32 PM PST 23
Finished Dec 20 12:43:35 PM PST 23
Peak memory 199160 kb
Host smart-e6a6ddbd-113a-4759-a419-c51a4bb5db3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854625056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.3854625056
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.220894914
Short name T552
Test name
Test status
Simulation time 150818790 ps
CPU time 1.07 seconds
Started Dec 20 12:43:33 PM PST 23
Finished Dec 20 12:43:37 PM PST 23
Peak memory 199232 kb
Host smart-a8501254-ffc4-44b9-8a90-f5d83e729dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220894914 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.220894914
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.643517268
Short name T44
Test name
Test status
Simulation time 62359538 ps
CPU time 0.66 seconds
Started Dec 20 12:41:07 PM PST 23
Finished Dec 20 12:42:14 PM PST 23
Peak memory 198968 kb
Host smart-289fa7fe-b058-4ecf-a84b-02fd745dc5a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643517268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.643517268
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.1435545250
Short name T489
Test name
Test status
Simulation time 1230371100 ps
CPU time 5.37 seconds
Started Dec 20 12:41:10 PM PST 23
Finished Dec 20 12:42:18 PM PST 23
Peak memory 216276 kb
Host smart-e16cae7f-037b-49d1-9222-5bd0dc5227fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435545250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.1435545250
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.3763303924
Short name T169
Test name
Test status
Simulation time 245162622 ps
CPU time 1.01 seconds
Started Dec 20 12:41:14 PM PST 23
Finished Dec 20 12:42:19 PM PST 23
Peak memory 216388 kb
Host smart-298a23de-d0c4-49e8-bf57-03f0c61e53bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763303924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.3763303924
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.607096838
Short name T80
Test name
Test status
Simulation time 128775229 ps
CPU time 0.8 seconds
Started Dec 20 12:41:06 PM PST 23
Finished Dec 20 12:42:11 PM PST 23
Peak memory 199280 kb
Host smart-a4effd60-d170-4277-aadb-457ef8d2a2e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607096838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.607096838
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.3880657662
Short name T374
Test name
Test status
Simulation time 934453535 ps
CPU time 4.52 seconds
Started Dec 20 12:41:14 PM PST 23
Finished Dec 20 12:42:22 PM PST 23
Peak memory 199588 kb
Host smart-29383c54-cbfd-4f35-9cc0-49aa5dbe40f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880657662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.3880657662
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.2077855285
Short name T365
Test name
Test status
Simulation time 97400239 ps
CPU time 0.93 seconds
Started Dec 20 12:41:19 PM PST 23
Finished Dec 20 12:42:25 PM PST 23
Peak memory 199336 kb
Host smart-9b6187b1-041e-4221-baf6-319454a4e05b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077855285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.2077855285
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.941771812
Short name T271
Test name
Test status
Simulation time 126707444 ps
CPU time 1.16 seconds
Started Dec 20 12:41:06 PM PST 23
Finished Dec 20 12:42:11 PM PST 23
Peak memory 199532 kb
Host smart-cc871894-de7e-440a-a7fc-e2ef62e47a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941771812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.941771812
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.3321696109
Short name T496
Test name
Test status
Simulation time 282077360 ps
CPU time 1.78 seconds
Started Dec 20 12:41:08 PM PST 23
Finished Dec 20 12:42:14 PM PST 23
Peak memory 199684 kb
Host smart-7ddcd11d-1a9e-44a1-a2d2-e3c4f1e9dab3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321696109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.3321696109
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.2768310557
Short name T388
Test name
Test status
Simulation time 147532128 ps
CPU time 1.67 seconds
Started Dec 20 12:41:05 PM PST 23
Finished Dec 20 12:42:11 PM PST 23
Peak memory 199432 kb
Host smart-d8929543-1c6c-4dfa-8e1c-c2ff27245219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768310557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.2768310557
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.3983277581
Short name T356
Test name
Test status
Simulation time 194987023 ps
CPU time 1.11 seconds
Started Dec 20 12:41:16 PM PST 23
Finished Dec 20 12:42:20 PM PST 23
Peak memory 199364 kb
Host smart-53c6cdb4-a4ac-4854-b97c-88dd552cee2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983277581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.3983277581
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.2180678033
Short name T283
Test name
Test status
Simulation time 69950465 ps
CPU time 0.72 seconds
Started Dec 20 12:41:12 PM PST 23
Finished Dec 20 12:42:19 PM PST 23
Peak memory 199180 kb
Host smart-648d65fb-6c21-4576-ba56-3cee8083474a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180678033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.2180678033
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.4016072698
Short name T475
Test name
Test status
Simulation time 2369171944 ps
CPU time 7.74 seconds
Started Dec 20 12:41:23 PM PST 23
Finished Dec 20 12:42:36 PM PST 23
Peak memory 216920 kb
Host smart-930a5c35-d47e-4e82-a96d-07b5e000fef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016072698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.4016072698
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.2268352984
Short name T154
Test name
Test status
Simulation time 243122560 ps
CPU time 1.07 seconds
Started Dec 20 12:41:18 PM PST 23
Finished Dec 20 12:42:24 PM PST 23
Peak memory 216720 kb
Host smart-0da80bcf-8007-44cc-8026-d52898dfb0d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268352984 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.2268352984
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.609106586
Short name T20
Test name
Test status
Simulation time 143236687 ps
CPU time 0.76 seconds
Started Dec 20 12:41:25 PM PST 23
Finished Dec 20 12:42:29 PM PST 23
Peak memory 199208 kb
Host smart-a117c7b0-2064-4382-8eef-fc8e15feaaed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609106586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.609106586
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.3046751535
Short name T286
Test name
Test status
Simulation time 1508129606 ps
CPU time 5.73 seconds
Started Dec 20 12:41:05 PM PST 23
Finished Dec 20 12:42:15 PM PST 23
Peak memory 199272 kb
Host smart-133f0139-fae5-4ca5-9b48-f63110c75a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046751535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.3046751535
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.48271426
Short name T416
Test name
Test status
Simulation time 95776767 ps
CPU time 0.91 seconds
Started Dec 20 12:41:22 PM PST 23
Finished Dec 20 12:42:28 PM PST 23
Peak memory 199440 kb
Host smart-5b98c2b3-d9a9-4487-ab5c-5395b5d48581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48271426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.48271426
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.2822332499
Short name T568
Test name
Test status
Simulation time 122367730 ps
CPU time 1.12 seconds
Started Dec 20 12:41:12 PM PST 23
Finished Dec 20 12:42:16 PM PST 23
Peak memory 199624 kb
Host smart-65397184-ec03-4594-bcd3-c614feff94b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822332499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.2822332499
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.1091900545
Short name T106
Test name
Test status
Simulation time 6610506629 ps
CPU time 22.99 seconds
Started Dec 20 12:41:17 PM PST 23
Finished Dec 20 12:42:45 PM PST 23
Peak memory 199668 kb
Host smart-8082963e-0d88-451a-af28-626f4fed69a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091900545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.1091900545
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.3509313668
Short name T291
Test name
Test status
Simulation time 152823499 ps
CPU time 1.73 seconds
Started Dec 20 12:41:13 PM PST 23
Finished Dec 20 12:42:18 PM PST 23
Peak memory 199372 kb
Host smart-f08bff8d-e59f-4043-8a44-72b7719523f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509313668 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.3509313668
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.2507557442
Short name T470
Test name
Test status
Simulation time 122742587 ps
CPU time 1 seconds
Started Dec 20 12:41:11 PM PST 23
Finished Dec 20 12:42:15 PM PST 23
Peak memory 199428 kb
Host smart-835e05b4-8843-4c0e-85a4-4b698a440523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507557442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.2507557442
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.1060061684
Short name T144
Test name
Test status
Simulation time 75567048 ps
CPU time 0.77 seconds
Started Dec 20 12:41:14 PM PST 23
Finished Dec 20 12:42:19 PM PST 23
Peak memory 199204 kb
Host smart-e9308a12-00d6-4fa8-9452-7e8111b94c7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060061684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.1060061684
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.3839198719
Short name T172
Test name
Test status
Simulation time 244190886 ps
CPU time 1.02 seconds
Started Dec 20 12:41:24 PM PST 23
Finished Dec 20 12:42:29 PM PST 23
Peak memory 216636 kb
Host smart-6323ddf2-ed98-4b6a-8f11-ccea2c4010d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839198719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.3839198719
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.3810207553
Short name T435
Test name
Test status
Simulation time 207160554 ps
CPU time 0.84 seconds
Started Dec 20 12:41:20 PM PST 23
Finished Dec 20 12:42:25 PM PST 23
Peak memory 199200 kb
Host smart-97d59130-ed6d-41af-b6e5-2346910aff7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810207553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.3810207553
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.1210230781
Short name T446
Test name
Test status
Simulation time 916908885 ps
CPU time 4.38 seconds
Started Dec 20 12:41:12 PM PST 23
Finished Dec 20 12:42:22 PM PST 23
Peak memory 199572 kb
Host smart-2fbceb05-f3b8-4f0a-9e45-7a82d6712bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210230781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.1210230781
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.1209660516
Short name T466
Test name
Test status
Simulation time 183868586 ps
CPU time 1.16 seconds
Started Dec 20 12:41:14 PM PST 23
Finished Dec 20 12:42:19 PM PST 23
Peak memory 198636 kb
Host smart-60ea8a0a-7373-4079-8ec3-97c4a3cb8bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209660516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.1209660516
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.219877721
Short name T593
Test name
Test status
Simulation time 250530554 ps
CPU time 1.41 seconds
Started Dec 20 12:41:13 PM PST 23
Finished Dec 20 12:42:18 PM PST 23
Peak memory 199572 kb
Host smart-0ce19409-9058-4b19-a43a-c1f21224616c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219877721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.219877721
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.3115487239
Short name T583
Test name
Test status
Simulation time 4800652351 ps
CPU time 18.2 seconds
Started Dec 20 12:41:27 PM PST 23
Finished Dec 20 12:42:50 PM PST 23
Peak memory 199500 kb
Host smart-eb258959-d7fe-4076-8878-5e05b22551ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115487239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.3115487239
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.4073321547
Short name T535
Test name
Test status
Simulation time 242745157 ps
CPU time 1.67 seconds
Started Dec 20 12:41:26 PM PST 23
Finished Dec 20 12:42:32 PM PST 23
Peak memory 199156 kb
Host smart-c5053731-cd25-4983-b0e1-1c62a56ac803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073321547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.4073321547
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.186759311
Short name T497
Test name
Test status
Simulation time 263823031 ps
CPU time 1.49 seconds
Started Dec 20 12:41:25 PM PST 23
Finished Dec 20 12:42:30 PM PST 23
Peak memory 199424 kb
Host smart-59f10355-8474-427f-b274-c7103f78e5d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186759311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.186759311
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.1976798561
Short name T173
Test name
Test status
Simulation time 98660842 ps
CPU time 0.79 seconds
Started Dec 20 12:40:37 PM PST 23
Finished Dec 20 12:41:41 PM PST 23
Peak memory 199332 kb
Host smart-76e45411-cb6b-4d42-9ade-8e14608f892e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976798561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.1976798561
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.1844859393
Short name T476
Test name
Test status
Simulation time 1886834348 ps
CPU time 7.1 seconds
Started Dec 20 12:40:50 PM PST 23
Finished Dec 20 12:42:01 PM PST 23
Peak memory 229436 kb
Host smart-8f3683f3-dfee-46db-95ba-7d469e339e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844859393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.1844859393
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.3219725477
Short name T170
Test name
Test status
Simulation time 245290732 ps
CPU time 1 seconds
Started Dec 20 12:40:44 PM PST 23
Finished Dec 20 12:41:48 PM PST 23
Peak memory 216716 kb
Host smart-aa5e5f5d-a7f8-4bba-9655-0776b554ce13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219725477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.3219725477
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.3585388300
Short name T19
Test name
Test status
Simulation time 188906335 ps
CPU time 0.83 seconds
Started Dec 20 12:40:27 PM PST 23
Finished Dec 20 12:41:30 PM PST 23
Peak memory 199168 kb
Host smart-1cbf707a-d443-4386-b4f1-015f63528c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585388300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.3585388300
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.3030351682
Short name T596
Test name
Test status
Simulation time 884586883 ps
CPU time 3.88 seconds
Started Dec 20 12:41:48 PM PST 23
Finished Dec 20 12:42:55 PM PST 23
Peak memory 198100 kb
Host smart-d6c9611d-4d79-42af-826f-f286fb7c5637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030351682 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.3030351682
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.3982375420
Short name T71
Test name
Test status
Simulation time 16524871204 ps
CPU time 33.16 seconds
Started Dec 20 12:40:22 PM PST 23
Finished Dec 20 12:41:54 PM PST 23
Peak memory 217108 kb
Host smart-b7982f8b-b97d-4d4d-9bb0-4052b2c302a0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982375420 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.3982375420
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.1711067895
Short name T152
Test name
Test status
Simulation time 97622673 ps
CPU time 0.93 seconds
Started Dec 20 12:40:23 PM PST 23
Finished Dec 20 12:41:23 PM PST 23
Peak memory 199392 kb
Host smart-3688e99d-f62c-4403-b08d-091529973177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711067895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.1711067895
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.2405118140
Short name T263
Test name
Test status
Simulation time 260699034 ps
CPU time 1.66 seconds
Started Dec 20 12:40:20 PM PST 23
Finished Dec 20 12:41:22 PM PST 23
Peak memory 199640 kb
Host smart-82f5fc1e-3e85-4faa-af8b-29e19d105680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405118140 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.2405118140
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.3210952889
Short name T318
Test name
Test status
Simulation time 4612268399 ps
CPU time 17.32 seconds
Started Dec 20 12:40:24 PM PST 23
Finished Dec 20 12:41:42 PM PST 23
Peak memory 199688 kb
Host smart-3f82df59-91ee-4c4f-b131-a9d2d1c24875
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210952889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.3210952889
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.2340143659
Short name T275
Test name
Test status
Simulation time 120607621 ps
CPU time 1.46 seconds
Started Dec 20 12:40:37 PM PST 23
Finished Dec 20 12:41:41 PM PST 23
Peak memory 199412 kb
Host smart-170e5eab-c663-4b5c-8c51-daf4f660560c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340143659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.2340143659
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.3516128203
Short name T272
Test name
Test status
Simulation time 209200870 ps
CPU time 1.28 seconds
Started Dec 20 12:40:32 PM PST 23
Finished Dec 20 12:41:34 PM PST 23
Peak memory 199412 kb
Host smart-57b0a289-8b11-40ac-9cdd-a00031a61533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516128203 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.3516128203
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.60148554
Short name T297
Test name
Test status
Simulation time 83202359 ps
CPU time 0.8 seconds
Started Dec 20 12:43:14 PM PST 23
Finished Dec 20 12:43:29 PM PST 23
Peak memory 197652 kb
Host smart-40818853-c667-42fc-a670-a79633baffd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60148554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.60148554
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.198741206
Short name T554
Test name
Test status
Simulation time 1224922252 ps
CPU time 5.14 seconds
Started Dec 20 12:41:05 PM PST 23
Finished Dec 20 12:42:14 PM PST 23
Peak memory 221124 kb
Host smart-a7749526-72fc-4265-90ac-1f2c548fe0ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198741206 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.198741206
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.2009406686
Short name T274
Test name
Test status
Simulation time 244288509 ps
CPU time 1.11 seconds
Started Dec 20 12:41:07 PM PST 23
Finished Dec 20 12:42:12 PM PST 23
Peak memory 216420 kb
Host smart-f6894412-9e9a-4cad-864e-7ff03c8227ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009406686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.2009406686
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.3119910210
Short name T580
Test name
Test status
Simulation time 240033146 ps
CPU time 0.91 seconds
Started Dec 20 12:41:12 PM PST 23
Finished Dec 20 12:42:15 PM PST 23
Peak memory 199248 kb
Host smart-d234e7c7-bb7e-46c1-9d97-de3cd6cff6ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119910210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.3119910210
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.3260706164
Short name T270
Test name
Test status
Simulation time 797322643 ps
CPU time 4.22 seconds
Started Dec 20 12:41:07 PM PST 23
Finished Dec 20 12:42:17 PM PST 23
Peak memory 199524 kb
Host smart-152d2926-5700-42f7-8362-de65e5a5c0c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260706164 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.3260706164
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.2123174665
Short name T300
Test name
Test status
Simulation time 147788286 ps
CPU time 1.08 seconds
Started Dec 20 12:43:33 PM PST 23
Finished Dec 20 12:43:37 PM PST 23
Peak memory 199200 kb
Host smart-8f664499-63eb-401b-8049-5b3e3c654bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123174665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.2123174665
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.2729302711
Short name T88
Test name
Test status
Simulation time 193454454 ps
CPU time 1.29 seconds
Started Dec 20 12:41:12 PM PST 23
Finished Dec 20 12:42:16 PM PST 23
Peak memory 199584 kb
Host smart-87fbf3aa-2f7b-432d-8e63-bf3c00a86f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729302711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.2729302711
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.81260931
Short name T2
Test name
Test status
Simulation time 10382235166 ps
CPU time 33.52 seconds
Started Dec 20 12:41:03 PM PST 23
Finished Dec 20 12:42:40 PM PST 23
Peak memory 199376 kb
Host smart-9f1e785c-a783-4616-92aa-32c0e23653e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81260931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.81260931
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.3075034776
Short name T566
Test name
Test status
Simulation time 139200207 ps
CPU time 1.68 seconds
Started Dec 20 12:41:07 PM PST 23
Finished Dec 20 12:42:12 PM PST 23
Peak memory 199296 kb
Host smart-4bba2a14-9a78-4b25-99d9-6202e6f7347b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075034776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.3075034776
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.4070264323
Short name T128
Test name
Test status
Simulation time 272817453 ps
CPU time 1.36 seconds
Started Dec 20 12:41:04 PM PST 23
Finished Dec 20 12:42:08 PM PST 23
Peak memory 199420 kb
Host smart-a9e39051-3ff4-42e5-8626-9b192a976422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070264323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.4070264323
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.875423986
Short name T296
Test name
Test status
Simulation time 91445074 ps
CPU time 0.79 seconds
Started Dec 20 12:41:06 PM PST 23
Finished Dec 20 12:42:11 PM PST 23
Peak memory 199204 kb
Host smart-f8cd3ce5-36a2-45ea-9885-cd2cc6080af5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875423986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.875423986
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.4005393438
Short name T54
Test name
Test status
Simulation time 2376756968 ps
CPU time 7.6 seconds
Started Dec 20 12:41:14 PM PST 23
Finished Dec 20 12:42:25 PM PST 23
Peak memory 216536 kb
Host smart-5929cbe1-56b9-47f7-bce6-8a7f3d378065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005393438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.4005393438
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.2720947398
Short name T306
Test name
Test status
Simulation time 246316086 ps
CPU time 0.99 seconds
Started Dec 20 12:41:20 PM PST 23
Finished Dec 20 12:42:25 PM PST 23
Peak memory 216312 kb
Host smart-48555fc3-11f7-4e3c-a43f-2794cc7bb602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720947398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.2720947398
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.542400154
Short name T419
Test name
Test status
Simulation time 102107873 ps
CPU time 0.73 seconds
Started Dec 20 12:43:32 PM PST 23
Finished Dec 20 12:43:34 PM PST 23
Peak memory 198880 kb
Host smart-eb02cc03-4301-49ed-936c-8a6c21e16902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542400154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.542400154
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.797867142
Short name T550
Test name
Test status
Simulation time 807711016 ps
CPU time 3.96 seconds
Started Dec 20 12:41:08 PM PST 23
Finished Dec 20 12:42:16 PM PST 23
Peak memory 199348 kb
Host smart-a640e5d5-2de2-439f-951a-ffb45584bd97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797867142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.797867142
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.112162940
Short name T299
Test name
Test status
Simulation time 167358838 ps
CPU time 1.18 seconds
Started Dec 20 12:41:06 PM PST 23
Finished Dec 20 12:42:11 PM PST 23
Peak memory 199468 kb
Host smart-19901351-46e2-46f1-a919-b269cb0a5401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112162940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.112162940
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.625883775
Short name T369
Test name
Test status
Simulation time 242571293 ps
CPU time 1.5 seconds
Started Dec 20 12:41:07 PM PST 23
Finished Dec 20 12:42:15 PM PST 23
Peak memory 199544 kb
Host smart-4f472a41-d157-463a-8753-03f74013e5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625883775 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.625883775
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.2744573561
Short name T398
Test name
Test status
Simulation time 8797473205 ps
CPU time 31.8 seconds
Started Dec 20 12:41:04 PM PST 23
Finished Dec 20 12:42:39 PM PST 23
Peak memory 199572 kb
Host smart-6d7e2fc2-90af-4edd-b336-6491031988cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744573561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.2744573561
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.2093590757
Short name T90
Test name
Test status
Simulation time 135158415 ps
CPU time 1.48 seconds
Started Dec 20 12:41:20 PM PST 23
Finished Dec 20 12:42:26 PM PST 23
Peak memory 199472 kb
Host smart-8f4f1a60-327e-44d3-b887-4cf1cee4ff60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093590757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.2093590757
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.2351204592
Short name T498
Test name
Test status
Simulation time 122538935 ps
CPU time 0.92 seconds
Started Dec 20 12:41:10 PM PST 23
Finished Dec 20 12:42:17 PM PST 23
Peak memory 199432 kb
Host smart-fb65751b-1745-4630-bec8-fd56ed0a2ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351204592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.2351204592
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.3485424288
Short name T364
Test name
Test status
Simulation time 63522775 ps
CPU time 0.73 seconds
Started Dec 20 12:41:06 PM PST 23
Finished Dec 20 12:42:10 PM PST 23
Peak memory 198976 kb
Host smart-3b1fd22c-a683-48d8-a33c-6802050cdf65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485424288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.3485424288
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.2509879864
Short name T473
Test name
Test status
Simulation time 1226335702 ps
CPU time 6 seconds
Started Dec 20 12:41:06 PM PST 23
Finished Dec 20 12:42:16 PM PST 23
Peak memory 221396 kb
Host smart-b6e0cfa9-6dae-46b1-940c-6783b3046a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509879864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.2509879864
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.3126956389
Short name T570
Test name
Test status
Simulation time 243902525 ps
CPU time 1.11 seconds
Started Dec 20 12:41:19 PM PST 23
Finished Dec 20 12:42:25 PM PST 23
Peak memory 216604 kb
Host smart-32782675-544e-4eeb-823c-4146c06b2397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126956389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.3126956389
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.3960207289
Short name T407
Test name
Test status
Simulation time 104406720 ps
CPU time 0.78 seconds
Started Dec 20 12:41:24 PM PST 23
Finished Dec 20 12:42:29 PM PST 23
Peak memory 199328 kb
Host smart-fd54b4ce-08fa-4ff4-8e9e-0f7a66c1717d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960207289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.3960207289
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.1050875680
Short name T42
Test name
Test status
Simulation time 1913750049 ps
CPU time 7 seconds
Started Dec 20 12:41:10 PM PST 23
Finished Dec 20 12:42:20 PM PST 23
Peak memory 199572 kb
Host smart-dfa2062d-fed0-4e2a-8ce3-4cc2bcae4575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050875680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.1050875680
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.296367065
Short name T49
Test name
Test status
Simulation time 150364503 ps
CPU time 1.07 seconds
Started Dec 20 12:41:14 PM PST 23
Finished Dec 20 12:42:19 PM PST 23
Peak memory 199316 kb
Host smart-3c5f6e3c-1f73-48ef-9eae-e83d82c3a476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296367065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.296367065
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.3252379936
Short name T368
Test name
Test status
Simulation time 198821555 ps
CPU time 1.29 seconds
Started Dec 20 12:41:06 PM PST 23
Finished Dec 20 12:42:11 PM PST 23
Peak memory 199532 kb
Host smart-e263731b-f177-46fa-88c5-5389459e8d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252379936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.3252379936
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.3908981893
Short name T520
Test name
Test status
Simulation time 5295447519 ps
CPU time 18.85 seconds
Started Dec 20 12:41:17 PM PST 23
Finished Dec 20 12:42:40 PM PST 23
Peak memory 199444 kb
Host smart-c0940ce0-d040-4f89-becb-8c80fd090ea6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908981893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.3908981893
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.817007018
Short name T422
Test name
Test status
Simulation time 127357030 ps
CPU time 1.58 seconds
Started Dec 20 12:41:16 PM PST 23
Finished Dec 20 12:42:21 PM PST 23
Peak memory 199472 kb
Host smart-a5e98ce4-b84f-4828-b31c-1acbfaed1b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817007018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.817007018
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.1787778826
Short name T396
Test name
Test status
Simulation time 167277223 ps
CPU time 1.16 seconds
Started Dec 20 12:41:12 PM PST 23
Finished Dec 20 12:42:16 PM PST 23
Peak memory 199460 kb
Host smart-515796ef-89a7-413a-b1ed-2f8f1d03c43e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787778826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.1787778826
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.848396629
Short name T612
Test name
Test status
Simulation time 66483475 ps
CPU time 0.69 seconds
Started Dec 20 12:41:32 PM PST 23
Finished Dec 20 12:42:35 PM PST 23
Peak memory 199188 kb
Host smart-73ba9cf2-059d-470f-9014-2bd5b7c4fb69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848396629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.848396629
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.2424563935
Short name T571
Test name
Test status
Simulation time 1219077267 ps
CPU time 5.25 seconds
Started Dec 20 12:41:33 PM PST 23
Finished Dec 20 12:42:42 PM PST 23
Peak memory 229436 kb
Host smart-11dae219-23b6-4dd5-8712-a65b79775720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424563935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.2424563935
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.710740098
Short name T14
Test name
Test status
Simulation time 243367119 ps
CPU time 1.02 seconds
Started Dec 20 12:41:32 PM PST 23
Finished Dec 20 12:42:36 PM PST 23
Peak memory 216600 kb
Host smart-86cc5c3d-e7d3-41d4-bd92-6646789d647f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710740098 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.710740098
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.267404154
Short name T544
Test name
Test status
Simulation time 214082867 ps
CPU time 0.87 seconds
Started Dec 20 12:41:16 PM PST 23
Finished Dec 20 12:42:21 PM PST 23
Peak memory 199272 kb
Host smart-7f9c2057-3d58-4f51-8485-266f98ac258f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267404154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.267404154
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.2255587211
Short name T132
Test name
Test status
Simulation time 1478591825 ps
CPU time 5.58 seconds
Started Dec 20 12:41:23 PM PST 23
Finished Dec 20 12:42:34 PM PST 23
Peak memory 199428 kb
Host smart-ca0f2837-a94b-42ce-a5a1-75c005ef029b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255587211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.2255587211
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.3985904019
Short name T320
Test name
Test status
Simulation time 146083462 ps
CPU time 1.07 seconds
Started Dec 20 12:41:21 PM PST 23
Finished Dec 20 12:42:26 PM PST 23
Peak memory 199464 kb
Host smart-b21418c7-ba9a-4727-bb55-dd1ed4a0d158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985904019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.3985904019
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.4086759280
Short name T277
Test name
Test status
Simulation time 254777280 ps
CPU time 1.48 seconds
Started Dec 20 12:41:12 PM PST 23
Finished Dec 20 12:42:17 PM PST 23
Peak memory 199452 kb
Host smart-b51a3aec-47c7-4372-bd92-0fd5770215cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086759280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.4086759280
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.2382400421
Short name T282
Test name
Test status
Simulation time 18550882276 ps
CPU time 61.26 seconds
Started Dec 20 12:41:48 PM PST 23
Finished Dec 20 12:43:52 PM PST 23
Peak memory 199696 kb
Host smart-19bbbc57-51ab-41f1-8bc5-899e7ace4911
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382400421 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.2382400421
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.3187428821
Short name T424
Test name
Test status
Simulation time 120897149 ps
CPU time 1.46 seconds
Started Dec 20 12:41:12 PM PST 23
Finished Dec 20 12:42:16 PM PST 23
Peak memory 199324 kb
Host smart-41899ef8-090b-4f2b-b107-4e33dda28c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187428821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.3187428821
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.1572136856
Short name T343
Test name
Test status
Simulation time 150494373 ps
CPU time 1 seconds
Started Dec 20 12:41:14 PM PST 23
Finished Dec 20 12:42:19 PM PST 23
Peak memory 199364 kb
Host smart-85162d3f-3181-4b7d-836f-09dbe4d53be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572136856 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.1572136856
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.1913224947
Short name T605
Test name
Test status
Simulation time 76288802 ps
CPU time 0.74 seconds
Started Dec 20 12:41:35 PM PST 23
Finished Dec 20 12:42:40 PM PST 23
Peak memory 199040 kb
Host smart-5f3fbfd4-7834-4800-8ee3-4494b377eedf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913224947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.1913224947
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.1703587647
Short name T519
Test name
Test status
Simulation time 2347428556 ps
CPU time 7.72 seconds
Started Dec 20 12:41:37 PM PST 23
Finished Dec 20 12:42:48 PM PST 23
Peak memory 217128 kb
Host smart-58a33536-085e-46d5-af10-4a417c4b2a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703587647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.1703587647
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.1758636960
Short name T337
Test name
Test status
Simulation time 244240470 ps
CPU time 0.99 seconds
Started Dec 20 12:41:33 PM PST 23
Finished Dec 20 12:42:38 PM PST 23
Peak memory 216632 kb
Host smart-08508bdc-f17a-457e-bdc8-1ebed532d6f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758636960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.1758636960
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.1087484895
Short name T410
Test name
Test status
Simulation time 93660067 ps
CPU time 0.72 seconds
Started Dec 20 12:41:30 PM PST 23
Finished Dec 20 12:42:34 PM PST 23
Peak memory 199276 kb
Host smart-eac9260e-ff50-4ecd-abe8-20119744c3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087484895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.1087484895
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.2327168498
Short name T349
Test name
Test status
Simulation time 923077023 ps
CPU time 4.34 seconds
Started Dec 20 12:41:38 PM PST 23
Finished Dec 20 12:42:46 PM PST 23
Peak memory 199308 kb
Host smart-2c6ba57f-fd2d-4d62-9da6-4575a92ef10b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327168498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.2327168498
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.2858379945
Short name T142
Test name
Test status
Simulation time 170370048 ps
CPU time 1.1 seconds
Started Dec 20 12:41:34 PM PST 23
Finished Dec 20 12:42:38 PM PST 23
Peak memory 199344 kb
Host smart-8b268829-1973-45f9-a8b9-16adc6a5b24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858379945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.2858379945
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.316057307
Short name T324
Test name
Test status
Simulation time 251945669 ps
CPU time 1.49 seconds
Started Dec 20 12:41:34 PM PST 23
Finished Dec 20 12:42:41 PM PST 23
Peak memory 199624 kb
Host smart-89619e07-03ec-4de4-ae9f-9b5fdfe88c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316057307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.316057307
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.1113910912
Short name T102
Test name
Test status
Simulation time 5757585555 ps
CPU time 26.28 seconds
Started Dec 20 12:41:40 PM PST 23
Finished Dec 20 12:43:09 PM PST 23
Peak memory 199604 kb
Host smart-27434ee4-d21e-4d6e-84e7-b7094236f13a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113910912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.1113910912
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.3849114842
Short name T129
Test name
Test status
Simulation time 455651887 ps
CPU time 2.36 seconds
Started Dec 20 12:41:25 PM PST 23
Finished Dec 20 12:42:32 PM PST 23
Peak memory 199356 kb
Host smart-7812574d-9971-4b95-a909-903d2a716b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849114842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.3849114842
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.510692875
Short name T617
Test name
Test status
Simulation time 164996059 ps
CPU time 1.11 seconds
Started Dec 20 12:41:35 PM PST 23
Finished Dec 20 12:42:39 PM PST 23
Peak memory 199484 kb
Host smart-9352a677-11d9-4187-9a45-9543ceafa719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510692875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.510692875
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.4071665549
Short name T387
Test name
Test status
Simulation time 78739801 ps
CPU time 0.71 seconds
Started Dec 20 12:41:29 PM PST 23
Finished Dec 20 12:42:33 PM PST 23
Peak memory 199232 kb
Host smart-8aebddb0-3d6c-49cf-8e24-8225ff708328
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071665549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.4071665549
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.2907595028
Short name T39
Test name
Test status
Simulation time 1220118921 ps
CPU time 5.5 seconds
Started Dec 20 12:41:32 PM PST 23
Finished Dec 20 12:42:43 PM PST 23
Peak memory 221436 kb
Host smart-c1729ea1-86a8-41a6-b90d-c95e97e04e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907595028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.2907595028
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.3102273097
Short name T141
Test name
Test status
Simulation time 243540006 ps
CPU time 1.13 seconds
Started Dec 20 12:41:30 PM PST 23
Finished Dec 20 12:42:35 PM PST 23
Peak memory 216532 kb
Host smart-737043a3-0908-4cb4-b22d-c5160fed6c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102273097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.3102273097
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.2999912712
Short name T405
Test name
Test status
Simulation time 216523660 ps
CPU time 0.86 seconds
Started Dec 20 12:41:34 PM PST 23
Finished Dec 20 12:42:40 PM PST 23
Peak memory 199260 kb
Host smart-01190001-3124-477c-ad8f-896580e5e6c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999912712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.2999912712
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.2097398110
Short name T587
Test name
Test status
Simulation time 1674492871 ps
CPU time 6.65 seconds
Started Dec 20 12:41:33 PM PST 23
Finished Dec 20 12:42:43 PM PST 23
Peak memory 199484 kb
Host smart-99547395-be26-4b85-901d-6795946c8046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097398110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.2097398110
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.906458666
Short name T403
Test name
Test status
Simulation time 113364913 ps
CPU time 0.94 seconds
Started Dec 20 12:41:36 PM PST 23
Finished Dec 20 12:42:40 PM PST 23
Peak memory 199460 kb
Host smart-0be90918-56ff-4726-ae4f-1052dfebfdec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906458666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.906458666
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.2787709719
Short name T355
Test name
Test status
Simulation time 123775590 ps
CPU time 1.1 seconds
Started Dec 20 12:41:39 PM PST 23
Finished Dec 20 12:42:43 PM PST 23
Peak memory 199604 kb
Host smart-f703441f-d3cd-4435-91ff-dfddc374aa8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787709719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.2787709719
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.2910348983
Short name T408
Test name
Test status
Simulation time 1753837587 ps
CPU time 7.57 seconds
Started Dec 20 12:41:36 PM PST 23
Finished Dec 20 12:42:46 PM PST 23
Peak memory 199612 kb
Host smart-c6f4d493-78cf-4f0e-9b2e-417f68052fb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910348983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.2910348983
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.1316802812
Short name T381
Test name
Test status
Simulation time 124286320 ps
CPU time 1.36 seconds
Started Dec 20 12:41:33 PM PST 23
Finished Dec 20 12:42:37 PM PST 23
Peak memory 199232 kb
Host smart-3bd651d5-95c6-4148-a123-73cb50dc6d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316802812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.1316802812
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.2673370053
Short name T547
Test name
Test status
Simulation time 181158676 ps
CPU time 1.33 seconds
Started Dec 20 12:41:46 PM PST 23
Finished Dec 20 12:42:50 PM PST 23
Peak memory 199604 kb
Host smart-88ffe1d5-99e3-444a-a0e2-c204a4597669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673370053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.2673370053
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.2731821382
Short name T397
Test name
Test status
Simulation time 73450364 ps
CPU time 0.72 seconds
Started Dec 20 12:41:30 PM PST 23
Finished Dec 20 12:42:34 PM PST 23
Peak memory 199244 kb
Host smart-93c5b067-9549-4e92-b642-acabce9ef7ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731821382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.2731821382
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.2319543659
Short name T464
Test name
Test status
Simulation time 1896997668 ps
CPU time 6.83 seconds
Started Dec 20 12:41:35 PM PST 23
Finished Dec 20 12:42:46 PM PST 23
Peak memory 217436 kb
Host smart-feb67168-0fb3-4b68-8bd8-85a20008ddfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319543659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.2319543659
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.1096963506
Short name T438
Test name
Test status
Simulation time 244522964 ps
CPU time 1.12 seconds
Started Dec 20 12:41:40 PM PST 23
Finished Dec 20 12:42:45 PM PST 23
Peak memory 216456 kb
Host smart-d9c47641-a0a2-43e1-8cf9-92d711df3680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096963506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.1096963506
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.498947136
Short name T17
Test name
Test status
Simulation time 139996843 ps
CPU time 0.76 seconds
Started Dec 20 12:41:43 PM PST 23
Finished Dec 20 12:42:47 PM PST 23
Peak memory 199232 kb
Host smart-f9ba9b17-d6b4-4cbb-bb46-b3e7442f6559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498947136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.498947136
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.4183238675
Short name T30
Test name
Test status
Simulation time 1830177002 ps
CPU time 6.74 seconds
Started Dec 20 12:41:41 PM PST 23
Finished Dec 20 12:42:51 PM PST 23
Peak memory 199588 kb
Host smart-36435436-0773-44a4-9310-82301ee21a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183238675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.4183238675
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.2753334160
Short name T534
Test name
Test status
Simulation time 142664280 ps
CPU time 1.13 seconds
Started Dec 20 12:41:33 PM PST 23
Finished Dec 20 12:42:37 PM PST 23
Peak memory 199288 kb
Host smart-2a610a66-bab7-4d97-925b-c47d2e67c17e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753334160 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.2753334160
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.1309020870
Short name T323
Test name
Test status
Simulation time 204784269 ps
CPU time 1.3 seconds
Started Dec 20 12:41:36 PM PST 23
Finished Dec 20 12:42:40 PM PST 23
Peak memory 199568 kb
Host smart-c3d016b8-b61b-467f-9d74-8bbe5df8ef3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309020870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.1309020870
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.2773875690
Short name T505
Test name
Test status
Simulation time 732904319 ps
CPU time 3.38 seconds
Started Dec 20 12:41:24 PM PST 23
Finished Dec 20 12:42:32 PM PST 23
Peak memory 199464 kb
Host smart-a221dba3-e675-4e35-a7f9-0d1c3b3f59c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773875690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.2773875690
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.4285600165
Short name T399
Test name
Test status
Simulation time 145399240 ps
CPU time 1.77 seconds
Started Dec 20 12:41:37 PM PST 23
Finished Dec 20 12:42:42 PM PST 23
Peak memory 199464 kb
Host smart-475ce074-05f0-4549-b836-fb69786dc9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285600165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.4285600165
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.733049205
Short name T395
Test name
Test status
Simulation time 72288762 ps
CPU time 0.73 seconds
Started Dec 20 12:41:30 PM PST 23
Finished Dec 20 12:42:34 PM PST 23
Peak memory 199408 kb
Host smart-41d8544e-f54f-475d-8663-b660ddb3222a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733049205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.733049205
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.1852284281
Short name T161
Test name
Test status
Simulation time 68197974 ps
CPU time 0.73 seconds
Started Dec 20 12:41:36 PM PST 23
Finished Dec 20 12:42:39 PM PST 23
Peak memory 199224 kb
Host smart-72ffb9d9-49cb-4146-ba20-5015ff65520f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852284281 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.1852284281
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.3504518065
Short name T40
Test name
Test status
Simulation time 1227799992 ps
CPU time 5.35 seconds
Started Dec 20 12:41:32 PM PST 23
Finished Dec 20 12:42:40 PM PST 23
Peak memory 221320 kb
Host smart-0ad10113-d4c1-4b9a-aae1-e4e58b3b8ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504518065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.3504518065
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.2656843822
Short name T454
Test name
Test status
Simulation time 244735515 ps
CPU time 1.01 seconds
Started Dec 20 12:41:33 PM PST 23
Finished Dec 20 12:42:38 PM PST 23
Peak memory 216572 kb
Host smart-4ace4afd-50c9-487e-8da0-45eed18dfe03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656843822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.2656843822
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.1852597493
Short name T366
Test name
Test status
Simulation time 148863340 ps
CPU time 0.78 seconds
Started Dec 20 12:41:35 PM PST 23
Finished Dec 20 12:42:40 PM PST 23
Peak memory 199116 kb
Host smart-0ddf1324-a72c-4f57-9f18-3c8ea65ff370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852597493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.1852597493
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.24600866
Short name T581
Test name
Test status
Simulation time 1837542474 ps
CPU time 6.26 seconds
Started Dec 20 12:41:39 PM PST 23
Finished Dec 20 12:42:48 PM PST 23
Peak memory 199524 kb
Host smart-443d2bbf-776a-41d8-829c-28b6cc315b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24600866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.24600866
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.2991676842
Short name T462
Test name
Test status
Simulation time 106688318 ps
CPU time 0.96 seconds
Started Dec 20 12:41:40 PM PST 23
Finished Dec 20 12:42:45 PM PST 23
Peak memory 199460 kb
Host smart-39e1db24-901b-4fec-848c-e9c0c0ae90c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991676842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.2991676842
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.2690581921
Short name T29
Test name
Test status
Simulation time 193318451 ps
CPU time 1.37 seconds
Started Dec 20 12:41:30 PM PST 23
Finished Dec 20 12:42:34 PM PST 23
Peak memory 199540 kb
Host smart-5c1fd74c-c07c-43f4-a8d9-096bb486d441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690581921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.2690581921
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.2595816869
Short name T276
Test name
Test status
Simulation time 7478089707 ps
CPU time 26.68 seconds
Started Dec 20 12:41:34 PM PST 23
Finished Dec 20 12:43:06 PM PST 23
Peak memory 199740 kb
Host smart-614388f9-4a5a-4be9-816e-556a37817ea3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595816869 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.2595816869
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.4266283521
Short name T285
Test name
Test status
Simulation time 144819480 ps
CPU time 1.66 seconds
Started Dec 20 12:41:34 PM PST 23
Finished Dec 20 12:42:41 PM PST 23
Peak memory 199336 kb
Host smart-f0c771bc-3b0f-4c57-a1f4-4c379562716d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266283521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.4266283521
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.441517852
Short name T445
Test name
Test status
Simulation time 117032917 ps
CPU time 0.95 seconds
Started Dec 20 12:41:29 PM PST 23
Finished Dec 20 12:42:33 PM PST 23
Peak memory 199488 kb
Host smart-c1790c3e-293b-4807-9016-8afefb2bb583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441517852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.441517852
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.1440990221
Short name T579
Test name
Test status
Simulation time 72952105 ps
CPU time 0.72 seconds
Started Dec 20 12:41:54 PM PST 23
Finished Dec 20 12:42:55 PM PST 23
Peak memory 199192 kb
Host smart-e13d9f60-87b0-4435-8852-c91c178cd92f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440990221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.1440990221
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.4280309426
Short name T53
Test name
Test status
Simulation time 2345629653 ps
CPU time 7.45 seconds
Started Dec 20 12:41:35 PM PST 23
Finished Dec 20 12:42:46 PM PST 23
Peak memory 217400 kb
Host smart-d538bf02-3aab-4442-99bc-f8af380b6aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280309426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.4280309426
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.398731738
Short name T613
Test name
Test status
Simulation time 245411830 ps
CPU time 1.03 seconds
Started Dec 20 12:41:35 PM PST 23
Finished Dec 20 12:42:40 PM PST 23
Peak memory 216452 kb
Host smart-1c1c1fe1-c9bb-4234-8599-3155212022d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398731738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.398731738
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.2195768384
Short name T401
Test name
Test status
Simulation time 204191255 ps
CPU time 0.85 seconds
Started Dec 20 12:41:32 PM PST 23
Finished Dec 20 12:42:38 PM PST 23
Peak memory 199284 kb
Host smart-747ce796-749b-4895-a5be-17bf92b75ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195768384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.2195768384
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.1104589425
Short name T452
Test name
Test status
Simulation time 2042758829 ps
CPU time 6.87 seconds
Started Dec 20 12:41:38 PM PST 23
Finished Dec 20 12:42:47 PM PST 23
Peak memory 199596 kb
Host smart-e84807d4-cad5-4fad-9f58-485e3873c51c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104589425 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.1104589425
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.3273549694
Short name T507
Test name
Test status
Simulation time 144489663 ps
CPU time 1.01 seconds
Started Dec 20 12:41:52 PM PST 23
Finished Dec 20 12:42:54 PM PST 23
Peak memory 199204 kb
Host smart-dd85a2f8-8a05-4730-b169-26ebf8ba7f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273549694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.3273549694
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.256828502
Short name T538
Test name
Test status
Simulation time 128456545 ps
CPU time 1.08 seconds
Started Dec 20 12:41:32 PM PST 23
Finished Dec 20 12:42:38 PM PST 23
Peak memory 199352 kb
Host smart-e519fb90-df97-4c1b-a5f9-8b7eba532116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256828502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.256828502
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.507467940
Short name T595
Test name
Test status
Simulation time 14556442325 ps
CPU time 54.07 seconds
Started Dec 20 12:41:34 PM PST 23
Finished Dec 20 12:43:33 PM PST 23
Peak memory 199684 kb
Host smart-0fedf773-428a-4606-a34d-46272e902743
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507467940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.507467940
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.542759426
Short name T145
Test name
Test status
Simulation time 298867586 ps
CPU time 1.77 seconds
Started Dec 20 12:41:32 PM PST 23
Finished Dec 20 12:42:39 PM PST 23
Peak memory 199112 kb
Host smart-c65a511c-97a1-463e-896f-26d22a4c52b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542759426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.542759426
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.858215034
Short name T4
Test name
Test status
Simulation time 84741704 ps
CPU time 0.82 seconds
Started Dec 20 12:41:46 PM PST 23
Finished Dec 20 12:42:50 PM PST 23
Peak memory 199412 kb
Host smart-931926ac-6f35-456b-810d-e254fb99ea26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858215034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.858215034
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.1606831479
Short name T256
Test name
Test status
Simulation time 64564345 ps
CPU time 0.69 seconds
Started Dec 20 12:41:40 PM PST 23
Finished Dec 20 12:42:43 PM PST 23
Peak memory 199080 kb
Host smart-c93cb34a-3fe2-475b-9fbd-527d217ff761
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606831479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.1606831479
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.1846706751
Short name T532
Test name
Test status
Simulation time 1907667477 ps
CPU time 7.48 seconds
Started Dec 20 12:41:33 PM PST 23
Finished Dec 20 12:42:44 PM PST 23
Peak memory 217368 kb
Host smart-78e1924c-3312-431a-b4b1-2b1a486fe0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846706751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.1846706751
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.1522120860
Short name T383
Test name
Test status
Simulation time 244456130 ps
CPU time 1 seconds
Started Dec 20 12:43:52 PM PST 23
Finished Dec 20 12:43:55 PM PST 23
Peak memory 216388 kb
Host smart-c24c93c6-dc04-4c2b-a86b-54e72e7cf370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522120860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.1522120860
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.2033631550
Short name T463
Test name
Test status
Simulation time 206273881 ps
CPU time 0.85 seconds
Started Dec 20 12:41:40 PM PST 23
Finished Dec 20 12:42:45 PM PST 23
Peak memory 199240 kb
Host smart-af493e82-6e15-4609-ac64-f298d1cd239a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033631550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.2033631550
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.2034670522
Short name T539
Test name
Test status
Simulation time 897702002 ps
CPU time 4.17 seconds
Started Dec 20 12:41:35 PM PST 23
Finished Dec 20 12:42:42 PM PST 23
Peak memory 199636 kb
Host smart-ae341166-ddd6-462e-be20-a900aa29c087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034670522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.2034670522
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.47315194
Short name T433
Test name
Test status
Simulation time 103249611 ps
CPU time 0.94 seconds
Started Dec 20 12:43:53 PM PST 23
Finished Dec 20 12:44:07 PM PST 23
Peak memory 199164 kb
Host smart-ddf025ae-6207-46ef-ab05-d77564bc5c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47315194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.47315194
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.930312762
Short name T448
Test name
Test status
Simulation time 205484819 ps
CPU time 1.29 seconds
Started Dec 20 12:41:44 PM PST 23
Finished Dec 20 12:42:49 PM PST 23
Peak memory 199516 kb
Host smart-524866d6-d02e-4d08-bdf7-dcf450bb4b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930312762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.930312762
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.432063512
Short name T560
Test name
Test status
Simulation time 5201494083 ps
CPU time 24.59 seconds
Started Dec 20 12:41:36 PM PST 23
Finished Dec 20 12:43:03 PM PST 23
Peak memory 199696 kb
Host smart-365f8fcf-3425-4856-a2e0-03553eb2ad10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432063512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.432063512
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.1625871285
Short name T250
Test name
Test status
Simulation time 350369696 ps
CPU time 2.05 seconds
Started Dec 20 12:43:48 PM PST 23
Finished Dec 20 12:43:52 PM PST 23
Peak memory 199208 kb
Host smart-11ec7265-8b31-4392-8467-a0b0937c3914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625871285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.1625871285
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.4251301782
Short name T616
Test name
Test status
Simulation time 67537236 ps
CPU time 0.7 seconds
Started Dec 20 12:43:48 PM PST 23
Finished Dec 20 12:43:50 PM PST 23
Peak memory 199180 kb
Host smart-2d2f1e9d-ae81-4bf7-9e8a-93be4a00038e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251301782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.4251301782
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.170328000
Short name T352
Test name
Test status
Simulation time 65188950 ps
CPU time 0.7 seconds
Started Dec 20 12:40:34 PM PST 23
Finished Dec 20 12:41:36 PM PST 23
Peak memory 199248 kb
Host smart-f6dd826b-40a7-4355-b682-a6020d2f3f8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170328000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.170328000
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.313116431
Short name T61
Test name
Test status
Simulation time 1225250487 ps
CPU time 5.3 seconds
Started Dec 20 12:41:05 PM PST 23
Finished Dec 20 12:42:14 PM PST 23
Peak memory 217404 kb
Host smart-85068963-cf39-48d5-89a3-597def9044d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313116431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.313116431
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.1264103513
Short name T516
Test name
Test status
Simulation time 243700756 ps
CPU time 1.12 seconds
Started Dec 20 12:40:22 PM PST 23
Finished Dec 20 12:41:24 PM PST 23
Peak memory 216592 kb
Host smart-ba040f5d-cb6a-45cd-bb55-68fa2b4ef339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264103513 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.1264103513
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.3446605349
Short name T604
Test name
Test status
Simulation time 120578651 ps
CPU time 0.78 seconds
Started Dec 20 12:40:27 PM PST 23
Finished Dec 20 12:41:29 PM PST 23
Peak memory 199264 kb
Host smart-cd15466e-d32f-4b97-8c1f-2c3850c7a9a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446605349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.3446605349
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.3473444418
Short name T362
Test name
Test status
Simulation time 1901721276 ps
CPU time 7.29 seconds
Started Dec 20 12:40:20 PM PST 23
Finished Dec 20 12:41:28 PM PST 23
Peak memory 199552 kb
Host smart-676d449b-9537-4119-aabc-7c3d812e219e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473444418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.3473444418
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.2618244106
Short name T76
Test name
Test status
Simulation time 8319482191 ps
CPU time 12.88 seconds
Started Dec 20 12:40:39 PM PST 23
Finished Dec 20 12:41:54 PM PST 23
Peak memory 216336 kb
Host smart-915296e7-103e-49eb-9d65-684c8dd44f83
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618244106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.2618244106
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.317066065
Short name T43
Test name
Test status
Simulation time 141231839 ps
CPU time 1.11 seconds
Started Dec 20 12:40:28 PM PST 23
Finished Dec 20 12:41:33 PM PST 23
Peak memory 199440 kb
Host smart-0e19e106-60a2-4009-abdb-f09dd3921fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317066065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.317066065
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.758402501
Short name T432
Test name
Test status
Simulation time 198321891 ps
CPU time 1.33 seconds
Started Dec 20 12:40:49 PM PST 23
Finished Dec 20 12:41:55 PM PST 23
Peak memory 199620 kb
Host smart-73c1fb64-2f4a-4255-b100-1d0fdbb28e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758402501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.758402501
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.764833325
Short name T434
Test name
Test status
Simulation time 2571132061 ps
CPU time 12.36 seconds
Started Dec 20 12:40:22 PM PST 23
Finished Dec 20 12:41:35 PM PST 23
Peak memory 199672 kb
Host smart-904befa2-cedc-4f1d-84a6-b927563fd6c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764833325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.764833325
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.2159967700
Short name T56
Test name
Test status
Simulation time 128578962 ps
CPU time 1.51 seconds
Started Dec 20 12:41:48 PM PST 23
Finished Dec 20 12:42:52 PM PST 23
Peak memory 197596 kb
Host smart-6772e17b-f736-4c98-bccd-4c956445203a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159967700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.2159967700
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.3614383129
Short name T8
Test name
Test status
Simulation time 194167179 ps
CPU time 1.17 seconds
Started Dec 20 12:41:05 PM PST 23
Finished Dec 20 12:42:10 PM PST 23
Peak memory 199448 kb
Host smart-28b99ff5-09f5-4ad4-b4c2-22a760bd08d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614383129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.3614383129
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.2916119619
Short name T404
Test name
Test status
Simulation time 68859922 ps
CPU time 0.75 seconds
Started Dec 20 12:41:44 PM PST 23
Finished Dec 20 12:42:48 PM PST 23
Peak memory 199180 kb
Host smart-c3cac457-4cf0-491b-bd52-228b0df41af8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916119619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.2916119619
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.2982719729
Short name T51
Test name
Test status
Simulation time 1887047796 ps
CPU time 7.04 seconds
Started Dec 20 12:41:45 PM PST 23
Finished Dec 20 12:42:55 PM PST 23
Peak memory 217416 kb
Host smart-7dd589dc-8834-4a49-9842-2631442e0ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982719729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.2982719729
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.1328214793
Short name T400
Test name
Test status
Simulation time 243570343 ps
CPU time 1.21 seconds
Started Dec 20 12:43:29 PM PST 23
Finished Dec 20 12:43:33 PM PST 23
Peak memory 214648 kb
Host smart-557cbcf4-763c-4a63-91ad-21a5a9edb1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328214793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.1328214793
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.814998585
Short name T491
Test name
Test status
Simulation time 186863917 ps
CPU time 0.83 seconds
Started Dec 20 12:41:40 PM PST 23
Finished Dec 20 12:42:43 PM PST 23
Peak memory 199072 kb
Host smart-e2e2473c-f78a-4ca1-ad36-a1187eb1323b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814998585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.814998585
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.1256172967
Short name T600
Test name
Test status
Simulation time 1356256400 ps
CPU time 5.06 seconds
Started Dec 20 12:43:29 PM PST 23
Finished Dec 20 12:43:37 PM PST 23
Peak memory 197296 kb
Host smart-1f23522d-82af-466b-9400-82686c9c198d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256172967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.1256172967
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.451368540
Short name T469
Test name
Test status
Simulation time 157906967 ps
CPU time 1.06 seconds
Started Dec 20 12:41:48 PM PST 23
Finished Dec 20 12:42:51 PM PST 23
Peak memory 199260 kb
Host smart-1a007635-61b1-4534-ae71-4702c1096c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451368540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.451368540
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.2641332656
Short name T78
Test name
Test status
Simulation time 121617628 ps
CPU time 1.18 seconds
Started Dec 20 12:41:40 PM PST 23
Finished Dec 20 12:42:43 PM PST 23
Peak memory 199576 kb
Host smart-87454359-752d-4401-8532-f0f4edd68175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641332656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.2641332656
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.2208041753
Short name T12
Test name
Test status
Simulation time 4545724461 ps
CPU time 18.73 seconds
Started Dec 20 12:41:44 PM PST 23
Finished Dec 20 12:43:06 PM PST 23
Peak memory 199580 kb
Host smart-432353ee-b2e3-4bf6-b481-d71763a6dc46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208041753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.2208041753
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.2762526316
Short name T301
Test name
Test status
Simulation time 370666984 ps
CPU time 2.02 seconds
Started Dec 20 12:41:42 PM PST 23
Finished Dec 20 12:42:47 PM PST 23
Peak memory 199388 kb
Host smart-2487e7d0-e899-43c1-871c-33040218f6cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762526316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.2762526316
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.1629397999
Short name T378
Test name
Test status
Simulation time 131457817 ps
CPU time 0.94 seconds
Started Dec 20 12:41:34 PM PST 23
Finished Dec 20 12:42:39 PM PST 23
Peak memory 199388 kb
Host smart-8717a627-0b2e-47f0-8f43-fba060f39975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629397999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.1629397999
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.3463162936
Short name T540
Test name
Test status
Simulation time 68456643 ps
CPU time 0.71 seconds
Started Dec 20 12:41:39 PM PST 23
Finished Dec 20 12:42:43 PM PST 23
Peak memory 199252 kb
Host smart-33d345ae-83b3-40ac-81d5-e1e09f6e34f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463162936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.3463162936
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.2263470612
Short name T453
Test name
Test status
Simulation time 2352634612 ps
CPU time 8.03 seconds
Started Dec 20 12:41:34 PM PST 23
Finished Dec 20 12:42:47 PM PST 23
Peak memory 217528 kb
Host smart-26de68c6-fa52-4fe9-b153-ea860a52831e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263470612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.2263470612
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.3442281360
Short name T577
Test name
Test status
Simulation time 243440208 ps
CPU time 1.02 seconds
Started Dec 20 12:41:49 PM PST 23
Finished Dec 20 12:42:54 PM PST 23
Peak memory 216440 kb
Host smart-a8c9f657-a727-49f1-90dd-4c458b558eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442281360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.3442281360
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.1236046539
Short name T304
Test name
Test status
Simulation time 154493117 ps
CPU time 0.77 seconds
Started Dec 20 12:41:35 PM PST 23
Finished Dec 20 12:42:39 PM PST 23
Peak memory 199256 kb
Host smart-1eaa8739-d2f1-4b4a-a81d-126c8fefb156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236046539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.1236046539
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.4019441213
Short name T509
Test name
Test status
Simulation time 1766502245 ps
CPU time 6.28 seconds
Started Dec 20 12:43:29 PM PST 23
Finished Dec 20 12:43:38 PM PST 23
Peak memory 197792 kb
Host smart-feceedd0-6fd0-4b52-9f47-4b1aca97455b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019441213 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.4019441213
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.128652936
Short name T146
Test name
Test status
Simulation time 102775264 ps
CPU time 0.96 seconds
Started Dec 20 12:41:40 PM PST 23
Finished Dec 20 12:42:45 PM PST 23
Peak memory 199440 kb
Host smart-ee140359-d3e7-4d0a-a12a-8d08bfce60f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128652936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.128652936
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.3390431378
Short name T45
Test name
Test status
Simulation time 108191573 ps
CPU time 1.07 seconds
Started Dec 20 12:43:51 PM PST 23
Finished Dec 20 12:43:54 PM PST 23
Peak memory 199340 kb
Host smart-82ad9f8f-881e-4f6b-85d9-4b38de96c227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390431378 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.3390431378
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.1650614224
Short name T439
Test name
Test status
Simulation time 6503788352 ps
CPU time 25.82 seconds
Started Dec 20 12:41:39 PM PST 23
Finished Dec 20 12:43:09 PM PST 23
Peak memory 199672 kb
Host smart-b4191468-ffb4-4f42-8b60-9714244f2529
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650614224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.1650614224
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.3236915865
Short name T253
Test name
Test status
Simulation time 363817013 ps
CPU time 2.14 seconds
Started Dec 20 12:41:45 PM PST 23
Finished Dec 20 12:42:50 PM PST 23
Peak memory 199268 kb
Host smart-3a6294e5-dced-415d-acaa-906664ea0419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236915865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.3236915865
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.3552973144
Short name T340
Test name
Test status
Simulation time 226991407 ps
CPU time 1.3 seconds
Started Dec 20 12:41:46 PM PST 23
Finished Dec 20 12:42:50 PM PST 23
Peak memory 199444 kb
Host smart-ee2196cf-494c-44cb-a0d7-8d7a79bfbb1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552973144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.3552973144
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.3796509633
Short name T48
Test name
Test status
Simulation time 66819355 ps
CPU time 0.76 seconds
Started Dec 20 12:41:34 PM PST 23
Finished Dec 20 12:42:40 PM PST 23
Peak memory 199232 kb
Host smart-0a8bfb2a-d772-4122-9839-121df50cf56f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796509633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.3796509633
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.245254846
Short name T599
Test name
Test status
Simulation time 2367174767 ps
CPU time 7.77 seconds
Started Dec 20 12:41:42 PM PST 23
Finished Dec 20 12:42:55 PM PST 23
Peak memory 216164 kb
Host smart-9586906d-f04b-4727-96ca-40ea3b6c5dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245254846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.245254846
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.1382077575
Short name T85
Test name
Test status
Simulation time 244332731 ps
CPU time 0.99 seconds
Started Dec 20 12:41:37 PM PST 23
Finished Dec 20 12:42:43 PM PST 23
Peak memory 216680 kb
Host smart-c8014cd0-1102-4b4a-aa30-7dbd7aac8d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382077575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.1382077575
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.3217803318
Short name T608
Test name
Test status
Simulation time 149534732 ps
CPU time 0.92 seconds
Started Dec 20 12:41:37 PM PST 23
Finished Dec 20 12:42:41 PM PST 23
Peak memory 199180 kb
Host smart-18d0e78a-6abd-4374-9272-945b5e20f9f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217803318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.3217803318
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.456323847
Short name T284
Test name
Test status
Simulation time 814377226 ps
CPU time 4.39 seconds
Started Dec 20 12:41:37 PM PST 23
Finished Dec 20 12:42:45 PM PST 23
Peak memory 199556 kb
Host smart-f00c1dd8-7431-464b-97be-6a81a2a54f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456323847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.456323847
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.3897649090
Short name T575
Test name
Test status
Simulation time 108489939 ps
CPU time 0.95 seconds
Started Dec 20 12:41:36 PM PST 23
Finished Dec 20 12:42:40 PM PST 23
Peak memory 199420 kb
Host smart-aad7212d-10a0-47d6-a8e9-121cfa0e5b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897649090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.3897649090
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.3404677308
Short name T373
Test name
Test status
Simulation time 197083018 ps
CPU time 1.35 seconds
Started Dec 20 12:41:39 PM PST 23
Finished Dec 20 12:42:43 PM PST 23
Peak memory 199348 kb
Host smart-845efc5e-e9ca-426b-bfe1-6d4a3a04a242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404677308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.3404677308
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.3535941880
Short name T584
Test name
Test status
Simulation time 15679656607 ps
CPU time 50.21 seconds
Started Dec 20 12:41:38 PM PST 23
Finished Dec 20 12:43:30 PM PST 23
Peak memory 199668 kb
Host smart-62089b9c-c3ff-4881-8c3d-ae603ed8d485
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535941880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.3535941880
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.1818926037
Short name T279
Test name
Test status
Simulation time 522406774 ps
CPU time 2.85 seconds
Started Dec 20 12:41:40 PM PST 23
Finished Dec 20 12:42:46 PM PST 23
Peak memory 199284 kb
Host smart-5d47e331-908f-4430-9d6c-9cc9d9501e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818926037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.1818926037
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.3588004680
Short name T358
Test name
Test status
Simulation time 185280657 ps
CPU time 1.14 seconds
Started Dec 20 12:41:33 PM PST 23
Finished Dec 20 12:42:37 PM PST 23
Peak memory 199476 kb
Host smart-47c8278c-839a-490d-85d4-4ac4802c8401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588004680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.3588004680
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.1927902273
Short name T601
Test name
Test status
Simulation time 70702473 ps
CPU time 0.7 seconds
Started Dec 20 12:41:39 PM PST 23
Finished Dec 20 12:42:43 PM PST 23
Peak memory 199352 kb
Host smart-1059fc65-7631-4ffa-be8f-26dba01531ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927902273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.1927902273
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.1326797132
Short name T569
Test name
Test status
Simulation time 2189001461 ps
CPU time 7.1 seconds
Started Dec 20 12:41:39 PM PST 23
Finished Dec 20 12:42:49 PM PST 23
Peak memory 216560 kb
Host smart-9e286c8d-eaaa-4c08-b9f7-0f44eb4c703a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326797132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.1326797132
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.393214757
Short name T594
Test name
Test status
Simulation time 244162769 ps
CPU time 1.09 seconds
Started Dec 20 12:41:36 PM PST 23
Finished Dec 20 12:42:40 PM PST 23
Peak memory 216832 kb
Host smart-8bfa4a1e-dc79-44b8-b8f1-1e4d63a06266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393214757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.393214757
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.847228130
Short name T361
Test name
Test status
Simulation time 122165528 ps
CPU time 0.73 seconds
Started Dec 20 12:41:38 PM PST 23
Finished Dec 20 12:42:42 PM PST 23
Peak memory 199024 kb
Host smart-33d7a6a0-4c1b-4e4e-97d9-5706bf548e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847228130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.847228130
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.1073302284
Short name T545
Test name
Test status
Simulation time 1744380122 ps
CPU time 5.54 seconds
Started Dec 20 12:41:33 PM PST 23
Finished Dec 20 12:42:42 PM PST 23
Peak memory 199564 kb
Host smart-8ddb8878-c89b-4c3b-98bf-9df6c6dbbdfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073302284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.1073302284
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.154106776
Short name T155
Test name
Test status
Simulation time 177316144 ps
CPU time 1.08 seconds
Started Dec 20 12:41:57 PM PST 23
Finished Dec 20 12:42:58 PM PST 23
Peak memory 199204 kb
Host smart-218d2d85-acb9-4a49-8012-046c1953609a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154106776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.154106776
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.2689551356
Short name T317
Test name
Test status
Simulation time 113824166 ps
CPU time 1.09 seconds
Started Dec 20 12:41:49 PM PST 23
Finished Dec 20 12:42:54 PM PST 23
Peak memory 199588 kb
Host smart-453b7ac2-3b0b-42c3-86a3-8f052bdbc362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689551356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.2689551356
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.126029863
Short name T502
Test name
Test status
Simulation time 5774410241 ps
CPU time 24.2 seconds
Started Dec 20 12:41:43 PM PST 23
Finished Dec 20 12:43:09 PM PST 23
Peak memory 199720 kb
Host smart-814119b6-00ed-4476-95e6-40fd7f9a6ee7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126029863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.126029863
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.600685193
Short name T163
Test name
Test status
Simulation time 112740325 ps
CPU time 1.39 seconds
Started Dec 20 12:41:42 PM PST 23
Finished Dec 20 12:42:47 PM PST 23
Peak memory 199420 kb
Host smart-6384721b-77eb-48cf-aaf7-351cee3d2879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600685193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.600685193
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.3680082102
Short name T133
Test name
Test status
Simulation time 143153619 ps
CPU time 1.09 seconds
Started Dec 20 12:41:33 PM PST 23
Finished Dec 20 12:42:37 PM PST 23
Peak memory 199424 kb
Host smart-6c11a041-44d1-4ea5-85c8-c37d88a07cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680082102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.3680082102
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.3243899221
Short name T321
Test name
Test status
Simulation time 71192597 ps
CPU time 0.77 seconds
Started Dec 20 12:41:49 PM PST 23
Finished Dec 20 12:42:52 PM PST 23
Peak memory 199332 kb
Host smart-895774bd-e117-418f-97aa-05f71bdfa5b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243899221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.3243899221
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.1530744919
Short name T390
Test name
Test status
Simulation time 1231657010 ps
CPU time 5.28 seconds
Started Dec 20 12:41:35 PM PST 23
Finished Dec 20 12:42:44 PM PST 23
Peak memory 217424 kb
Host smart-6ddc8395-6cf2-46d7-b428-69cdc8cbe892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530744919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.1530744919
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.2789381683
Short name T167
Test name
Test status
Simulation time 243534812 ps
CPU time 1.11 seconds
Started Dec 20 12:41:35 PM PST 23
Finished Dec 20 12:42:39 PM PST 23
Peak memory 216648 kb
Host smart-fb6c737f-04f9-45db-b730-2dbae7ae99f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789381683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.2789381683
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.1751324807
Short name T478
Test name
Test status
Simulation time 151818420 ps
CPU time 0.89 seconds
Started Dec 20 12:43:27 PM PST 23
Finished Dec 20 12:43:31 PM PST 23
Peak memory 197036 kb
Host smart-ec139a00-c455-4e05-9b76-2020c62c910d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751324807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.1751324807
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.126049469
Short name T384
Test name
Test status
Simulation time 1596877210 ps
CPU time 5.96 seconds
Started Dec 20 12:41:35 PM PST 23
Finished Dec 20 12:42:44 PM PST 23
Peak memory 199672 kb
Host smart-f8e48a22-85b0-4a19-880c-5a5e860e9d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126049469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.126049469
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.2587682080
Short name T265
Test name
Test status
Simulation time 109485245 ps
CPU time 0.97 seconds
Started Dec 20 12:41:37 PM PST 23
Finished Dec 20 12:42:43 PM PST 23
Peak memory 199520 kb
Host smart-1a71c3c3-ece3-41f5-88d9-35cd1bbc8392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587682080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.2587682080
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.2800250184
Short name T426
Test name
Test status
Simulation time 114704909 ps
CPU time 1.13 seconds
Started Dec 20 12:41:39 PM PST 23
Finished Dec 20 12:42:44 PM PST 23
Peak memory 199660 kb
Host smart-5658651d-b98c-4048-ac6d-cd70dc8044a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800250184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.2800250184
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.1066406910
Short name T103
Test name
Test status
Simulation time 6547200490 ps
CPU time 27.76 seconds
Started Dec 20 12:41:36 PM PST 23
Finished Dec 20 12:43:06 PM PST 23
Peak memory 199696 kb
Host smart-3e3f978a-2dd2-4e7a-9f74-7d997c05a91a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066406910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.1066406910
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.1472591550
Short name T451
Test name
Test status
Simulation time 126033290 ps
CPU time 1.47 seconds
Started Dec 20 12:41:41 PM PST 23
Finished Dec 20 12:42:48 PM PST 23
Peak memory 199408 kb
Host smart-fb9fee23-a850-4121-bf4a-ceadd860c843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472591550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.1472591550
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.3579200775
Short name T334
Test name
Test status
Simulation time 71357039 ps
CPU time 0.73 seconds
Started Dec 20 12:41:41 PM PST 23
Finished Dec 20 12:42:47 PM PST 23
Peak memory 199528 kb
Host smart-1d025cb2-ef7c-404c-ad3e-067c6beefd20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579200775 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.3579200775
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.130172788
Short name T290
Test name
Test status
Simulation time 71783536 ps
CPU time 0.71 seconds
Started Dec 20 12:41:43 PM PST 23
Finished Dec 20 12:42:46 PM PST 23
Peak memory 199252 kb
Host smart-f3f7cf43-37fe-48e4-8ccd-009a9cb93521
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130172788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.130172788
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.699533926
Short name T556
Test name
Test status
Simulation time 1904838591 ps
CPU time 6.85 seconds
Started Dec 20 12:43:48 PM PST 23
Finished Dec 20 12:43:56 PM PST 23
Peak memory 217132 kb
Host smart-d811dbda-b014-46df-adb5-92c524809f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699533926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.699533926
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.2982954886
Short name T70
Test name
Test status
Simulation time 244708440 ps
CPU time 1.04 seconds
Started Dec 20 12:41:45 PM PST 23
Finished Dec 20 12:42:48 PM PST 23
Peak memory 216664 kb
Host smart-9311ee8b-9eb6-4d8a-9853-2c03ef6c8d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982954886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.2982954886
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.944144029
Short name T409
Test name
Test status
Simulation time 164902136 ps
CPU time 0.84 seconds
Started Dec 20 12:41:44 PM PST 23
Finished Dec 20 12:42:48 PM PST 23
Peak memory 199204 kb
Host smart-b372de7f-bcd2-4304-9cfe-e6818bc7f07c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944144029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.944144029
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.2315618865
Short name T443
Test name
Test status
Simulation time 1067948880 ps
CPU time 4.97 seconds
Started Dec 20 12:41:40 PM PST 23
Finished Dec 20 12:42:47 PM PST 23
Peak memory 199600 kb
Host smart-c03bf33a-d0e9-401d-8c41-b5c136d89ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315618865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.2315618865
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.1101030460
Short name T314
Test name
Test status
Simulation time 175706764 ps
CPU time 1.1 seconds
Started Dec 20 12:41:40 PM PST 23
Finished Dec 20 12:42:43 PM PST 23
Peak memory 199436 kb
Host smart-4fdc97d2-ae73-4c3e-9c54-6a35336cb181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101030460 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.1101030460
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.1835156967
Short name T293
Test name
Test status
Simulation time 256245428 ps
CPU time 1.47 seconds
Started Dec 20 12:41:55 PM PST 23
Finished Dec 20 12:42:57 PM PST 23
Peak memory 199556 kb
Host smart-0d56bb1c-cf3e-495c-a976-6e8949c74297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835156967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.1835156967
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.3658765640
Short name T615
Test name
Test status
Simulation time 5531232001 ps
CPU time 22.87 seconds
Started Dec 20 12:41:36 PM PST 23
Finished Dec 20 12:43:02 PM PST 23
Peak memory 199744 kb
Host smart-b1943c5c-39dc-4174-b946-ca45caf74469
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658765640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.3658765640
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.2399226157
Short name T149
Test name
Test status
Simulation time 114541220 ps
CPU time 1.4 seconds
Started Dec 20 12:41:34 PM PST 23
Finished Dec 20 12:42:40 PM PST 23
Peak memory 199556 kb
Host smart-8142aa0a-73dc-48d4-9edd-51bf2300dafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399226157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.2399226157
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.2213694900
Short name T493
Test name
Test status
Simulation time 195322340 ps
CPU time 1.35 seconds
Started Dec 20 12:41:46 PM PST 23
Finished Dec 20 12:42:50 PM PST 23
Peak memory 199440 kb
Host smart-61eed5ea-6f0d-487e-be3c-99b7fdd42ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213694900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.2213694900
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.4055492133
Short name T582
Test name
Test status
Simulation time 80486312 ps
CPU time 0.76 seconds
Started Dec 20 12:41:37 PM PST 23
Finished Dec 20 12:42:43 PM PST 23
Peak memory 199048 kb
Host smart-66f63593-7087-4938-bad9-8807e442198f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055492133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.4055492133
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.3958986888
Short name T442
Test name
Test status
Simulation time 1223549003 ps
CPU time 5.4 seconds
Started Dec 20 12:43:27 PM PST 23
Finished Dec 20 12:43:36 PM PST 23
Peak memory 214812 kb
Host smart-4d2069b7-026b-409a-ba76-e16cf4bf04dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958986888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.3958986888
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.327831834
Short name T504
Test name
Test status
Simulation time 244822559 ps
CPU time 1 seconds
Started Dec 20 12:41:37 PM PST 23
Finished Dec 20 12:42:42 PM PST 23
Peak memory 216744 kb
Host smart-4b0b1d7f-0be1-4321-8fd8-4966d5815596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327831834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.327831834
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.633965847
Short name T309
Test name
Test status
Simulation time 83244040 ps
CPU time 0.7 seconds
Started Dec 20 12:41:36 PM PST 23
Finished Dec 20 12:42:39 PM PST 23
Peak memory 199288 kb
Host smart-dd65ecf1-8b4b-4f91-ad8b-66ca9ce5d70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633965847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.633965847
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.1422625976
Short name T280
Test name
Test status
Simulation time 1644753646 ps
CPU time 6.49 seconds
Started Dec 20 12:41:39 PM PST 23
Finished Dec 20 12:42:49 PM PST 23
Peak memory 199580 kb
Host smart-bdb58d6d-0fd1-462e-a7aa-2ac8178558a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422625976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.1422625976
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.566766289
Short name T480
Test name
Test status
Simulation time 107528346 ps
CPU time 0.96 seconds
Started Dec 20 12:41:35 PM PST 23
Finished Dec 20 12:42:39 PM PST 23
Peak memory 199440 kb
Host smart-f8431c98-4b1d-4649-9246-5a2a7794aaa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566766289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.566766289
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.2269948199
Short name T484
Test name
Test status
Simulation time 193909179 ps
CPU time 1.32 seconds
Started Dec 20 12:41:40 PM PST 23
Finished Dec 20 12:42:44 PM PST 23
Peak memory 199340 kb
Host smart-99bce526-6044-4b15-9f38-b15495895fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269948199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.2269948199
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.2459431749
Short name T258
Test name
Test status
Simulation time 3816279161 ps
CPU time 16.92 seconds
Started Dec 20 12:41:42 PM PST 23
Finished Dec 20 12:43:02 PM PST 23
Peak memory 199648 kb
Host smart-dbea6637-92dc-4364-893a-06700ef83a80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459431749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.2459431749
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.2127500325
Short name T83
Test name
Test status
Simulation time 112701706 ps
CPU time 1.38 seconds
Started Dec 20 12:41:44 PM PST 23
Finished Dec 20 12:42:48 PM PST 23
Peak memory 199464 kb
Host smart-0bfe81ab-3598-4db2-94e6-e72164397964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127500325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.2127500325
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.4132600843
Short name T311
Test name
Test status
Simulation time 190241200 ps
CPU time 1.15 seconds
Started Dec 20 12:41:35 PM PST 23
Finished Dec 20 12:42:38 PM PST 23
Peak memory 199500 kb
Host smart-359ad8fd-52d5-4dc7-b04a-f6daaa0d573e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132600843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.4132600843
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.1404478212
Short name T578
Test name
Test status
Simulation time 81914636 ps
CPU time 0.77 seconds
Started Dec 20 12:41:36 PM PST 23
Finished Dec 20 12:42:40 PM PST 23
Peak memory 199048 kb
Host smart-08e41b73-a354-4e31-b75e-f443d8dcb60e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404478212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.1404478212
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.2207334599
Short name T590
Test name
Test status
Simulation time 1229758667 ps
CPU time 6.26 seconds
Started Dec 20 12:43:27 PM PST 23
Finished Dec 20 12:43:37 PM PST 23
Peak memory 218788 kb
Host smart-66ec35b8-8cae-4482-9718-da0524c6da12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207334599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.2207334599
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.3971886670
Short name T267
Test name
Test status
Simulation time 244109433 ps
CPU time 1.04 seconds
Started Dec 20 12:43:48 PM PST 23
Finished Dec 20 12:43:50 PM PST 23
Peak memory 216460 kb
Host smart-04c4ddf4-4e0a-4f31-bca2-d61a3f369155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971886670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.3971886670
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.1857405932
Short name T18
Test name
Test status
Simulation time 143985345 ps
CPU time 0.85 seconds
Started Dec 20 12:41:36 PM PST 23
Finished Dec 20 12:42:40 PM PST 23
Peak memory 199248 kb
Host smart-430bec6c-ede8-43b5-b73e-9f6c51eaf261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857405932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.1857405932
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.537377926
Short name T413
Test name
Test status
Simulation time 1476216637 ps
CPU time 5.77 seconds
Started Dec 20 12:43:27 PM PST 23
Finished Dec 20 12:43:36 PM PST 23
Peak memory 198364 kb
Host smart-729cafec-714a-4b81-9a47-51a01f21b684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537377926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.537377926
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.1418835194
Short name T382
Test name
Test status
Simulation time 139207464 ps
CPU time 1.05 seconds
Started Dec 20 12:41:37 PM PST 23
Finished Dec 20 12:42:42 PM PST 23
Peak memory 199448 kb
Host smart-75093f2b-268a-4739-915f-7eb128cb63d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418835194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.1418835194
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.1429954981
Short name T588
Test name
Test status
Simulation time 258579287 ps
CPU time 1.41 seconds
Started Dec 20 12:43:28 PM PST 23
Finished Dec 20 12:43:32 PM PST 23
Peak memory 199032 kb
Host smart-f9b720ec-e6f2-4549-8289-b9314ad89433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429954981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.1429954981
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.2165340084
Short name T386
Test name
Test status
Simulation time 5978421329 ps
CPU time 25.3 seconds
Started Dec 20 12:41:37 PM PST 23
Finished Dec 20 12:43:07 PM PST 23
Peak memory 199700 kb
Host smart-43dccb42-060a-48f3-b320-f1900b807ff9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165340084 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.2165340084
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.1404724371
Short name T333
Test name
Test status
Simulation time 129983695 ps
CPU time 1.45 seconds
Started Dec 20 12:41:36 PM PST 23
Finished Dec 20 12:42:40 PM PST 23
Peak memory 199396 kb
Host smart-10894c43-b01f-423f-9370-a2a3f1516e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404724371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.1404724371
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.1751899837
Short name T359
Test name
Test status
Simulation time 90609273 ps
CPU time 0.9 seconds
Started Dec 20 12:43:27 PM PST 23
Finished Dec 20 12:43:31 PM PST 23
Peak memory 198228 kb
Host smart-3d8cd474-5229-426c-97dd-10099820521d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751899837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.1751899837
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.2590286910
Short name T521
Test name
Test status
Simulation time 63606657 ps
CPU time 0.73 seconds
Started Dec 20 12:41:40 PM PST 23
Finished Dec 20 12:42:43 PM PST 23
Peak memory 199084 kb
Host smart-ea3a825d-1786-4211-9995-3588f1a1a203
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590286910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.2590286910
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.665472024
Short name T427
Test name
Test status
Simulation time 1218334324 ps
CPU time 5.69 seconds
Started Dec 20 12:43:53 PM PST 23
Finished Dec 20 12:44:12 PM PST 23
Peak memory 221088 kb
Host smart-ebaddae9-6367-42f1-af31-d2365a39e76a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665472024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.665472024
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.3027933367
Short name T332
Test name
Test status
Simulation time 243785117 ps
CPU time 1.1 seconds
Started Dec 20 12:41:35 PM PST 23
Finished Dec 20 12:42:39 PM PST 23
Peak memory 216440 kb
Host smart-a209ca3f-4a88-4e14-b0f6-4a3fcbcfc675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027933367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.3027933367
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.236242025
Short name T273
Test name
Test status
Simulation time 103572279 ps
CPU time 0.71 seconds
Started Dec 20 12:41:37 PM PST 23
Finished Dec 20 12:42:42 PM PST 23
Peak memory 199244 kb
Host smart-11d2530d-b2cb-4e78-97c1-4b0ee27f5e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236242025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.236242025
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.2497300847
Short name T148
Test name
Test status
Simulation time 1526254831 ps
CPU time 6.4 seconds
Started Dec 20 12:43:48 PM PST 23
Finished Dec 20 12:43:56 PM PST 23
Peak memory 199400 kb
Host smart-e4f08db4-3798-4c33-8916-a820ffe4c1b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497300847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.2497300847
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.2234728388
Short name T168
Test name
Test status
Simulation time 153279852 ps
CPU time 1.05 seconds
Started Dec 20 12:43:52 PM PST 23
Finished Dec 20 12:43:55 PM PST 23
Peak memory 199164 kb
Host smart-d320e23d-56b8-44b7-aaa6-29e86ec923e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234728388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.2234728388
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.1837500253
Short name T541
Test name
Test status
Simulation time 255237077 ps
CPU time 1.46 seconds
Started Dec 20 12:41:37 PM PST 23
Finished Dec 20 12:42:43 PM PST 23
Peak memory 199344 kb
Host smart-6e27e2c5-2b64-45b7-9828-87ae99f2dc3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837500253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.1837500253
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.3599277115
Short name T591
Test name
Test status
Simulation time 4215734392 ps
CPU time 16.69 seconds
Started Dec 20 12:43:52 PM PST 23
Finished Dec 20 12:44:10 PM PST 23
Peak memory 199420 kb
Host smart-d274a625-7ea8-4db0-9c22-f1ed5abc9e79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599277115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.3599277115
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.4271668168
Short name T150
Test name
Test status
Simulation time 330364633 ps
CPU time 2.12 seconds
Started Dec 20 12:41:52 PM PST 23
Finished Dec 20 12:42:55 PM PST 23
Peak memory 199396 kb
Host smart-f5320a29-d6f7-440d-b62c-c9bdb048e07b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271668168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.4271668168
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.2094266543
Short name T1
Test name
Test status
Simulation time 108414525 ps
CPU time 0.9 seconds
Started Dec 20 12:43:53 PM PST 23
Finished Dec 20 12:44:05 PM PST 23
Peak memory 199196 kb
Host smart-afb5da52-823b-447a-8f22-6c2c9ca5a105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094266543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.2094266543
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.3849098420
Short name T262
Test name
Test status
Simulation time 70938266 ps
CPU time 0.75 seconds
Started Dec 20 12:41:45 PM PST 23
Finished Dec 20 12:42:48 PM PST 23
Peak memory 199136 kb
Host smart-614165b2-defa-4293-ac5c-c72c35544971
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849098420 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.3849098420
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.3098690399
Short name T482
Test name
Test status
Simulation time 2390712900 ps
CPU time 8.38 seconds
Started Dec 20 12:41:35 PM PST 23
Finished Dec 20 12:42:46 PM PST 23
Peak memory 221196 kb
Host smart-42d3274c-3271-410e-b02b-1b8accf18031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098690399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.3098690399
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.2651213517
Short name T514
Test name
Test status
Simulation time 244651175 ps
CPU time 1 seconds
Started Dec 20 12:41:45 PM PST 23
Finished Dec 20 12:42:49 PM PST 23
Peak memory 216460 kb
Host smart-04c8054a-d019-436a-bb43-6c447e6cbdd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651213517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.2651213517
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.3782074752
Short name T483
Test name
Test status
Simulation time 208123366 ps
CPU time 0.85 seconds
Started Dec 20 12:41:40 PM PST 23
Finished Dec 20 12:42:43 PM PST 23
Peak memory 199040 kb
Host smart-c27e1b40-f08e-4899-99e9-69e9543fc9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782074752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.3782074752
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.726238058
Short name T125
Test name
Test status
Simulation time 1847913967 ps
CPU time 6.97 seconds
Started Dec 20 12:41:44 PM PST 23
Finished Dec 20 12:42:54 PM PST 23
Peak memory 199508 kb
Host smart-7843c1cb-910c-44f3-bfee-ebe7b8006871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726238058 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.726238058
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.1310216685
Short name T327
Test name
Test status
Simulation time 144533281 ps
CPU time 1.08 seconds
Started Dec 20 12:41:44 PM PST 23
Finished Dec 20 12:42:48 PM PST 23
Peak memory 199368 kb
Host smart-19f21d66-2ddb-45f1-a5d1-8fa28b0d0d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310216685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.1310216685
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.236278148
Short name T162
Test name
Test status
Simulation time 201399641 ps
CPU time 1.27 seconds
Started Dec 20 12:41:40 PM PST 23
Finished Dec 20 12:42:44 PM PST 23
Peak memory 199376 kb
Host smart-ee617a4f-e612-4465-97d8-97156119c5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236278148 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.236278148
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.2959590946
Short name T500
Test name
Test status
Simulation time 16210570655 ps
CPU time 59.39 seconds
Started Dec 20 12:41:42 PM PST 23
Finished Dec 20 12:43:46 PM PST 23
Peak memory 199380 kb
Host smart-c405567f-6631-4e34-90f3-3b10dde2dd2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959590946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.2959590946
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.3521789879
Short name T338
Test name
Test status
Simulation time 148534007 ps
CPU time 1.7 seconds
Started Dec 20 12:41:44 PM PST 23
Finished Dec 20 12:42:50 PM PST 23
Peak memory 199392 kb
Host smart-5f48c1b1-a4c5-49c0-8bc9-bf83dbb1c68f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521789879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.3521789879
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.4080920323
Short name T347
Test name
Test status
Simulation time 174533395 ps
CPU time 1.29 seconds
Started Dec 20 12:43:29 PM PST 23
Finished Dec 20 12:43:33 PM PST 23
Peak memory 197336 kb
Host smart-8ab88407-bded-45c5-8182-2e997efd6558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080920323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.4080920323
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.471916250
Short name T558
Test name
Test status
Simulation time 81896807 ps
CPU time 0.78 seconds
Started Dec 20 12:41:05 PM PST 23
Finished Dec 20 12:42:10 PM PST 23
Peak memory 199172 kb
Host smart-4e92cb9b-fb81-47cd-b57c-edb1a56031b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471916250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.471916250
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.1436889112
Short name T513
Test name
Test status
Simulation time 1228241614 ps
CPU time 5.62 seconds
Started Dec 20 12:40:29 PM PST 23
Finished Dec 20 12:41:38 PM PST 23
Peak memory 220428 kb
Host smart-b681784b-2850-4049-907b-b0833b1b81a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436889112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.1436889112
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.588604108
Short name T542
Test name
Test status
Simulation time 243740627 ps
CPU time 1.03 seconds
Started Dec 20 12:40:22 PM PST 23
Finished Dec 20 12:41:24 PM PST 23
Peak memory 216564 kb
Host smart-7e31ba9f-30e3-4ca5-b424-bd53a227d52d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588604108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.588604108
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.3238383073
Short name T23
Test name
Test status
Simulation time 170190835 ps
CPU time 0.86 seconds
Started Dec 20 12:40:48 PM PST 23
Finished Dec 20 12:41:53 PM PST 23
Peak memory 199264 kb
Host smart-af35d03d-a7bb-4e4c-b57d-c3ff51e7543b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238383073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.3238383073
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.2258127807
Short name T527
Test name
Test status
Simulation time 1661011387 ps
CPU time 6.7 seconds
Started Dec 20 12:40:47 PM PST 23
Finished Dec 20 12:41:58 PM PST 23
Peak memory 199464 kb
Host smart-053f27e0-22dc-42ff-b8ea-4931cc2cecae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258127807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.2258127807
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.3877769699
Short name T467
Test name
Test status
Simulation time 106855131 ps
CPU time 0.95 seconds
Started Dec 20 12:40:22 PM PST 23
Finished Dec 20 12:41:24 PM PST 23
Peak memory 199404 kb
Host smart-c88a4fb4-0468-48c9-b441-e0f222dda23e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877769699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.3877769699
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.4242027751
Short name T310
Test name
Test status
Simulation time 195288252 ps
CPU time 1.32 seconds
Started Dec 20 12:40:22 PM PST 23
Finished Dec 20 12:41:34 PM PST 23
Peak memory 199604 kb
Host smart-9466edf8-3d34-42f1-b0de-900c6f0590ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242027751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.4242027751
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.307223818
Short name T305
Test name
Test status
Simulation time 7450053197 ps
CPU time 24.23 seconds
Started Dec 20 12:40:55 PM PST 23
Finished Dec 20 12:42:24 PM PST 23
Peak memory 199576 kb
Host smart-3940e6d6-cadf-4fee-a46e-b452e1e68d9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307223818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.307223818
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.919640877
Short name T87
Test name
Test status
Simulation time 131282826 ps
CPU time 1.52 seconds
Started Dec 20 12:40:21 PM PST 23
Finished Dec 20 12:41:22 PM PST 23
Peak memory 199468 kb
Host smart-870625ec-8ebb-4e51-9596-530747cea0f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919640877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.919640877
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.2872227251
Short name T375
Test name
Test status
Simulation time 92276025 ps
CPU time 0.77 seconds
Started Dec 20 12:40:37 PM PST 23
Finished Dec 20 12:41:41 PM PST 23
Peak memory 199308 kb
Host smart-41818ad6-0b14-41ba-b6f2-93052ce2dc52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872227251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.2872227251
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.3176789277
Short name T27
Test name
Test status
Simulation time 172242298 ps
CPU time 0.91 seconds
Started Dec 20 12:40:59 PM PST 23
Finished Dec 20 12:42:04 PM PST 23
Peak memory 199240 kb
Host smart-b760b571-0e17-4b9d-aab6-5d0f471f424c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176789277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.3176789277
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.2910817872
Short name T55
Test name
Test status
Simulation time 1217127236 ps
CPU time 5.26 seconds
Started Dec 20 12:40:41 PM PST 23
Finished Dec 20 12:41:49 PM PST 23
Peak memory 217364 kb
Host smart-7abbbbe4-4089-4211-a1c4-a510cb5a2de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910817872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.2910817872
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.2205281837
Short name T377
Test name
Test status
Simulation time 243033733 ps
CPU time 1.09 seconds
Started Dec 20 12:40:47 PM PST 23
Finished Dec 20 12:41:53 PM PST 23
Peak memory 216632 kb
Host smart-8f81450e-f2db-4d64-81bd-fe1f749faa49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205281837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.2205281837
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.1700597870
Short name T376
Test name
Test status
Simulation time 193898502 ps
CPU time 0.82 seconds
Started Dec 20 12:40:50 PM PST 23
Finished Dec 20 12:41:55 PM PST 23
Peak memory 199260 kb
Host smart-aa1a5577-6f27-4053-aaaa-428801bc3e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700597870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.1700597870
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.2883083356
Short name T492
Test name
Test status
Simulation time 1766802818 ps
CPU time 7.25 seconds
Started Dec 20 12:43:22 PM PST 23
Finished Dec 20 12:43:37 PM PST 23
Peak memory 198640 kb
Host smart-7889ef4e-f91d-4e1c-9121-55bb9aa6f6a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883083356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.2883083356
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.2702923784
Short name T472
Test name
Test status
Simulation time 141873458 ps
CPU time 1.09 seconds
Started Dec 20 12:40:53 PM PST 23
Finished Dec 20 12:41:59 PM PST 23
Peak memory 199540 kb
Host smart-47422f1e-4d09-4e78-9b45-5f837948fa95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702923784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.2702923784
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.3181565120
Short name T536
Test name
Test status
Simulation time 227940688 ps
CPU time 1.43 seconds
Started Dec 20 12:40:59 PM PST 23
Finished Dec 20 12:42:05 PM PST 23
Peak memory 199556 kb
Host smart-480d0388-9221-4128-b464-c1f5b3f3fb4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181565120 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.3181565120
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.1936519231
Short name T367
Test name
Test status
Simulation time 2232302488 ps
CPU time 10.13 seconds
Started Dec 20 12:41:05 PM PST 23
Finished Dec 20 12:42:18 PM PST 23
Peak memory 199692 kb
Host smart-7f1892cc-6295-4d15-b26f-88b99258d984
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936519231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.1936519231
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.1710248744
Short name T607
Test name
Test status
Simulation time 149065644 ps
CPU time 1.72 seconds
Started Dec 20 12:40:33 PM PST 23
Finished Dec 20 12:41:37 PM PST 23
Peak memory 199608 kb
Host smart-5cd48068-af80-4c5a-9a0d-c42f181eb385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710248744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.1710248744
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.4104967786
Short name T471
Test name
Test status
Simulation time 89203917 ps
CPU time 0.79 seconds
Started Dec 20 12:40:37 PM PST 23
Finished Dec 20 12:41:41 PM PST 23
Peak memory 199352 kb
Host smart-acd19534-0f02-4351-be9e-bdb619d8ff0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104967786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.4104967786
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.3171845927
Short name T303
Test name
Test status
Simulation time 76120818 ps
CPU time 0.79 seconds
Started Dec 20 12:40:51 PM PST 23
Finished Dec 20 12:41:55 PM PST 23
Peak memory 199176 kb
Host smart-1b3c85d4-b661-4a52-8828-43eba051f9aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171845927 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.3171845927
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.3203472246
Short name T412
Test name
Test status
Simulation time 1222490645 ps
CPU time 5.93 seconds
Started Dec 20 12:40:38 PM PST 23
Finished Dec 20 12:41:46 PM PST 23
Peak memory 221452 kb
Host smart-abca3f34-5b77-43b6-9baa-23b8d726bd74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203472246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.3203472246
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.970753205
Short name T171
Test name
Test status
Simulation time 244566216 ps
CPU time 1 seconds
Started Dec 20 12:40:47 PM PST 23
Finished Dec 20 12:41:53 PM PST 23
Peak memory 216216 kb
Host smart-f27ba2e0-3273-4192-89fa-82b87a3187ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970753205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.970753205
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.3121194620
Short name T411
Test name
Test status
Simulation time 105273848 ps
CPU time 0.73 seconds
Started Dec 20 12:40:35 PM PST 23
Finished Dec 20 12:41:40 PM PST 23
Peak memory 199144 kb
Host smart-f8c0551b-a8b8-4b77-8c6d-1e969978edd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121194620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.3121194620
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.325639700
Short name T57
Test name
Test status
Simulation time 984922150 ps
CPU time 4.65 seconds
Started Dec 20 12:40:43 PM PST 23
Finished Dec 20 12:41:50 PM PST 23
Peak memory 199564 kb
Host smart-f7329c70-fe5f-4d07-82e0-172e383d23cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325639700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.325639700
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.3151849222
Short name T543
Test name
Test status
Simulation time 110498444 ps
CPU time 0.96 seconds
Started Dec 20 12:40:52 PM PST 23
Finished Dec 20 12:41:57 PM PST 23
Peak memory 199540 kb
Host smart-c3e040c2-f930-4140-ab7f-2ed4718a6677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151849222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.3151849222
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.952054687
Short name T392
Test name
Test status
Simulation time 110908030 ps
CPU time 1.06 seconds
Started Dec 20 12:40:57 PM PST 23
Finished Dec 20 12:42:04 PM PST 23
Peak memory 199320 kb
Host smart-83ba765b-1932-43fd-894f-f388f6ef9544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952054687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.952054687
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.3552264444
Short name T487
Test name
Test status
Simulation time 283189911 ps
CPU time 1.51 seconds
Started Dec 20 12:40:52 PM PST 23
Finished Dec 20 12:41:57 PM PST 23
Peak memory 199480 kb
Host smart-28bf883b-243b-4dd3-a551-99acbe61b167
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552264444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.3552264444
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.729093622
Short name T393
Test name
Test status
Simulation time 254407553 ps
CPU time 1.7 seconds
Started Dec 20 12:43:22 PM PST 23
Finished Dec 20 12:43:31 PM PST 23
Peak memory 198868 kb
Host smart-a77ba6dd-0585-4643-957f-e3e00022ffb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729093622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.729093622
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.1695080266
Short name T266
Test name
Test status
Simulation time 180415995 ps
CPU time 1.08 seconds
Started Dec 20 12:40:45 PM PST 23
Finished Dec 20 12:41:49 PM PST 23
Peak memory 199132 kb
Host smart-9c836f18-a74c-4b68-ad61-1c1f96082f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695080266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.1695080266
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.1773941351
Short name T7
Test name
Test status
Simulation time 76981748 ps
CPU time 0.74 seconds
Started Dec 20 12:40:45 PM PST 23
Finished Dec 20 12:41:49 PM PST 23
Peak memory 199308 kb
Host smart-97d00036-f88b-418e-a6ae-2a918b652ab2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773941351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.1773941351
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.1875875864
Short name T430
Test name
Test status
Simulation time 1234459815 ps
CPU time 5.71 seconds
Started Dec 20 12:40:42 PM PST 23
Finished Dec 20 12:41:50 PM PST 23
Peak memory 216776 kb
Host smart-1c7a2c05-8ec7-45fc-afa6-b89583ffce10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875875864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.1875875864
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.3120027333
Short name T147
Test name
Test status
Simulation time 244275516 ps
CPU time 1.02 seconds
Started Dec 20 12:41:05 PM PST 23
Finished Dec 20 12:42:10 PM PST 23
Peak memory 216580 kb
Host smart-71fcf0c2-bb4b-46d7-a04b-c1422bf4725f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120027333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.3120027333
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.2021771051
Short name T563
Test name
Test status
Simulation time 147370319 ps
CPU time 0.76 seconds
Started Dec 20 12:43:23 PM PST 23
Finished Dec 20 12:43:30 PM PST 23
Peak memory 198324 kb
Host smart-ec650cab-43b2-40a5-9442-7a5d2da0dd2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021771051 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.2021771051
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.2985637160
Short name T101
Test name
Test status
Simulation time 1833869294 ps
CPU time 7.21 seconds
Started Dec 20 12:40:46 PM PST 23
Finished Dec 20 12:41:57 PM PST 23
Peak memory 199628 kb
Host smart-521e150f-9b15-4da8-8de8-03ad77905d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985637160 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.2985637160
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.3646021762
Short name T459
Test name
Test status
Simulation time 174231408 ps
CPU time 1.14 seconds
Started Dec 20 12:40:45 PM PST 23
Finished Dec 20 12:41:49 PM PST 23
Peak memory 199432 kb
Host smart-7b24d8bb-e8cd-476a-b03d-fd8e86fab563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646021762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.3646021762
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.1603215655
Short name T341
Test name
Test status
Simulation time 114661913 ps
CPU time 1.13 seconds
Started Dec 20 12:40:45 PM PST 23
Finished Dec 20 12:41:49 PM PST 23
Peak memory 199656 kb
Host smart-426e3399-6bec-447c-8a90-c7e9a8d853c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603215655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.1603215655
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.2417264922
Short name T611
Test name
Test status
Simulation time 3984639640 ps
CPU time 16.43 seconds
Started Dec 20 12:40:53 PM PST 23
Finished Dec 20 12:42:13 PM PST 23
Peak memory 199528 kb
Host smart-31399378-59b7-43b3-a529-4b478c4a26b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417264922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.2417264922
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.1798807487
Short name T319
Test name
Test status
Simulation time 127899938 ps
CPU time 1.48 seconds
Started Dec 20 12:40:55 PM PST 23
Finished Dec 20 12:42:01 PM PST 23
Peak memory 199132 kb
Host smart-88bbbd39-7942-4d84-be9b-e067ea8be031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798807487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.1798807487
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.439439307
Short name T385
Test name
Test status
Simulation time 71037492 ps
CPU time 0.83 seconds
Started Dec 20 12:43:04 PM PST 23
Finished Dec 20 12:43:28 PM PST 23
Peak memory 198400 kb
Host smart-1e9cbae6-9977-4fbb-a47f-f3f0dcb3e18f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439439307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.439439307
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.600406074
Short name T447
Test name
Test status
Simulation time 59702622 ps
CPU time 0.73 seconds
Started Dec 20 12:40:35 PM PST 23
Finished Dec 20 12:41:38 PM PST 23
Peak memory 199288 kb
Host smart-f5d3078d-2be2-470c-a8d2-88e94a616fa6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600406074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.600406074
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.2927868266
Short name T597
Test name
Test status
Simulation time 1229621175 ps
CPU time 5.37 seconds
Started Dec 20 12:40:42 PM PST 23
Finished Dec 20 12:41:51 PM PST 23
Peak memory 221480 kb
Host smart-0be468c8-266d-4bb3-811e-8d13f258b98c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927868266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.2927868266
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.2523663874
Short name T278
Test name
Test status
Simulation time 244661958 ps
CPU time 1.13 seconds
Started Dec 20 12:43:23 PM PST 23
Finished Dec 20 12:43:30 PM PST 23
Peak memory 216216 kb
Host smart-889103ce-fac5-4954-b75e-703d3a914e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523663874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.2523663874
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.855598446
Short name T391
Test name
Test status
Simulation time 205155694 ps
CPU time 0.85 seconds
Started Dec 20 12:41:02 PM PST 23
Finished Dec 20 12:42:06 PM PST 23
Peak memory 199220 kb
Host smart-109ebe76-a307-4d63-b9a5-0c9baf3e9b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855598446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.855598446
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.1862379412
Short name T449
Test name
Test status
Simulation time 873003284 ps
CPU time 4.32 seconds
Started Dec 20 12:41:01 PM PST 23
Finished Dec 20 12:42:09 PM PST 23
Peak memory 199600 kb
Host smart-62850240-6fa3-44fa-890d-e676c849db78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862379412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.1862379412
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.3741276963
Short name T308
Test name
Test status
Simulation time 181911715 ps
CPU time 1.18 seconds
Started Dec 20 12:40:54 PM PST 23
Finished Dec 20 12:42:00 PM PST 23
Peak memory 199484 kb
Host smart-1980fd69-a0f3-416e-991a-9d2263559e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741276963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.3741276963
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.3622326363
Short name T58
Test name
Test status
Simulation time 113733837 ps
CPU time 1.13 seconds
Started Dec 20 12:41:04 PM PST 23
Finished Dec 20 12:42:08 PM PST 23
Peak memory 199616 kb
Host smart-a80c1c63-a459-45e7-b873-a417b9821167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622326363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.3622326363
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.2577466661
Short name T254
Test name
Test status
Simulation time 3154892877 ps
CPU time 14.8 seconds
Started Dec 20 12:40:41 PM PST 23
Finished Dec 20 12:41:58 PM PST 23
Peak memory 199392 kb
Host smart-57e8ea9f-a0c2-4e3a-8abb-0307d8cedb70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577466661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.2577466661
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.1499481848
Short name T420
Test name
Test status
Simulation time 499460304 ps
CPU time 2.61 seconds
Started Dec 20 12:43:22 PM PST 23
Finished Dec 20 12:43:32 PM PST 23
Peak memory 198912 kb
Host smart-6fa04e57-db3f-4b67-ad04-4b233f16352d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499481848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.1499481848
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.1919780602
Short name T298
Test name
Test status
Simulation time 130116359 ps
CPU time 0.92 seconds
Started Dec 20 12:40:55 PM PST 23
Finished Dec 20 12:42:01 PM PST 23
Peak memory 199276 kb
Host smart-3e9508e9-68ee-44a5-8340-415c0a4f6272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919780602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.1919780602
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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