Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8029

1

T4

18

T7

32

T8

13

auto[1]

10979

1

T3

4

T4

83

T7

28

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5873	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6490	1			T1	1		T2	1		T3	2
reset_info_cp[2]	2844	1			T3	1		T4	12		T7	8
reset_info_cp[4]	3843	1			T3	1		T4	21		T7	14
reset_info_cp[8]	108	1			T7	1		T8	1		T12	1
reset_info_cp[16]	109	1			T89	1		T138	1		T96	2
reset_info_cp[32]	110	1			T96	1		T35	1		T42	1
reset_info_cp[64]	123	1			T7	1		T11	1		T12	2
reset_info_cp[128]	128	1			T3	1		T47	1		T49	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3192	1			T4	18		T7	7		T14	10
reset_info_cp[1]	auto[1]	2678	1			T3	1		T4	8		T7	11
reset_info_cp[2]	auto[0]	870	1			T7	3		T14	4		T47	11
reset_info_cp[2]	auto[1]	1974	1			T3	1		T4	12		T7	5
reset_info_cp[4]	auto[0]	1332	1			T7	8		T14	8		T47	14
reset_info_cp[4]	auto[1]	2511	1			T3	1		T4	21		T7	6
reset_info_cp[8]	auto[0]	45	1			T7	1		T8	1		T12	1
reset_info_cp[8]	auto[1]	63	1			T47	2		T35	1		T28	2
reset_info_cp[16]	auto[0]	40	1			T89	1		T96	2		T39	1
reset_info_cp[16]	auto[1]	69	1			T138	1		T25	1		T35	2
reset_info_cp[32]	auto[0]	45	1			T42	1		T58	1		T59	1
reset_info_cp[32]	auto[1]	65	1			T96	1		T35	1		T27	1
reset_info_cp[64]	auto[0]	53	1			T12	2		T14	2		T89	1
reset_info_cp[64]	auto[1]	70	1			T7	1		T11	1		T35	1
reset_info_cp[128]	auto[0]	53	1			T49	1		T53	1		T58	1
reset_info_cp[128]	auto[1]	75	1			T3	1		T47	1		T96	1