Assertions
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Assertions by Category
ASSERTPROPERTIESSEQUENCES
Total733010
Category 0733010


Assertions by Severity
ASSERTPROPERTIESSEQUENCES
Total733010
Severity 0733010


Summary for Assertions
NUMBERPERCENT
Total Number733100.00
Uncovered40.55
Success72999.45
Failure00.00
Incomplete00.00
Without Attempts00.00


Summary for Cover Sequences
NUMBERPERCENT
Total Number10100.00
Uncovered00.00
All Matches10100.00
First Matches10100.00


Detail Report for Assertions

Assertions Uncovered:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorAonEnTracksRstPorAonActive_A 001543402000
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorEnTracksRstPorInactive_A 0050919005000
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoDiv4EnTracksRstPorIoDiv4Active_A 0012220198000
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoEnTracksRstPorIoInactive_A 0048880762000

Assertions Success:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
tb.dut.AlertsKnownO_A 0010787475591170400
tb.dut.FpvSecCmRegWeOnehotCheck_A 00107874758000
tb.dut.ParameterMatch_A 0050550500
tb.dut.PwrKnownO_A 0010787475591170400
tb.dut.ResetsKnownO_A 0010787475591170400
tb.dut.RstEnKnownO_A 0010787475591170400
tb.dut.TlAReadyKnownO_A 0010787475591170400
tb.dut.TlDValidKnownO_A 0010787475591170400
tb.dut.gen_d0_i2c0_assert.FpvSecCmD0I2c0FsmCheck_A 00107874758000
tb.dut.gen_d0_i2c1_assert.FpvSecCmD0I2c1FsmCheck_A 00107874758000
tb.dut.gen_d0_i2c2_assert.FpvSecCmD0I2c2FsmCheck_A 00107874758000
tb.dut.gen_d0_lc_assert.FpvSecCmD0LcFsmCheck_A 00107874758000
tb.dut.gen_d0_lc_io_assert.FpvSecCmD0LcIoFsmCheck_A 00107874758000
tb.dut.gen_d0_lc_io_div2_assert.FpvSecCmD0LcIoDiv2FsmCheck_A 00107874758000
tb.dut.gen_d0_lc_shadowed_assert.FpvSecCmD0LcShadowedFsmCheck_A 00107874758000
tb.dut.gen_d0_lc_usb_assert.FpvSecCmD0LcUsbFsmCheck_A 00107874758000
tb.dut.gen_d0_spi_device_assert.FpvSecCmD0SpiDeviceFsmCheck_A 00107874758000
tb.dut.gen_d0_spi_host0_assert.FpvSecCmD0SpiHost0FsmCheck_A 00107874758000
tb.dut.gen_d0_spi_host1_assert.FpvSecCmD0SpiHost1FsmCheck_A 00107874758000
tb.dut.gen_d0_sys_assert.FpvSecCmD0SysFsmCheck_A 00107874758000
tb.dut.gen_d0_usb_aon_assert.FpvSecCmD0UsbAonFsmCheck_A 00107874758000
tb.dut.gen_d0_usb_assert.FpvSecCmD0UsbFsmCheck_A 00107874758000
tb.dut.gen_daon_lc_aon_assert.FpvSecCmDAonLcAonFsmCheck_A 00107874758000
tb.dut.gen_daon_lc_assert.FpvSecCmDAonLcFsmCheck_A 00107874758000
tb.dut.gen_daon_lc_io_assert.FpvSecCmDAonLcIoFsmCheck_A 00107874758000
tb.dut.gen_daon_lc_io_div2_assert.FpvSecCmDAonLcIoDiv2FsmCheck_A 00107874758000
tb.dut.gen_daon_lc_shadowed_assert.FpvSecCmDAonLcShadowedFsmCheck_A 00107874758000
tb.dut.gen_daon_lc_usb_assert.FpvSecCmDAonLcUsbFsmCheck_A 00107874758000
tb.dut.gen_daon_por_assert.FpvSecCmDAonPorFsmCheck_A 00107874758000
tb.dut.gen_daon_por_io_assert.FpvSecCmDAonPorIoFsmCheck_A 00107874758000
tb.dut.gen_daon_por_io_div2_assert.FpvSecCmDAonPorIoDiv2FsmCheck_A 00107874758000
tb.dut.gen_daon_por_io_div4_assert.FpvSecCmDAonPorIoDiv4FsmCheck_A 00107874758000
tb.dut.gen_daon_por_usb_assert.FpvSecCmDAonPorUsbFsmCheck_A 00107874758000
tb.dut.gen_daon_sys_io_div4_assert.FpvSecCmDAonSysIoDiv4FsmCheck_A 00107874758000
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_prim_mubi4_sender.OutputsKnown_A 00154340289504900
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic.selKnown0 009271876600
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic.selKnown1 002725222000
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic.selKnown0 008848834300
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic.selKnown1 002725222000
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic.selKnown0 007085658000
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic.selKnown1 002725222000
tb.dut.gen_rst_por_aon[0].u_por_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.gen_rst_por_aon[0].u_por_scanmode_sync.OutputsKnown_A 0010787475591170400
tb.dut.gen_rst_por_aon[0].u_por_scanmode_sync.gen_no_flops.OutputDelay_A 0010787475591170400
tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic.selKnown0 008848834300
tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic.selKnown1 002725222000
tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_prim_mubi4_sender.OutputsKnown_A 00154340287643400
tb.dut.gen_rst_por_aon[1].u_por_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.gen_rst_por_aon[1].u_por_scanmode_sync.OutputsKnown_A 0010787475591170400
tb.dut.gen_rst_por_aon[1].u_por_scanmode_sync.gen_no_flops.OutputDelay_A 0010787475591170400
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[0].LcHandshakeOff_A 00107874751283900
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[0].LcHandshakeOn_A 001078747511852300
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[0].SysHandshakeOff_A 0010787475595151300
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[0].SysHandshakeOn_A 001078747518908300
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[1].LcHandshakeOff_A 00107874751283900
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[1].LcHandshakeOn_A 001078747511852300
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[1].SysHandshakeOff_A 0010787475595151300
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[1].SysHandshakeOn_A 001078747518908300
tb.dut.rstmgr_attrs_sva_if.AlertInfoAttr_A 0050550500
tb.dut.rstmgr_attrs_sva_if.CpuInfoAttr_A 0050550500
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorAboveFall_A 0050919005884800
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorAboveRise_A 0050919005884800
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoAboveFall_A 0048880762884800
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoAboveRise_A 0048880762884800
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoDiv2AboveFall_A 0024441330884800
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoDiv2AboveRise_A 0024441330884800
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoDiv4AboveFall_A 0012220198884800
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoDiv4AboveRise_A 0012220198884800
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorUcbAboveFall_A 0024441375884800
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorUcbAboveRise_A 0024441375884800
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcAboveFall_A 00509190052168700
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcAboveRise_A 00509190052168700
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcAonAboveFall_A 0015434022168700
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcAonAboveRise_A 0015434022168700
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcShadowedAboveFall_A 00509190052168700
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcShadowedAboveRise_A 00509190052168700
tb.dut.rstmgr_cascading_sva_if.CascadePorToAonAboveFall_A 001543402710100
tb.dut.rstmgr_cascading_sva_if.CascadeSysToSysAboveFall_A 00509190052168700
tb.dut.rstmgr_cascading_sva_if.CascadeSysToSysAboveRise_A 00509190052168700
tb.dut.rstmgr_cascading_sva_if.ScanRstToAonRise_A 00154340221600
tb.dut.rstmgr_cascading_sva_if.StablePorToAonRise_A 001543402884800
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].CascadeLcToSysAboveFall_A 00107874752168700
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].CascadeLcToSysAboveRise_A 00107874752168700
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].CascadeLocalRstToLcAboveFall_A 00107874752168700
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].CascadeLocalRstToLcAboveRise_A 00107874752168700
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A 00122201982168700
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A 00122201982168700
tb.dut.rstmgr_cascading_sva_if.g_power_domains[1].CascadeLcToSysAboveFall_A 00107874752168700
tb.dut.rstmgr_cascading_sva_if.g_power_domains[1].CascadeLcToSysAboveRise_A 00107874752168700
tb.dut.rstmgr_cascading_sva_if.g_power_domains[1].CascadeLocalRstToLcAboveFall_A 00107874752168700
tb.dut.rstmgr_cascading_sva_if.g_power_domains[1].CascadeLocalRstToLcAboveRise_A 00107874752168700
tb.dut.rstmgr_csr_assert.TlulOOBAddrErr_A 0011575447939600
tb.dut.rstmgr_csr_assert.alert_regwen_rd_A 0011575447334600
tb.dut.rstmgr_csr_assert.cpu_regwen_rd_A 0011575447336000
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_0_rd_A 0011575447711500
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_1_rd_A 0011575447693900
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_2_rd_A 0011575447687100
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_3_rd_A 0011575447705600
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_4_rd_A 0011575447676800
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_5_rd_A 0011575447683500
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_6_rd_A 0011575447694600
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_7_rd_A 0011575447711200
tb.dut.rstmgr_csr_assert.sw_rst_regwen_0_rd_A 0011575447382000
tb.dut.rstmgr_csr_assert.sw_rst_regwen_1_rd_A 0011575447400100
tb.dut.rstmgr_csr_assert.sw_rst_regwen_2_rd_A 0011575447389400
tb.dut.rstmgr_csr_assert.sw_rst_regwen_3_rd_A 0011575447380000
tb.dut.rstmgr_csr_assert.sw_rst_regwen_4_rd_A 0011575447398600
tb.dut.rstmgr_csr_assert.sw_rst_regwen_5_rd_A 0011575447387000
tb.dut.rstmgr_csr_assert.sw_rst_regwen_6_rd_A 0011575447379600
tb.dut.rstmgr_csr_assert.sw_rst_regwen_7_rd_A 0011575447385200
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c0EnTracksRstI2c0Active_A 00122201981404600
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c0EnTracksRstI2c0Inactive_A 00122201982277900
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c1EnTracksRstI2c1Active_A 00122201981412100
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c1EnTracksRstI2c1Inactive_A 00122201982285100
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c2EnTracksRstI2c2Active_A 00122201981416200
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c2EnTracksRstI2c2Inactive_A 00122201982290600
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoDiv2EnTracksRstLcIoDiv2Active_A 00244413301291000
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoDiv2EnTracksRstLcIoDiv2Inactive_A 00244413302168700
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoDiv4ShadowedEnTracksRstLcIoDiv4ShadowedActive_A 00122201981293900
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoDiv4ShadowedEnTracksRstLcIoDiv4ShadowedInactive_A 00122201982173700
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoEnTracksRstLcIoActive_A 00488807621291600
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoEnTracksRstLcIoInactive_A 00488807622168700
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcShadowedEnTracksRstLcShadowedActive_A 00509190051288900
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcShadowedEnTracksRstLcShadowedInactive_A 00509190052168700
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcUsbEnTracksRstLcUsbActive_A 00244413751292400
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcUsbEnTracksRstLcUsbInactive_A 00244413752168700
tb.dut.rstmgr_rst_en_track_sva_if.D0RstPorAonEnTracksRstPorAonActive_A 0015434025000
tb.dut.rstmgr_rst_en_track_sva_if.D0RstPorAonEnTracksRstPorAonInactive_A 001543402882500
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiDeviceEnTracksRstSpiDeviceActive_A 00122201981380000
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiDeviceEnTracksRstSpiDeviceInactive_A 00122201982254500
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiHost0EnTracksRstSpiHost0Active_A 00488807621384200
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiHost0EnTracksRstSpiHost0Inactive_A 00488807622257700
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiHost1EnTracksRstSpiHost1Active_A 00244413301386700
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiHost1EnTracksRstSpiHost1Inactive_A 00244413302261400
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSysEnTracksRstSysActive_A 00509190051291900
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSysEnTracksRstSysInactive_A 00509190052168700
tb.dut.rstmgr_rst_en_track_sva_if.D0RstUsbAonEnTracksRstUsbAonActive_A 0015434021360100
tb.dut.rstmgr_rst_en_track_sva_if.D0RstUsbAonEnTracksRstUsbAonInactive_A 0015434022190200
tb.dut.rstmgr_rst_en_track_sva_if.D0RstUsbEnTracksRstUsbActive_A 00244413751394200
tb.dut.rstmgr_rst_en_track_sva_if.D0RstUsbEnTracksRstUsbInactive_A 00244413752268900
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcAonEnTracksRstLcAonActive_A 0015434021286100
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcAonEnTracksRstLcAonInactive_A 0015434022166400
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoDiv2EnTracksRstLcIoDiv2Active_A 00244413301286400
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoDiv2EnTracksRstLcIoDiv2Inactive_A 00244413302168700
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoDiv4ShadowedEnTracksRstLcIoDiv4ShadowedActive_A 00122201981288900
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoDiv4ShadowedEnTracksRstLcIoDiv4ShadowedInactive_A 00122201982173700
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoEnTracksRstLcIoActive_A 00488807621286300
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoEnTracksRstLcIoInactive_A 00488807622168700
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcShadowedEnTracksRstLcShadowedActive_A 00509190051291900
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcShadowedEnTracksRstLcShadowedInactive_A 00509190052173700
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcUsbEnTracksRstLcUsbActive_A 00244413751286200
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcUsbEnTracksRstLcUsbInactive_A 00244413752168700
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorAonEnTracksRstPorAonInactive_A 001543402884800
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorEnTracksRstPorActive_A 00509190053000
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoDiv2EnTracksRstPorIoDiv2Active_A 00244413302500
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoDiv2EnTracksRstPorIoDiv2Inactive_A 0024441330236100
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoDiv4EnTracksRstPorIoDiv4Inactive_A 0012220198884800
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoEnTracksRstPorIoActive_A 00488807622700
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorUsbEnTracksRstPorUsbActive_A 00244413753100
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorUsbEnTracksRstPorUsbInactive_A 0024441375236100
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstSysIoDiv4EnTracksRstSysIoDiv4Active_A 00122201981287300
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstSysIoDiv4EnTracksRstSysIoDiv4Inactive_A 00122201982168700
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[0].RstEnOff_A 00122201981369500
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[0].RstEnOn_A 0012220198101700
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[0].RstNOff_A 00122201981369500
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[0].RstNOn_A 0012220198101700
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[1].RstEnOff_A 00488807621244100
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[1].RstEnOn_A 004888076297000
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[1].RstNOff_A 00488807621244100
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[1].RstNOn_A 004888076297000
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[2].RstEnOff_A 00244413301247500
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[2].RstEnOn_A 002444133097000
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[2].RstNOff_A 00244413301247500
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[2].RstNOn_A 002444133097000
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[3].RstEnOff_A 00244413751255100
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[3].RstEnOn_A 0024441375103100
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[3].RstNOff_A 00244413751255100
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[3].RstNOn_A 0024441375103100
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[4].RstEnOff_A 0015434022144800
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[4].RstEnOn_A 001543402109400
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tb.dut.tlul_assert_device.gen_assert_final[49].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[4].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[50].noOutstandingReqsAtEndOfSim_A 0062062000
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tb.dut.tlul_assert_device.gen_assert_final[53].noOutstandingReqsAtEndOfSim_A 0062062000
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tb.dut.tlul_assert_device.gen_assert_final[56].noOutstandingReqsAtEndOfSim_A 0062062000
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tb.dut.tlul_assert_device.gen_assert_final[58].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[59].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[5].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[60].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[61].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[62].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[63].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[64].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[65].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[66].noOutstandingReqsAtEndOfSim_A 0062062000
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tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_device.aDataKnown_M 001157606749499800
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A 0011575447635100
tb.dut.tlul_assert_device.gen_device.contigMask_M 001157606781167000
tb.dut.tlul_assert_device.gen_device.dDataKnown_A 001157606784055200
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A 0011575447703800
tb.dut.tlul_assert_device.gen_device.legalAParam_M 0011576067111123300
tb.dut.tlul_assert_device.gen_device.legalDParam_A 0011576067165470000
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M 0011576067111123300
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A 0011576067165470000
tb.dut.tlul_assert_device.gen_device.respOpcode_A 0011576067165470000
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A 0011576067165470000
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A 0011575447371900
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A 0011575447302000
tb.dut.tlul_assert_device.p_dbw.TlDbw_A 0062062000
tb.dut.u_alert_info.CntStoreSlot_A 0050550500
tb.dut.u_alert_info.CntWidth_A 0050550500
tb.dut.u_cpu_info.CntStoreSlot_A 0050550500
tb.dut.u_cpu_info.CntWidth_A 0050550500
tb.dut.u_ctrl_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_ctrl_scanmode_sync.OutputsKnown_A 0012220198700704800
tb.dut.u_ctrl_scanmode_sync.gen_no_flops.OutputDelay_A 0012220198700704800
tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00217372123200
tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002725222000
tb.dut.u_d0_i2c0.u_prim_mubi4_sender.OutputsKnown_A 0012220198581772000
tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00227772227200
tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002725222000
tb.dut.u_d0_i2c0.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_d0_i2c0.u_scanmode_sync.OutputsKnown_A 0010787475591170400
tb.dut.u_d0_i2c0.u_scanmode_sync.gen_no_flops.OutputDelay_A 0010787475591170400
tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00217372123200
tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002725222000
tb.dut.u_d0_i2c1.u_prim_mubi4_sender.OutputsKnown_A 0012220198581934600
tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00228492234400
tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002725222000
tb.dut.u_d0_i2c1.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_d0_i2c1.u_scanmode_sync.OutputsKnown_A 0010787475591170400
tb.dut.u_d0_i2c1.u_scanmode_sync.gen_no_flops.OutputDelay_A 0010787475591170400
tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00217372123200
tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002725222000
tb.dut.u_d0_i2c2.u_prim_mubi4_sender.OutputsKnown_A 0012220198582370800
tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00229042239900
tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002725222000
tb.dut.u_d0_i2c2.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_d0_i2c2.u_scanmode_sync.OutputsKnown_A 0010787475591170400
tb.dut.u_d0_i2c2.u_scanmode_sync.gen_no_flops.OutputDelay_A 0010787475591170400
tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00217372123200
tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002725222000
tb.dut.u_d0_lc.u_prim_mubi4_sender.OutputsKnown_A 00509190052489689000
tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00216872118200
tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002725222000
tb.dut.u_d0_lc.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_d0_lc.u_scanmode_sync.OutputsKnown_A 0010787475591170400
tb.dut.u_d0_lc.u_scanmode_sync.gen_no_flops.OutputDelay_A 0010787475591170400
tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00217372123200
tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002725222000
tb.dut.u_d0_lc_io.u_prim_mubi4_sender.OutputsKnown_A 00488807622389932100
tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00216872118200
tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002725222000
tb.dut.u_d0_lc_io.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_d0_lc_io.u_scanmode_sync.OutputsKnown_A 0010787475591170400
tb.dut.u_d0_lc_io.u_scanmode_sync.gen_no_flops.OutputDelay_A 0010787475591170400
tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00217372123200
tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002725222000
tb.dut.u_d0_lc_io_div2.u_prim_mubi4_sender.OutputsKnown_A 00244413301193987700
tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00216872118200
tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002725222000
tb.dut.u_d0_lc_io_div2.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_d0_lc_io_div2.u_scanmode_sync.OutputsKnown_A 0010787475591170400
tb.dut.u_d0_lc_io_div2.u_scanmode_sync.gen_no_flops.OutputDelay_A 0010787475591170400
tb.dut.u_d0_lc_io_div4.u_prim_mubi4_sender.OutputsKnown_A 0012220198594286100
tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00216872118200
tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002725222000
tb.dut.u_d0_lc_io_div4.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_d0_lc_io_div4.u_scanmode_sync.OutputsKnown_A 0010787475591170400
tb.dut.u_d0_lc_io_div4.u_scanmode_sync.gen_no_flops.OutputDelay_A 0010787475591170400
tb.dut.u_d0_lc_io_div4_shadowed.u_prim_mubi4_sender.OutputsKnown_A 0012220198594286100
tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00216872118200
tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002725222000
tb.dut.u_d0_lc_io_div4_shadowed.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_d0_lc_io_div4_shadowed.u_scanmode_sync.OutputsKnown_A 0010787475591170400
tb.dut.u_d0_lc_io_div4_shadowed.u_scanmode_sync.gen_no_flops.OutputDelay_A 0010787475591170400
tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00217372123200
tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002725222000
tb.dut.u_d0_lc_shadowed.u_prim_mubi4_sender.OutputsKnown_A 00509190052489862300
tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00216872118200
tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002725222000
tb.dut.u_d0_lc_shadowed.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_d0_lc_shadowed.u_scanmode_sync.OutputsKnown_A 0010787475591170400
tb.dut.u_d0_lc_shadowed.u_scanmode_sync.gen_no_flops.OutputDelay_A 0010787475591170400
tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00217372123200
tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002725222000
tb.dut.u_d0_lc_usb.u_prim_mubi4_sender.OutputsKnown_A 00244413751193941300
tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00216872118200
tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002725222000
tb.dut.u_d0_lc_usb.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_d0_lc_usb.u_scanmode_sync.OutputsKnown_A 0010787475591170400
tb.dut.u_d0_lc_usb.u_scanmode_sync.gen_no_flops.OutputDelay_A 0010787475591170400
tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00217372123200
tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002725222000
tb.dut.u_d0_spi_device.u_prim_mubi4_sender.OutputsKnown_A 0012220198582287700
tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00225432203800
tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002725222000
tb.dut.u_d0_spi_device.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_d0_spi_device.u_scanmode_sync.OutputsKnown_A 0010787475591170400
tb.dut.u_d0_spi_device.u_scanmode_sync.gen_no_flops.OutputDelay_A 0010787475591170400
tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00217372123200
tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002725222000
tb.dut.u_d0_spi_host0.u_prim_mubi4_sender.OutputsKnown_A 00488807622340380700
tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00225752207000
tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002725222000
tb.dut.u_d0_spi_host0.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_d0_spi_host0.u_scanmode_sync.OutputsKnown_A 0010787475591170400
tb.dut.u_d0_spi_host0.u_scanmode_sync.gen_no_flops.OutputDelay_A 0010787475591170400
tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00217372123200
tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002725222000
tb.dut.u_d0_spi_host1.u_prim_mubi4_sender.OutputsKnown_A 00244413301169546200
tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00226092210400
tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002725222000
tb.dut.u_d0_spi_host1.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_d0_spi_host1.u_scanmode_sync.OutputsKnown_A 0010787475591170400
tb.dut.u_d0_spi_host1.u_scanmode_sync.gen_no_flops.OutputDelay_A 0010787475591170400
tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00217372123200
tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002725222000
tb.dut.u_d0_sys.u_prim_mubi4_sender.OutputsKnown_A 00509190052460297400
tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00216872118200
tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002725222000
tb.dut.u_d0_sys.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_d0_sys.u_scanmode_sync.OutputsKnown_A 0010787475591170400
tb.dut.u_d0_sys.u_scanmode_sync.gen_no_flops.OutputDelay_A 0010787475591170400
tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00217372123200
tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002725222000
tb.dut.u_d0_usb.u_prim_mubi4_sender.OutputsKnown_A 00244413751170164500
tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00226852218000
tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002725222000
tb.dut.u_d0_usb.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_d0_usb.u_scanmode_sync.OutputsKnown_A 0010787475591170400
tb.dut.u_d0_usb.u_scanmode_sync.gen_no_flops.OutputDelay_A 0010787475591170400
tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00216142110900
tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002725222000
tb.dut.u_d0_usb_aon.u_prim_mubi4_sender.OutputsKnown_A 00154340272174300
tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00227292222400
tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002725222000
tb.dut.u_d0_usb_aon.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_d0_usb_aon.u_scanmode_sync.OutputsKnown_A 0010787475591170400
tb.dut.u_d0_usb_aon.u_scanmode_sync.gen_no_flops.OutputDelay_A 0010787475591170400
tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00217372123200
tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002725222000
tb.dut.u_daon_lc.u_prim_mubi4_sender.OutputsKnown_A 00509190052562272500
tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00216872118200
tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002725222000
tb.dut.u_daon_lc.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_daon_lc.u_scanmode_sync.OutputsKnown_A 0010787475591170400
tb.dut.u_daon_lc.u_scanmode_sync.gen_no_flops.OutputDelay_A 0010787475591170400
tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00216142110900
tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002725222000
tb.dut.u_daon_lc_aon.u_prim_mubi4_sender.OutputsKnown_A 00154340275867600
tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00216872118200
tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002725222000
tb.dut.u_daon_lc_aon.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_daon_lc_aon.u_scanmode_sync.OutputsKnown_A 0010787475591170400
tb.dut.u_daon_lc_aon.u_scanmode_sync.gen_no_flops.OutputDelay_A 0010787475591170400
tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00217372123200
tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002725222000
tb.dut.u_daon_lc_io.u_prim_mubi4_sender.OutputsKnown_A 00488807622459794200
tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00216872118200
tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002725222000
tb.dut.u_daon_lc_io.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_daon_lc_io.u_scanmode_sync.OutputsKnown_A 0010787475591170400
tb.dut.u_daon_lc_io.u_scanmode_sync.gen_no_flops.OutputDelay_A 0010787475591170400
tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00217372123200
tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002725222000
tb.dut.u_daon_lc_io_div2.u_prim_mubi4_sender.OutputsKnown_A 00244413301228894700
tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00216872118200
tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002725222000
tb.dut.u_daon_lc_io_div2.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_daon_lc_io_div2.u_scanmode_sync.OutputsKnown_A 0010787475591170400
tb.dut.u_daon_lc_io_div2.u_scanmode_sync.gen_no_flops.OutputDelay_A 0010787475591170400
tb.dut.u_daon_lc_io_div4.u_prim_mubi4_sender.OutputsKnown_A 0012220198611745700
tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00216872118200
tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002725222000
tb.dut.u_daon_lc_io_div4.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_daon_lc_io_div4.u_scanmode_sync.OutputsKnown_A 0010787475591170400
tb.dut.u_daon_lc_io_div4.u_scanmode_sync.gen_no_flops.OutputDelay_A 0010787475591170400
tb.dut.u_daon_lc_io_div4_shadowed.u_prim_mubi4_sender.OutputsKnown_A 0012220198611745700
tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00216872118200
tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002725222000
tb.dut.u_daon_lc_io_div4_shadowed.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_daon_lc_io_div4_shadowed.u_scanmode_sync.OutputsKnown_A 0010787475591170400
tb.dut.u_daon_lc_io_div4_shadowed.u_scanmode_sync.gen_no_flops.OutputDelay_A 0010787475591170400
tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00217372123200
tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002725222000
tb.dut.u_daon_lc_shadowed.u_prim_mubi4_sender.OutputsKnown_A 00509190052562229200
tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00216872118200
tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002725222000
tb.dut.u_daon_lc_shadowed.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_daon_lc_shadowed.u_scanmode_sync.OutputsKnown_A 0010787475591170400
tb.dut.u_daon_lc_shadowed.u_scanmode_sync.gen_no_flops.OutputDelay_A 0010787475591170400
tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00217372123200
tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002725222000
tb.dut.u_daon_lc_usb.u_prim_mubi4_sender.OutputsKnown_A 00244413751228895700
tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00216872118200
tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002725222000
tb.dut.u_daon_lc_usb.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_daon_lc_usb.u_scanmode_sync.OutputsKnown_A 0010787475591170400
tb.dut.u_daon_lc_usb.u_scanmode_sync.gen_no_flops.OutputDelay_A 0010787475591170400
tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00217372123200
tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002725222000
tb.dut.u_daon_por.u_prim_mubi4_sender.OutputsKnown_A 00509190052921745400
tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic.selKnown0 008848834300
tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002725222000
tb.dut.u_daon_por.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_daon_por.u_scanmode_sync.OutputsKnown_A 0010787475591170400
tb.dut.u_daon_por.u_scanmode_sync.gen_no_flops.OutputDelay_A 0010787475591170400
tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00217372123200
tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002725222000
tb.dut.u_daon_por_io.u_prim_mubi4_sender.OutputsKnown_A 00488807622804761600
tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic.selKnown0 008848834300
tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002725222000
tb.dut.u_daon_por_io.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_daon_por_io.u_scanmode_sync.OutputsKnown_A 0010787475591170400
tb.dut.u_daon_por_io.u_scanmode_sync.gen_no_flops.OutputDelay_A 0010787475591170400
tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00217372123200
tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002725222000
tb.dut.u_daon_por_io_div2.u_prim_mubi4_sender.OutputsKnown_A 00244413301402017700
tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown0 008848834300
tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002725222000
tb.dut.u_daon_por_io_div2.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_daon_por_io_div2.u_scanmode_sync.OutputsKnown_A 0010787475591170400
tb.dut.u_daon_por_io_div2.u_scanmode_sync.gen_no_flops.OutputDelay_A 0010787475591170400
tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00217372123200
tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002725222000
tb.dut.u_daon_por_io_div4.u_prim_mubi4_sender.OutputsKnown_A 0012220198700704800
tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown0 008848834300
tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002725222000
tb.dut.u_daon_por_io_div4.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_daon_por_io_div4.u_scanmode_sync.OutputsKnown_A 0010787475591170400
tb.dut.u_daon_por_io_div4.u_scanmode_sync.gen_no_flops.OutputDelay_A 0010787475591170400
tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00217372123200
tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002725222000
tb.dut.u_daon_por_usb.u_prim_mubi4_sender.OutputsKnown_A 00244413751401999600
tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown0 008848834300
tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002725222000
tb.dut.u_daon_por_usb.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_daon_por_usb.u_scanmode_sync.OutputsKnown_A 0010787475591170400
tb.dut.u_daon_por_usb.u_scanmode_sync.gen_no_flops.OutputDelay_A 0010787475591170400
tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00217372123200
tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002725222000
tb.dut.u_daon_sys_io_div4.u_prim_mubi4_sender.OutputsKnown_A 0012220198604693400
tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00216872118200
tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002725222000
tb.dut.u_daon_sys_io_div4.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_daon_sys_io_div4.u_scanmode_sync.OutputsKnown_A 0010787475591170400
tb.dut.u_daon_sys_io_div4.u_scanmode_sync.gen_no_flops.OutputDelay_A 0010787475591170400
tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic.selKnown0 00216872118200
tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic.selKnown1 002725222000
tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic.selKnown0 00216872118200
tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic.selKnown1 002725222000
tb.dut.u_reg.en2addrHit 001157544796311500
tb.dut.u_reg.reAfterRv 001157544796297900
tb.dut.u_reg.rePulse 001157544751653300
tb.dut.u_reg.u_chk.PayLoadWidthCheck 0062062000
tb.dut.u_reg.u_reg_if.AllowedLatency_A 0062062000
tb.dut.u_reg.u_reg_if.MatchedWidthAssert 0062062000
tb.dut.u_reg.u_reg_if.u_err.dataWidthOnly32_A 0062062000
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A 0062062000
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck 0062062000
tb.dut.u_reg.u_rsp_intg_gen.DataWidthCheck_A 0062062000
tb.dut.u_reg.u_rsp_intg_gen.PayLoadWidthCheck 0062062000
tb.dut.u_reg.wePulse 001157544744644600
tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic.selKnown0 00216872118200
tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic.selKnown1 002725222000
tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic.selKnown0 00216872118200
tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic.selKnown1 002725222000


Detail Report for Cover Sequences

Cover Sequences All Matches:
COVER SEQUENCESCATEGORYSEVERITYATTEMPTSALL MATCHESFIRST MATCHESINCOMPLETESRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C 0011576067602760270
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C 0011576067233523351
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C 0011576067234323431
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C 0011576067162516251
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C 00115760671151151
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C 0011576067125412541
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C 00115760677747741
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C 0011576067514351430
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C 001157606765690656900
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C 0011576067495440495440454

Cover Sequences First Matches:
COVER SEQUENCESCATEGORYSEVERITYATTEMPTSALL MATCHESFIRST MATCHESINCOMPLETESRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C 0011576067602760270
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C 0011576067233523351
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C 0011576067234323431
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C 0011576067162516251
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C 00115760671151151
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C 0011576067125412541
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C 00115760677747741
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C 0011576067514351430
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C 001157606765690656900
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C 0011576067495440495440454

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