Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.88 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T76 /workspace/coverage/default/0.rstmgr_sec_cm.63520574 Dec 24 12:29:42 PM PST 23 Dec 24 12:30:31 PM PST 23 16518408126 ps
T503 /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.1175176165 Dec 24 12:25:07 PM PST 23 Dec 24 12:25:09 PM PST 23 244197051 ps
T504 /workspace/coverage/default/0.rstmgr_por_stretcher.2481644147 Dec 24 12:25:34 PM PST 23 Dec 24 12:25:37 PM PST 23 89732927 ps
T505 /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.2274228553 Dec 24 12:25:10 PM PST 23 Dec 24 12:25:12 PM PST 23 74534513 ps
T506 /workspace/coverage/default/11.rstmgr_sw_rst.853059745 Dec 24 12:29:56 PM PST 23 Dec 24 12:30:25 PM PST 23 331208542 ps
T507 /workspace/coverage/default/43.rstmgr_sw_rst.2289383793 Dec 24 12:28:49 PM PST 23 Dec 24 12:29:02 PM PST 23 325622347 ps
T508 /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.2060905961 Dec 24 12:26:38 PM PST 23 Dec 24 12:26:42 PM PST 23 67284905 ps
T509 /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.3133873454 Dec 24 12:28:51 PM PST 23 Dec 24 12:29:03 PM PST 23 243651920 ps
T510 /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.1877257774 Dec 24 12:25:42 PM PST 23 Dec 24 12:25:51 PM PST 23 1227049468 ps
T511 /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.674162691 Dec 24 12:25:42 PM PST 23 Dec 24 12:25:45 PM PST 23 72860470 ps
T512 /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.1779299912 Dec 24 12:25:21 PM PST 23 Dec 24 12:25:28 PM PST 23 1222911215 ps
T513 /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.3639117839 Dec 24 12:24:35 PM PST 23 Dec 24 12:24:37 PM PST 23 91272395 ps
T514 /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.1653606550 Dec 24 12:25:57 PM PST 23 Dec 24 12:26:01 PM PST 23 153497088 ps
T515 /workspace/coverage/default/41.rstmgr_por_stretcher.4247184254 Dec 24 12:27:01 PM PST 23 Dec 24 12:27:07 PM PST 23 168151371 ps
T516 /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.3875156650 Dec 24 12:26:39 PM PST 23 Dec 24 12:26:44 PM PST 23 244166753 ps
T517 /workspace/coverage/default/1.rstmgr_reset.1375869762 Dec 24 12:33:30 PM PST 23 Dec 24 12:34:10 PM PST 23 1277753742 ps
T518 /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.3603035391 Dec 24 12:25:47 PM PST 23 Dec 24 12:25:57 PM PST 23 2348879589 ps
T519 /workspace/coverage/default/48.rstmgr_alert_test.3142752154 Dec 24 12:28:03 PM PST 23 Dec 24 12:28:16 PM PST 23 66569456 ps
T520 /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.1284902876 Dec 24 12:27:57 PM PST 23 Dec 24 12:28:11 PM PST 23 157536452 ps
T521 /workspace/coverage/default/40.rstmgr_smoke.2681722451 Dec 24 12:26:18 PM PST 23 Dec 24 12:26:22 PM PST 23 241397747 ps
T522 /workspace/coverage/default/14.rstmgr_reset.3668106041 Dec 24 12:24:08 PM PST 23 Dec 24 12:24:16 PM PST 23 2021709897 ps
T523 /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.853224451 Dec 24 12:24:39 PM PST 23 Dec 24 12:24:49 PM PST 23 2157965618 ps
T524 /workspace/coverage/default/0.rstmgr_reset.743297062 Dec 24 12:26:23 PM PST 23 Dec 24 12:26:29 PM PST 23 821655151 ps
T525 /workspace/coverage/default/7.rstmgr_smoke.2697986517 Dec 24 12:25:42 PM PST 23 Dec 24 12:25:45 PM PST 23 110329201 ps
T526 /workspace/coverage/default/26.rstmgr_smoke.2242873996 Dec 24 12:24:50 PM PST 23 Dec 24 12:24:53 PM PST 23 125821372 ps
T527 /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.496967565 Dec 24 12:25:09 PM PST 23 Dec 24 12:25:11 PM PST 23 243496742 ps
T528 /workspace/coverage/default/23.rstmgr_reset.2664758763 Dec 24 12:26:25 PM PST 23 Dec 24 12:26:33 PM PST 23 1432325835 ps
T77 /workspace/coverage/default/3.rstmgr_sec_cm.82552651 Dec 24 12:26:12 PM PST 23 Dec 24 12:26:43 PM PST 23 16511209952 ps
T529 /workspace/coverage/default/44.rstmgr_smoke.2149316274 Dec 24 12:27:57 PM PST 23 Dec 24 12:28:11 PM PST 23 121531681 ps
T530 /workspace/coverage/default/29.rstmgr_stress_all.2913548762 Dec 24 12:25:34 PM PST 23 Dec 24 12:26:00 PM PST 23 7076999281 ps
T531 /workspace/coverage/default/22.rstmgr_por_stretcher.1760179607 Dec 24 12:25:20 PM PST 23 Dec 24 12:25:21 PM PST 23 102327211 ps
T532 /workspace/coverage/default/44.rstmgr_sw_rst.2574701212 Dec 24 12:26:45 PM PST 23 Dec 24 12:26:49 PM PST 23 405250096 ps
T533 /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.982353310 Dec 24 12:28:57 PM PST 23 Dec 24 12:29:13 PM PST 23 1227378098 ps
T534 /workspace/coverage/default/17.rstmgr_sw_rst.4105769864 Dec 24 12:25:44 PM PST 23 Dec 24 12:25:48 PM PST 23 128985461 ps
T535 /workspace/coverage/default/8.rstmgr_stress_all.261165129 Dec 24 12:26:40 PM PST 23 Dec 24 12:27:32 PM PST 23 12093742817 ps
T536 /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.996845761 Dec 24 12:27:57 PM PST 23 Dec 24 12:28:10 PM PST 23 86074054 ps
T537 /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.1390574311 Dec 24 12:25:34 PM PST 23 Dec 24 12:25:36 PM PST 23 99194839 ps
T538 /workspace/coverage/default/41.rstmgr_smoke.2698711933 Dec 24 12:26:58 PM PST 23 Dec 24 12:27:04 PM PST 23 198024947 ps
T539 /workspace/coverage/default/11.rstmgr_stress_all.3075182928 Dec 24 12:23:57 PM PST 23 Dec 24 12:23:59 PM PST 23 122781515 ps
T540 /workspace/coverage/default/49.rstmgr_alert_test.2431133808 Dec 24 12:28:46 PM PST 23 Dec 24 12:28:55 PM PST 23 61783817 ps
T541 /workspace/coverage/default/37.rstmgr_alert_test.1965765842 Dec 24 12:28:48 PM PST 23 Dec 24 12:28:58 PM PST 23 70663358 ps
T542 /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.3343019558 Dec 24 12:26:35 PM PST 23 Dec 24 12:26:38 PM PST 23 245901278 ps
T543 /workspace/coverage/default/24.rstmgr_reset.834371913 Dec 24 12:24:42 PM PST 23 Dec 24 12:24:50 PM PST 23 1654374378 ps
T544 /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.3056786141 Dec 24 12:26:39 PM PST 23 Dec 24 12:26:44 PM PST 23 110398661 ps
T545 /workspace/coverage/default/29.rstmgr_por_stretcher.3499290911 Dec 24 12:26:17 PM PST 23 Dec 24 12:26:21 PM PST 23 143778640 ps
T546 /workspace/coverage/default/40.rstmgr_sw_rst.3525254333 Dec 24 12:26:15 PM PST 23 Dec 24 12:26:18 PM PST 23 131522610 ps
T547 /workspace/coverage/default/28.rstmgr_por_stretcher.402703659 Dec 24 12:26:38 PM PST 23 Dec 24 12:26:42 PM PST 23 84773200 ps
T548 /workspace/coverage/default/38.rstmgr_smoke.83964996 Dec 24 12:27:27 PM PST 23 Dec 24 12:27:31 PM PST 23 114412988 ps
T549 /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.486648624 Dec 24 12:26:17 PM PST 23 Dec 24 12:26:21 PM PST 23 184150059 ps
T550 /workspace/coverage/default/26.rstmgr_stress_all.3242683590 Dec 24 12:26:38 PM PST 23 Dec 24 12:26:47 PM PST 23 1321286687 ps
T551 /workspace/coverage/default/3.rstmgr_sw_rst.4004570002 Dec 24 12:28:51 PM PST 23 Dec 24 12:29:04 PM PST 23 319583995 ps
T552 /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.1818001438 Dec 24 12:24:45 PM PST 23 Dec 24 12:24:48 PM PST 23 182565963 ps
T553 /workspace/coverage/default/7.rstmgr_alert_test.3022078924 Dec 24 12:26:16 PM PST 23 Dec 24 12:26:20 PM PST 23 70784954 ps
T554 /workspace/coverage/default/12.rstmgr_sw_rst.1542640013 Dec 24 12:26:53 PM PST 23 Dec 24 12:26:58 PM PST 23 368486954 ps
T555 /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.2779332450 Dec 24 12:25:05 PM PST 23 Dec 24 12:25:07 PM PST 23 245034207 ps
T556 /workspace/coverage/default/21.rstmgr_alert_test.2287463070 Dec 24 12:26:52 PM PST 23 Dec 24 12:26:55 PM PST 23 65820761 ps
T557 /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.4094945389 Dec 24 12:28:03 PM PST 23 Dec 24 12:28:17 PM PST 23 244780333 ps
T558 /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.3103054205 Dec 24 12:25:40 PM PST 23 Dec 24 12:25:43 PM PST 23 244824945 ps
T559 /workspace/coverage/default/11.rstmgr_por_stretcher.1646459881 Dec 24 12:26:17 PM PST 23 Dec 24 12:26:21 PM PST 23 145790121 ps
T560 /workspace/coverage/default/34.rstmgr_sw_rst.2840716419 Dec 24 12:25:28 PM PST 23 Dec 24 12:25:30 PM PST 23 118957070 ps
T561 /workspace/coverage/default/32.rstmgr_smoke.1573517721 Dec 24 12:26:56 PM PST 23 Dec 24 12:27:01 PM PST 23 125158539 ps
T562 /workspace/coverage/default/44.rstmgr_stress_all.1468618835 Dec 24 12:26:32 PM PST 23 Dec 24 12:27:03 PM PST 23 6806912207 ps
T563 /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.1968812753 Dec 24 12:25:52 PM PST 23 Dec 24 12:25:54 PM PST 23 125943498 ps
T564 /workspace/coverage/default/1.rstmgr_sw_rst.2603377085 Dec 24 12:26:39 PM PST 23 Dec 24 12:26:46 PM PST 23 551747013 ps
T565 /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.1463265625 Dec 24 12:28:06 PM PST 23 Dec 24 12:28:20 PM PST 23 126583265 ps
T566 /workspace/coverage/default/30.rstmgr_sw_rst.1760435430 Dec 24 12:26:32 PM PST 23 Dec 24 12:26:36 PM PST 23 376197330 ps
T567 /workspace/coverage/default/47.rstmgr_alert_test.3493355553 Dec 24 12:26:08 PM PST 23 Dec 24 12:26:11 PM PST 23 77617473 ps
T568 /workspace/coverage/default/21.rstmgr_sw_rst.3635957702 Dec 24 12:25:49 PM PST 23 Dec 24 12:25:52 PM PST 23 268833184 ps
T569 /workspace/coverage/default/10.rstmgr_por_stretcher.251291796 Dec 24 12:26:50 PM PST 23 Dec 24 12:26:52 PM PST 23 91815303 ps
T570 /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.1429494742 Dec 24 12:29:13 PM PST 23 Dec 24 12:29:28 PM PST 23 244154235 ps
T571 /workspace/coverage/default/36.rstmgr_sw_rst.2509102753 Dec 24 12:28:47 PM PST 23 Dec 24 12:28:58 PM PST 23 339167896 ps
T572 /workspace/coverage/default/42.rstmgr_smoke.2890342856 Dec 24 12:26:23 PM PST 23 Dec 24 12:26:28 PM PST 23 263662274 ps
T573 /workspace/coverage/default/8.rstmgr_sw_rst.607880327 Dec 24 12:27:22 PM PST 23 Dec 24 12:27:29 PM PST 23 505293879 ps
T574 /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.2443504736 Dec 24 12:27:27 PM PST 23 Dec 24 12:27:37 PM PST 23 2151663361 ps
T575 /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.158454256 Dec 24 12:26:52 PM PST 23 Dec 24 12:26:57 PM PST 23 61872854 ps
T576 /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.1562414237 Dec 24 12:29:56 PM PST 23 Dec 24 12:30:24 PM PST 23 244653705 ps
T577 /workspace/coverage/default/13.rstmgr_stress_all.1493836459 Dec 24 12:25:26 PM PST 23 Dec 24 12:26:14 PM PST 23 14166152160 ps
T578 /workspace/coverage/default/0.rstmgr_sw_rst.1905012253 Dec 24 12:25:19 PM PST 23 Dec 24 12:25:22 PM PST 23 413495381 ps
T579 /workspace/coverage/default/16.rstmgr_reset.645783526 Dec 24 12:25:35 PM PST 23 Dec 24 12:25:43 PM PST 23 1778165058 ps
T580 /workspace/coverage/default/18.rstmgr_alert_test.105121344 Dec 24 12:25:39 PM PST 23 Dec 24 12:25:43 PM PST 23 93272585 ps
T581 /workspace/coverage/default/30.rstmgr_alert_test.4047825749 Dec 24 12:26:42 PM PST 23 Dec 24 12:26:46 PM PST 23 59411860 ps
T582 /workspace/coverage/default/39.rstmgr_alert_test.2590631227 Dec 24 12:26:27 PM PST 23 Dec 24 12:26:29 PM PST 23 59498532 ps
T583 /workspace/coverage/default/23.rstmgr_sw_rst.75585712 Dec 24 12:26:25 PM PST 23 Dec 24 12:26:35 PM PST 23 131194976 ps
T584 /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.792352279 Dec 24 12:28:50 PM PST 23 Dec 24 12:29:09 PM PST 23 2382217988 ps
T585 /workspace/coverage/default/33.rstmgr_alert_test.3487664587 Dec 24 12:25:55 PM PST 23 Dec 24 12:25:57 PM PST 23 83069502 ps
T586 /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.3123425929 Dec 24 12:26:53 PM PST 23 Dec 24 12:27:02 PM PST 23 1220659769 ps
T587 /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.500384851 Dec 24 12:26:02 PM PST 23 Dec 24 12:26:09 PM PST 23 244077646 ps
T588 /workspace/coverage/default/47.rstmgr_por_stretcher.41130020 Dec 24 12:26:57 PM PST 23 Dec 24 12:27:02 PM PST 23 217499915 ps
T589 /workspace/coverage/default/7.rstmgr_reset.420760043 Dec 24 12:26:54 PM PST 23 Dec 24 12:27:01 PM PST 23 848531173 ps
T590 /workspace/coverage/default/27.rstmgr_reset.1819339221 Dec 24 12:26:06 PM PST 23 Dec 24 12:26:16 PM PST 23 1755882413 ps
T591 /workspace/coverage/default/13.rstmgr_smoke.3577807715 Dec 24 12:27:06 PM PST 23 Dec 24 12:27:12 PM PST 23 269204336 ps
T592 /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.3971811860 Dec 24 12:26:51 PM PST 23 Dec 24 12:26:54 PM PST 23 279329315 ps
T593 /workspace/coverage/default/45.rstmgr_smoke.1133399834 Dec 24 12:26:44 PM PST 23 Dec 24 12:26:48 PM PST 23 120615848 ps
T594 /workspace/coverage/default/16.rstmgr_smoke.3173648819 Dec 24 12:26:47 PM PST 23 Dec 24 12:26:50 PM PST 23 205116750 ps
T595 /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.2326052553 Dec 24 12:29:28 PM PST 23 Dec 24 12:29:45 PM PST 23 1906746304 ps
T596 /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.3920488339 Dec 24 12:27:57 PM PST 23 Dec 24 12:28:11 PM PST 23 173194076 ps
T597 /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.2957446228 Dec 24 12:25:20 PM PST 23 Dec 24 12:25:22 PM PST 23 152190717 ps
T598 /workspace/coverage/default/13.rstmgr_alert_test.3723999678 Dec 24 12:25:55 PM PST 23 Dec 24 12:25:57 PM PST 23 72493462 ps
T599 /workspace/coverage/default/27.rstmgr_smoke.4048026648 Dec 24 12:28:49 PM PST 23 Dec 24 12:29:01 PM PST 23 209732776 ps
T600 /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.819392486 Dec 24 12:24:16 PM PST 23 Dec 24 12:24:18 PM PST 23 174696607 ps
T601 /workspace/coverage/default/32.rstmgr_reset.3187426424 Dec 24 12:25:09 PM PST 23 Dec 24 12:25:15 PM PST 23 1047912288 ps
T602 /workspace/coverage/default/17.rstmgr_reset.1850597284 Dec 24 12:27:02 PM PST 23 Dec 24 12:27:11 PM PST 23 1040917084 ps
T603 /workspace/coverage/default/2.rstmgr_smoke.766874237 Dec 24 12:25:59 PM PST 23 Dec 24 12:26:05 PM PST 23 235167066 ps
T604 /workspace/coverage/default/24.rstmgr_smoke.1770467436 Dec 24 12:24:40 PM PST 23 Dec 24 12:24:43 PM PST 23 188790910 ps
T605 /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.2824565512 Dec 24 12:27:12 PM PST 23 Dec 24 12:27:16 PM PST 23 153156736 ps
T606 /workspace/coverage/default/8.rstmgr_reset.2334664276 Dec 24 12:26:25 PM PST 23 Dec 24 12:26:33 PM PST 23 1219072300 ps
T607 /workspace/coverage/default/6.rstmgr_stress_all.1747640390 Dec 24 12:27:23 PM PST 23 Dec 24 12:28:07 PM PST 23 11761949627 ps
T608 /workspace/coverage/default/5.rstmgr_reset.4262189414 Dec 24 12:25:44 PM PST 23 Dec 24 12:25:51 PM PST 23 1404044855 ps
T609 /workspace/coverage/default/19.rstmgr_por_stretcher.1669150258 Dec 24 12:28:18 PM PST 23 Dec 24 12:28:31 PM PST 23 138990214 ps
T610 /workspace/coverage/default/37.rstmgr_sw_rst.2477920747 Dec 24 12:29:00 PM PST 23 Dec 24 12:29:11 PM PST 23 421613541 ps
T611 /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.1797106282 Dec 24 12:25:52 PM PST 23 Dec 24 12:26:02 PM PST 23 1885244227 ps
T612 /workspace/coverage/default/4.rstmgr_por_stretcher.4118442524 Dec 24 12:25:35 PM PST 23 Dec 24 12:25:37 PM PST 23 125992275 ps
T613 /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.1463759644 Dec 24 12:26:38 PM PST 23 Dec 24 12:26:43 PM PST 23 133327831 ps
T614 /workspace/coverage/default/7.rstmgr_stress_all.2696960821 Dec 24 12:26:00 PM PST 23 Dec 24 12:26:08 PM PST 23 121147523 ps
T615 /workspace/coverage/default/24.rstmgr_alert_test.3548755319 Dec 24 12:24:43 PM PST 23 Dec 24 12:24:45 PM PST 23 78285099 ps
T616 /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.2859149878 Dec 24 12:29:33 PM PST 23 Dec 24 12:29:51 PM PST 23 1225133658 ps
T617 /workspace/coverage/default/0.rstmgr_smoke.3014314017 Dec 24 12:27:10 PM PST 23 Dec 24 12:27:15 PM PST 23 253744760 ps
T618 /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.3886460376 Dec 24 12:25:42 PM PST 23 Dec 24 12:25:46 PM PST 23 244440787 ps
T619 /workspace/coverage/default/35.rstmgr_sw_rst.1355261604 Dec 24 12:25:58 PM PST 23 Dec 24 12:26:03 PM PST 23 117443828 ps
T620 /workspace/coverage/default/20.rstmgr_por_stretcher.824415716 Dec 24 12:29:35 PM PST 23 Dec 24 12:29:49 PM PST 23 240322205 ps

Test location /workspace/coverage/default/29.rstmgr_smoke.3370307052
Short name T3
Test name
Test status
Simulation time 117953701 ps
CPU time 1.16 seconds
Started Dec 24 12:25:34 PM PST 23
Finished Dec 24 12:25:37 PM PST 23
Peak memory 199316 kb
Host smart-223d3897-0667-4c32-9371-8ab7f54adf7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370307052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.3370307052
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.1048491046
Short name T47
Test name
Test status
Simulation time 3407093910 ps
CPU time 14.83 seconds
Started Dec 24 12:25:57 PM PST 23
Finished Dec 24 12:26:14 PM PST 23
Peak memory 199456 kb
Host smart-8b8b02a2-221a-48cf-9eb5-3ea1f432dc76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048491046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.1048491046
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.2570978281
Short name T61
Test name
Test status
Simulation time 483168747 ps
CPU time 2.58 seconds
Started Dec 24 12:27:29 PM PST 23
Finished Dec 24 12:27:34 PM PST 23
Peak memory 199136 kb
Host smart-8ca4dc45-64d9-4815-aba5-b5438072f556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570978281 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.2570978281
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.4042421602
Short name T74
Test name
Test status
Simulation time 98323474 ps
CPU time 0.99 seconds
Started Dec 24 12:27:55 PM PST 23
Finished Dec 24 12:28:08 PM PST 23
Peak memory 199380 kb
Host smart-95e90646-2eb8-44aa-be78-4dd03a4f6f0f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042421602 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.4042421602
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.63520574
Short name T76
Test name
Test status
Simulation time 16518408126 ps
CPU time 28.18 seconds
Started Dec 24 12:29:42 PM PST 23
Finished Dec 24 12:30:31 PM PST 23
Peak memory 216324 kb
Host smart-6fab4c6f-2227-4423-a25a-ed36b7257edf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63520574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.63520574
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.2697170109
Short name T35
Test name
Test status
Simulation time 2355213145 ps
CPU time 7.93 seconds
Started Dec 24 12:29:30 PM PST 23
Finished Dec 24 12:29:49 PM PST 23
Peak memory 216876 kb
Host smart-9dcf7ae9-362d-4f44-8e18-e56ab08291a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697170109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.2697170109
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.3059741518
Short name T87
Test name
Test status
Simulation time 538871503 ps
CPU time 1.97 seconds
Started Dec 24 12:26:39 PM PST 23
Finished Dec 24 12:26:45 PM PST 23
Peak memory 199528 kb
Host smart-62609f9a-b8c3-405c-b7e2-fe49dbe14f35
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059741518 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.3059741518
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.3035262125
Short name T6
Test name
Test status
Simulation time 57526522 ps
CPU time 0.7 seconds
Started Dec 24 12:24:51 PM PST 23
Finished Dec 24 12:24:57 PM PST 23
Peak memory 198996 kb
Host smart-19a8f3d0-56f4-4555-9717-08d057ea917e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035262125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.3035262125
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_reset.1892913271
Short name T7
Test name
Test status
Simulation time 920544669 ps
CPU time 4.39 seconds
Started Dec 24 12:26:53 PM PST 23
Finished Dec 24 12:27:01 PM PST 23
Peak memory 198260 kb
Host smart-ac580020-ca7b-410a-9fe1-acab2807b912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892913271 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.1892913271
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2467682019
Short name T174
Test name
Test status
Simulation time 606752939 ps
CPU time 3.72 seconds
Started Dec 24 12:27:44 PM PST 23
Finished Dec 24 12:28:00 PM PST 23
Peak memory 199584 kb
Host smart-4f3fa3dd-029c-453b-9bd0-5683cf81731b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467682019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.2467682019
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.941570833
Short name T160
Test name
Test status
Simulation time 140068523 ps
CPU time 1.03 seconds
Started Dec 24 12:28:10 PM PST 23
Finished Dec 24 12:28:25 PM PST 23
Peak memory 199312 kb
Host smart-13b1aa20-89bd-4a31-b167-094809638f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941570833 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.941570833
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.479480199
Short name T42
Test name
Test status
Simulation time 117660482 ps
CPU time 1.03 seconds
Started Dec 24 12:26:19 PM PST 23
Finished Dec 24 12:26:23 PM PST 23
Peak memory 199244 kb
Host smart-292fbecf-f681-49dd-95cc-6a5008d40963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479480199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.479480199
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.314566331
Short name T30
Test name
Test status
Simulation time 1226705706 ps
CPU time 5.47 seconds
Started Dec 24 12:30:26 PM PST 23
Finished Dec 24 12:30:55 PM PST 23
Peak memory 216596 kb
Host smart-83a02349-694a-4371-9011-e6195ecc03cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314566331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.314566331
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.1878234361
Short name T116
Test name
Test status
Simulation time 73113958 ps
CPU time 0.8 seconds
Started Dec 24 12:28:47 PM PST 23
Finished Dec 24 12:28:57 PM PST 23
Peak memory 199280 kb
Host smart-296dcfed-767e-4c96-8f12-78a763fc3159
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878234361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.1878234361
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.4010812052
Short name T239
Test name
Test status
Simulation time 831575354 ps
CPU time 2.76 seconds
Started Dec 24 12:27:33 PM PST 23
Finished Dec 24 12:27:37 PM PST 23
Peak memory 199620 kb
Host smart-3ec8aae9-b3f6-48f8-8b37-5f620ce6490b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010812052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.4010812052
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/21.rstmgr_reset.3859763454
Short name T281
Test name
Test status
Simulation time 1377914225 ps
CPU time 5.85 seconds
Started Dec 24 12:25:39 PM PST 23
Finished Dec 24 12:25:47 PM PST 23
Peak memory 199412 kb
Host smart-425f2f79-49fd-41ec-afb9-7d6cd6dba76e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859763454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.3859763454
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.1873248355
Short name T100
Test name
Test status
Simulation time 182197589 ps
CPU time 2.45 seconds
Started Dec 24 12:28:37 PM PST 23
Finished Dec 24 12:28:45 PM PST 23
Peak memory 199648 kb
Host smart-7abdeae8-a539-48df-88bc-c5323f1df1d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873248355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.1873248355
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.3979950695
Short name T17
Test name
Test status
Simulation time 165656753 ps
CPU time 0.81 seconds
Started Dec 24 12:26:34 PM PST 23
Finished Dec 24 12:26:36 PM PST 23
Peak memory 198984 kb
Host smart-41b4741f-2fe4-4d93-95cc-0a1770f3c888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979950695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.3979950695
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.732641308
Short name T124
Test name
Test status
Simulation time 1148216644 ps
CPU time 3.25 seconds
Started Dec 24 12:27:58 PM PST 23
Finished Dec 24 12:28:15 PM PST 23
Peak memory 199488 kb
Host smart-eacada8b-8435-408d-8ef5-441e34171fa8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732641308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_err
.732641308
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.3292478227
Short name T218
Test name
Test status
Simulation time 163202723 ps
CPU time 1.94 seconds
Started Dec 24 12:26:43 PM PST 23
Finished Dec 24 12:26:48 PM PST 23
Peak memory 199572 kb
Host smart-dbfd203d-29bd-4b3f-b6fa-41c33d1f46b5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292478227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.3
292478227
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3114113734
Short name T176
Test name
Test status
Simulation time 2301914833 ps
CPU time 8.86 seconds
Started Dec 24 12:29:12 PM PST 23
Finished Dec 24 12:29:23 PM PST 23
Peak memory 199416 kb
Host smart-927dad9e-b1b0-417f-aca2-d46d2caa50a4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114113734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.3
114113734
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.1100620692
Short name T230
Test name
Test status
Simulation time 129914613 ps
CPU time 0.89 seconds
Started Dec 24 12:26:43 PM PST 23
Finished Dec 24 12:26:47 PM PST 23
Peak memory 199440 kb
Host smart-f22b09bc-3301-468e-8da5-ecbafedfb6f0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100620692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.1
100620692
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.1344490470
Short name T235
Test name
Test status
Simulation time 116323016 ps
CPU time 0.98 seconds
Started Dec 24 12:26:11 PM PST 23
Finished Dec 24 12:26:14 PM PST 23
Peak memory 198844 kb
Host smart-baacde98-3acc-4091-9669-a9dea8bd452e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344490470 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.1344490470
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.1375915033
Short name T111
Test name
Test status
Simulation time 78916342 ps
CPU time 0.81 seconds
Started Dec 24 12:27:02 PM PST 23
Finished Dec 24 12:27:08 PM PST 23
Peak memory 199460 kb
Host smart-e059d627-a58a-4fa1-9430-a02f66e55ca9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375915033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.1375915033
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.4257124756
Short name T119
Test name
Test status
Simulation time 90655271 ps
CPU time 0.96 seconds
Started Dec 24 12:27:41 PM PST 23
Finished Dec 24 12:27:45 PM PST 23
Peak memory 199520 kb
Host smart-b95dc461-ef72-4375-9ded-8747a36beb3d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257124756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.4257124756
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.3081852709
Short name T67
Test name
Test status
Simulation time 418283760 ps
CPU time 1.76 seconds
Started Dec 24 12:29:33 PM PST 23
Finished Dec 24 12:29:48 PM PST 23
Peak memory 199452 kb
Host smart-e19b5f27-b09c-4b8c-b867-54c2ac2b080a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081852709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.3081852709
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.359717889
Short name T225
Test name
Test status
Simulation time 148706225 ps
CPU time 1.89 seconds
Started Dec 24 12:26:17 PM PST 23
Finished Dec 24 12:26:22 PM PST 23
Peak memory 199300 kb
Host smart-65e849ef-aa12-4a23-b0bf-c28bc7b9fe51
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359717889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.359717889
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.2259218525
Short name T212
Test name
Test status
Simulation time 1530084838 ps
CPU time 7.8 seconds
Started Dec 24 12:26:42 PM PST 23
Finished Dec 24 12:26:53 PM PST 23
Peak memory 199528 kb
Host smart-1954e5c9-1d32-4017-bdae-0caa7bd81a64
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259218525 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.2
259218525
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.2917594087
Short name T237
Test name
Test status
Simulation time 115115118 ps
CPU time 0.84 seconds
Started Dec 24 12:26:43 PM PST 23
Finished Dec 24 12:26:46 PM PST 23
Peak memory 199312 kb
Host smart-4bae007a-e697-4b3c-a2c3-34c88d106d24
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917594087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.2
917594087
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.2200788343
Short name T179
Test name
Test status
Simulation time 174369514 ps
CPU time 1.57 seconds
Started Dec 24 12:26:35 PM PST 23
Finished Dec 24 12:26:39 PM PST 23
Peak memory 215852 kb
Host smart-f796e2be-e8a6-4dc5-b1ce-7f50bfe362a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200788343 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.2200788343
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.3948605503
Short name T178
Test name
Test status
Simulation time 62198333 ps
CPU time 0.8 seconds
Started Dec 24 12:26:52 PM PST 23
Finished Dec 24 12:26:55 PM PST 23
Peak memory 199212 kb
Host smart-0b275d2b-7975-448a-8655-0b2ad8017741
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948605503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.3948605503
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.3019606326
Short name T221
Test name
Test status
Simulation time 91622810 ps
CPU time 0.96 seconds
Started Dec 24 12:27:09 PM PST 23
Finished Dec 24 12:27:13 PM PST 23
Peak memory 199268 kb
Host smart-8e70d389-6ad3-407f-ace2-9b79dba8bfdc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019606326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.3019606326
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.2516366472
Short name T68
Test name
Test status
Simulation time 286833319 ps
CPU time 2.08 seconds
Started Dec 24 12:26:48 PM PST 23
Finished Dec 24 12:26:52 PM PST 23
Peak memory 207660 kb
Host smart-229c83e0-0edf-46d3-b3df-d0add8e56c2e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516366472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.2516366472
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3989497875
Short name T136
Test name
Test status
Simulation time 432114466 ps
CPU time 1.78 seconds
Started Dec 24 12:26:43 PM PST 23
Finished Dec 24 12:26:47 PM PST 23
Peak memory 199480 kb
Host smart-6f502993-93a5-41df-8d3d-336a787fad43
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989497875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.3989497875
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.270202087
Short name T99
Test name
Test status
Simulation time 176655411 ps
CPU time 1.24 seconds
Started Dec 24 12:28:03 PM PST 23
Finished Dec 24 12:28:17 PM PST 23
Peak memory 199612 kb
Host smart-cd986dd9-49a1-449c-a4ac-dafe0a22e1df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270202087 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.270202087
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.2035721837
Short name T180
Test name
Test status
Simulation time 66116030 ps
CPU time 0.78 seconds
Started Dec 24 12:28:47 PM PST 23
Finished Dec 24 12:28:56 PM PST 23
Peak memory 199292 kb
Host smart-425a67e0-4259-4265-84e7-f2d9810c3ed6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035721837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.2035721837
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.4233009429
Short name T232
Test name
Test status
Simulation time 120780013 ps
CPU time 1.03 seconds
Started Dec 24 12:31:11 PM PST 23
Finished Dec 24 12:31:33 PM PST 23
Peak memory 198688 kb
Host smart-7ceee503-ff21-4155-91d3-e55fb89fd0c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233009429 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.4233009429
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.4148060785
Short name T101
Test name
Test status
Simulation time 439247650 ps
CPU time 3.27 seconds
Started Dec 24 12:26:15 PM PST 23
Finished Dec 24 12:26:20 PM PST 23
Peak memory 199532 kb
Host smart-7eaa7195-8378-42d7-aefa-03cd82452da8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148060785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.4148060785
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.2572443835
Short name T228
Test name
Test status
Simulation time 800076916 ps
CPU time 2.89 seconds
Started Dec 24 12:27:34 PM PST 23
Finished Dec 24 12:27:38 PM PST 23
Peak memory 199400 kb
Host smart-47397198-1b4e-4f54-96a4-3e5ade8fe052
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572443835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.2572443835
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.189426487
Short name T103
Test name
Test status
Simulation time 109940633 ps
CPU time 0.9 seconds
Started Dec 24 12:28:50 PM PST 23
Finished Dec 24 12:29:01 PM PST 23
Peak memory 199352 kb
Host smart-6b9606ea-af1c-45ba-9b0c-a5da329f8e1b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189426487 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.189426487
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.3616605336
Short name T226
Test name
Test status
Simulation time 137522135 ps
CPU time 1.37 seconds
Started Dec 24 12:26:15 PM PST 23
Finished Dec 24 12:26:18 PM PST 23
Peak memory 199424 kb
Host smart-ba737d06-2b9e-42bb-a7ff-7a160953ae11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616605336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.3616605336
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.853051117
Short name T207
Test name
Test status
Simulation time 122689887 ps
CPU time 1.68 seconds
Started Dec 24 12:26:12 PM PST 23
Finished Dec 24 12:26:16 PM PST 23
Peak memory 199444 kb
Host smart-f3b795ff-4662-4690-b044-37ede4e1fd3b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853051117 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.853051117
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1939777614
Short name T210
Test name
Test status
Simulation time 932085520 ps
CPU time 3.29 seconds
Started Dec 24 12:27:05 PM PST 23
Finished Dec 24 12:27:13 PM PST 23
Peak memory 199576 kb
Host smart-84c2075a-9ab4-4337-b1b7-44d29a64257f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939777614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.1939777614
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.3945970595
Short name T206
Test name
Test status
Simulation time 135444073 ps
CPU time 0.96 seconds
Started Dec 24 12:27:05 PM PST 23
Finished Dec 24 12:27:11 PM PST 23
Peak memory 199416 kb
Host smart-786e7495-cf4b-47d9-9558-08dce67c38d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945970595 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.3945970595
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.1351604484
Short name T241
Test name
Test status
Simulation time 84368090 ps
CPU time 0.88 seconds
Started Dec 24 12:28:16 PM PST 23
Finished Dec 24 12:28:30 PM PST 23
Peak memory 197816 kb
Host smart-54763637-1e19-4500-99a7-a2098af47309
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351604484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.1351604484
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.4051864864
Short name T191
Test name
Test status
Simulation time 271946434 ps
CPU time 1.5 seconds
Started Dec 24 12:27:56 PM PST 23
Finished Dec 24 12:28:09 PM PST 23
Peak memory 199304 kb
Host smart-bdf7740b-035b-4a4a-9af0-a085c247a28e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051864864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.4051864864
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.2468789847
Short name T98
Test name
Test status
Simulation time 111327598 ps
CPU time 1.46 seconds
Started Dec 24 12:26:35 PM PST 23
Finished Dec 24 12:26:38 PM PST 23
Peak memory 199412 kb
Host smart-a883b310-2bba-47dc-b037-eabf66e2e531
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468789847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.2468789847
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.503504261
Short name T127
Test name
Test status
Simulation time 690912728 ps
CPU time 2.14 seconds
Started Dec 24 12:27:58 PM PST 23
Finished Dec 24 12:28:14 PM PST 23
Peak memory 199632 kb
Host smart-5222c648-5ff8-43b3-998e-eee2be1a3f7e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503504261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_err
.503504261
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.4188260583
Short name T203
Test name
Test status
Simulation time 175481646 ps
CPU time 1.71 seconds
Started Dec 24 12:29:33 PM PST 23
Finished Dec 24 12:29:50 PM PST 23
Peak memory 208000 kb
Host smart-64014186-be7b-43d4-8ce9-9541b1c49a7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188260583 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.4188260583
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.1629152587
Short name T213
Test name
Test status
Simulation time 73108423 ps
CPU time 0.74 seconds
Started Dec 24 12:26:23 PM PST 23
Finished Dec 24 12:26:27 PM PST 23
Peak memory 199088 kb
Host smart-2aa07eef-fff0-47aa-b796-67358964cf52
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629152587 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.1629152587
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2903462475
Short name T234
Test name
Test status
Simulation time 151576029 ps
CPU time 1.04 seconds
Started Dec 24 12:28:50 PM PST 23
Finished Dec 24 12:29:02 PM PST 23
Peak memory 199348 kb
Host smart-a993236d-72c8-4afd-99c4-f075490a88a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903462475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.2903462475
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.2262085195
Short name T195
Test name
Test status
Simulation time 267458816 ps
CPU time 1.71 seconds
Started Dec 24 12:27:42 PM PST 23
Finished Dec 24 12:27:51 PM PST 23
Peak memory 199636 kb
Host smart-bff5f1e1-1a3e-4841-8fc8-58377c88e349
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262085195 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.2262085195
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3563783389
Short name T185
Test name
Test status
Simulation time 409665990 ps
CPU time 1.69 seconds
Started Dec 24 12:28:47 PM PST 23
Finished Dec 24 12:28:58 PM PST 23
Peak memory 199436 kb
Host smart-67650995-5856-4024-a377-467b5cebfa0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563783389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.3563783389
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.3578139701
Short name T209
Test name
Test status
Simulation time 145907568 ps
CPU time 1.32 seconds
Started Dec 24 12:26:23 PM PST 23
Finished Dec 24 12:26:27 PM PST 23
Peak memory 198752 kb
Host smart-30379316-dd01-4424-a71f-22645b47e439
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578139701 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.3578139701
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.3928407851
Short name T182
Test name
Test status
Simulation time 69497816 ps
CPU time 0.72 seconds
Started Dec 24 12:29:56 PM PST 23
Finished Dec 24 12:30:23 PM PST 23
Peak memory 199320 kb
Host smart-9c1b1f5e-d72f-4021-afa0-93f93a55bed2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928407851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.3928407851
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.21821781
Short name T227
Test name
Test status
Simulation time 111689468 ps
CPU time 1.23 seconds
Started Dec 24 12:28:50 PM PST 23
Finished Dec 24 12:29:02 PM PST 23
Peak memory 198760 kb
Host smart-a9ba851a-3b64-4e83-ab3d-25281c2ed09b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21821781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_sam
e_csr_outstanding.21821781
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.4213658237
Short name T175
Test name
Test status
Simulation time 146572625 ps
CPU time 1.83 seconds
Started Dec 24 12:27:05 PM PST 23
Finished Dec 24 12:27:11 PM PST 23
Peak memory 199572 kb
Host smart-91fcf5a9-1c17-48fc-a343-e0853b931844
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213658237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.4213658237
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.946957305
Short name T75
Test name
Test status
Simulation time 175242344 ps
CPU time 1.31 seconds
Started Dec 24 12:27:05 PM PST 23
Finished Dec 24 12:27:11 PM PST 23
Peak memory 199564 kb
Host smart-7f605d56-fb73-4421-bb52-1379e20622f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946957305 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.946957305
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.956516965
Short name T117
Test name
Test status
Simulation time 70659877 ps
CPU time 0.76 seconds
Started Dec 24 12:28:50 PM PST 23
Finished Dec 24 12:29:02 PM PST 23
Peak memory 198456 kb
Host smart-4f3fc6c9-445d-4974-9d9b-8e6eb3a98e9d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956516965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.956516965
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.4091090513
Short name T231
Test name
Test status
Simulation time 85943467 ps
CPU time 1.07 seconds
Started Dec 24 12:27:11 PM PST 23
Finished Dec 24 12:27:15 PM PST 23
Peak memory 199504 kb
Host smart-b3c7dcff-0bbf-4bc0-b11d-0161a5a68967
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091090513 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.4091090513
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.1004512363
Short name T219
Test name
Test status
Simulation time 154609422 ps
CPU time 2.12 seconds
Started Dec 24 12:29:12 PM PST 23
Finished Dec 24 12:29:17 PM PST 23
Peak memory 198760 kb
Host smart-91e117ab-16e0-4260-b0cf-e3bc15f4087e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004512363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.1004512363
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3609487628
Short name T217
Test name
Test status
Simulation time 953494196 ps
CPU time 3.02 seconds
Started Dec 24 12:26:47 PM PST 23
Finished Dec 24 12:26:52 PM PST 23
Peak memory 199636 kb
Host smart-0cd6fadf-0495-4114-976e-3278902e5a62
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609487628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.3609487628
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.2847315247
Short name T223
Test name
Test status
Simulation time 145872700 ps
CPU time 1.35 seconds
Started Dec 24 12:30:04 PM PST 23
Finished Dec 24 12:30:31 PM PST 23
Peak memory 207852 kb
Host smart-40cfad0b-2598-4a3f-8253-52b11eccdcb7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847315247 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.2847315247
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.918645655
Short name T229
Test name
Test status
Simulation time 57623578 ps
CPU time 0.69 seconds
Started Dec 24 12:26:18 PM PST 23
Finished Dec 24 12:26:21 PM PST 23
Peak memory 199324 kb
Host smart-5e9a13c0-6832-4b86-a4b6-ee8de6268465
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918645655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.918645655
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3940822432
Short name T120
Test name
Test status
Simulation time 83738419 ps
CPU time 0.93 seconds
Started Dec 24 12:27:50 PM PST 23
Finished Dec 24 12:28:00 PM PST 23
Peak memory 199360 kb
Host smart-1f6c6d17-c468-4231-b610-ffe78047c8ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940822432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.3940822432
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.2573076164
Short name T222
Test name
Test status
Simulation time 505400679 ps
CPU time 3.3 seconds
Started Dec 24 12:27:33 PM PST 23
Finished Dec 24 12:27:38 PM PST 23
Peak memory 199532 kb
Host smart-161bd155-facf-4ee4-9861-43b28ba2f818
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573076164 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.2573076164
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3180034563
Short name T198
Test name
Test status
Simulation time 136689083 ps
CPU time 1.17 seconds
Started Dec 24 12:27:56 PM PST 23
Finished Dec 24 12:28:09 PM PST 23
Peak memory 199516 kb
Host smart-dd55e6c6-4c69-4737-8e2f-757162813b32
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180034563 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.3180034563
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.3266162936
Short name T211
Test name
Test status
Simulation time 57482016 ps
CPU time 0.82 seconds
Started Dec 24 12:26:35 PM PST 23
Finished Dec 24 12:26:37 PM PST 23
Peak memory 199252 kb
Host smart-53b96b20-c53e-42e1-b360-6961255c538f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266162936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.3266162936
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.870313397
Short name T63
Test name
Test status
Simulation time 81913334 ps
CPU time 1 seconds
Started Dec 24 12:26:17 PM PST 23
Finished Dec 24 12:26:21 PM PST 23
Peak memory 199512 kb
Host smart-4a834b89-cb30-4636-9dad-dccbd93f5584
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870313397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_sa
me_csr_outstanding.870313397
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.2844255543
Short name T172
Test name
Test status
Simulation time 124068868 ps
CPU time 1.05 seconds
Started Dec 24 12:27:54 PM PST 23
Finished Dec 24 12:28:04 PM PST 23
Peak memory 199624 kb
Host smart-3b1ee821-4e45-4e4f-a35a-ae8eb328422c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844255543 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.2844255543
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.3335364432
Short name T104
Test name
Test status
Simulation time 77495735 ps
CPU time 0.74 seconds
Started Dec 24 12:29:15 PM PST 23
Finished Dec 24 12:29:29 PM PST 23
Peak memory 198584 kb
Host smart-60413c54-bb2c-48fa-a6b2-5c8f91fd322c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335364432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.3335364432
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.1081210252
Short name T64
Test name
Test status
Simulation time 81538785 ps
CPU time 0.91 seconds
Started Dec 24 12:29:14 PM PST 23
Finished Dec 24 12:29:20 PM PST 23
Peak memory 199112 kb
Host smart-84c2a3f2-5dbc-495d-bcf9-9bd865447869
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081210252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.1081210252
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.30709418
Short name T243
Test name
Test status
Simulation time 201786386 ps
CPU time 3 seconds
Started Dec 24 12:26:16 PM PST 23
Finished Dec 24 12:26:22 PM PST 23
Peak memory 199600 kb
Host smart-d6e177eb-95d8-4754-b4e4-cec77a77af2d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30709418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.30709418
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.3748639248
Short name T197
Test name
Test status
Simulation time 626784981 ps
CPU time 2.26 seconds
Started Dec 24 12:26:22 PM PST 23
Finished Dec 24 12:26:26 PM PST 23
Peak memory 198964 kb
Host smart-9d6ba643-65da-4206-8a17-54e86b841f58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748639248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.3748639248
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.328073299
Short name T168
Test name
Test status
Simulation time 182373356 ps
CPU time 1.24 seconds
Started Dec 24 12:29:37 PM PST 23
Finished Dec 24 12:29:56 PM PST 23
Peak memory 199508 kb
Host smart-c7e70326-b004-4cdd-bed4-f569551dc629
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328073299 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.328073299
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2231863355
Short name T177
Test name
Test status
Simulation time 87873213 ps
CPU time 0.86 seconds
Started Dec 24 12:26:19 PM PST 23
Finished Dec 24 12:26:22 PM PST 23
Peak memory 199432 kb
Host smart-d09d2f12-0036-4db7-86bc-7f78bb2bd4a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231863355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.2231863355
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.3092652917
Short name T194
Test name
Test status
Simulation time 100414501 ps
CPU time 1.2 seconds
Started Dec 24 12:27:57 PM PST 23
Finished Dec 24 12:28:12 PM PST 23
Peak memory 199552 kb
Host smart-6e7d655d-0f11-4738-b4e6-65aea220a69d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092652917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.3092652917
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.2180274531
Short name T215
Test name
Test status
Simulation time 196772936 ps
CPU time 1.46 seconds
Started Dec 24 12:26:22 PM PST 23
Finished Dec 24 12:26:26 PM PST 23
Peak memory 198840 kb
Host smart-c6f3767e-efc9-4b93-9799-25aa2d584e8e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180274531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.2180274531
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.2585592570
Short name T125
Test name
Test status
Simulation time 772168205 ps
CPU time 2.63 seconds
Started Dec 24 12:29:45 PM PST 23
Finished Dec 24 12:30:09 PM PST 23
Peak memory 199516 kb
Host smart-3e7b245d-04fe-48dc-ab04-94076ce0e102
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585592570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.2585592570
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.1644096002
Short name T238
Test name
Test status
Simulation time 465873772 ps
CPU time 2.4 seconds
Started Dec 24 12:29:30 PM PST 23
Finished Dec 24 12:29:45 PM PST 23
Peak memory 199492 kb
Host smart-cb2c2574-43b1-4a8e-a19b-216fe1a6a6fc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644096002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.1
644096002
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.108288680
Short name T216
Test name
Test status
Simulation time 1176875128 ps
CPU time 5.18 seconds
Started Dec 24 12:28:53 PM PST 23
Finished Dec 24 12:29:09 PM PST 23
Peak memory 198608 kb
Host smart-943a7f93-04a3-4e20-9c78-d668e7f1ef66
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108288680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.108288680
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1925617995
Short name T201
Test name
Test status
Simulation time 88149534 ps
CPU time 0.77 seconds
Started Dec 24 12:26:57 PM PST 23
Finished Dec 24 12:27:00 PM PST 23
Peak memory 199108 kb
Host smart-77a4fb74-8533-464c-bced-deea5ff91350
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925617995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.1
925617995
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.4109047221
Short name T233
Test name
Test status
Simulation time 117987017 ps
CPU time 1.24 seconds
Started Dec 24 12:26:19 PM PST 23
Finished Dec 24 12:26:22 PM PST 23
Peak memory 199628 kb
Host smart-81648836-e153-4129-8937-8171bc15af94
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109047221 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.4109047221
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.4161771416
Short name T62
Test name
Test status
Simulation time 89528058 ps
CPU time 0.82 seconds
Started Dec 24 12:27:00 PM PST 23
Finished Dec 24 12:27:07 PM PST 23
Peak memory 199444 kb
Host smart-eb3c36d2-3fd1-4b0a-b567-5df3505ff8c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161771416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.4161771416
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.257613541
Short name T186
Test name
Test status
Simulation time 82367997 ps
CPU time 0.99 seconds
Started Dec 24 12:26:03 PM PST 23
Finished Dec 24 12:26:09 PM PST 23
Peak memory 199388 kb
Host smart-5d54c0f7-9b93-4595-9bdf-b768a9bab355
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257613541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sam
e_csr_outstanding.257613541
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.1201014637
Short name T66
Test name
Test status
Simulation time 376740909 ps
CPU time 2.81 seconds
Started Dec 24 12:26:11 PM PST 23
Finished Dec 24 12:26:16 PM PST 23
Peak memory 199436 kb
Host smart-4794f074-889a-4eaf-a32b-da00401f178c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201014637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.1201014637
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1454065530
Short name T123
Test name
Test status
Simulation time 793662802 ps
CPU time 2.7 seconds
Started Dec 24 12:29:32 PM PST 23
Finished Dec 24 12:29:49 PM PST 23
Peak memory 199556 kb
Host smart-4a097f56-b2e1-4676-a7e3-36633fa50b03
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454065530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.1454065530
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.2732557853
Short name T181
Test name
Test status
Simulation time 111065022 ps
CPU time 1.23 seconds
Started Dec 24 12:27:32 PM PST 23
Finished Dec 24 12:27:35 PM PST 23
Peak memory 199456 kb
Host smart-52ff70a6-5c9e-4ba7-823d-a8fc3d2fbe1b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732557853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.2
732557853
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2550183718
Short name T196
Test name
Test status
Simulation time 484650176 ps
CPU time 5.31 seconds
Started Dec 24 12:28:50 PM PST 23
Finished Dec 24 12:29:14 PM PST 23
Peak memory 199200 kb
Host smart-7167648e-d0e5-4ef2-a542-719aefca73c5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550183718 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.2
550183718
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1486105838
Short name T205
Test name
Test status
Simulation time 144192061 ps
CPU time 0.86 seconds
Started Dec 24 12:29:28 PM PST 23
Finished Dec 24 12:29:40 PM PST 23
Peak memory 199280 kb
Host smart-d2b7230f-2946-411d-a65e-3f052cbe8c77
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486105838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.1
486105838
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.3899162025
Short name T102
Test name
Test status
Simulation time 126659442 ps
CPU time 1.11 seconds
Started Dec 24 12:26:47 PM PST 23
Finished Dec 24 12:26:49 PM PST 23
Peak memory 199528 kb
Host smart-75f650f4-6c0e-474b-b71c-9e2337ea7038
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899162025 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.3899162025
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.127067675
Short name T105
Test name
Test status
Simulation time 72820386 ps
CPU time 0.74 seconds
Started Dec 24 12:29:35 PM PST 23
Finished Dec 24 12:29:57 PM PST 23
Peak memory 199452 kb
Host smart-c5cfd024-cfbf-4eed-a591-a282edbe0915
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127067675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.127067675
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.933470042
Short name T118
Test name
Test status
Simulation time 106160998 ps
CPU time 1.16 seconds
Started Dec 24 12:29:35 PM PST 23
Finished Dec 24 12:29:50 PM PST 23
Peak memory 199540 kb
Host smart-cd0bdcd8-724a-4bf9-96d6-4a11c915a632
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933470042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sam
e_csr_outstanding.933470042
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.2680684893
Short name T188
Test name
Test status
Simulation time 231412909 ps
CPU time 3.25 seconds
Started Dec 24 12:26:56 PM PST 23
Finished Dec 24 12:27:03 PM PST 23
Peak memory 199368 kb
Host smart-b03409da-8eff-4f8a-a1ee-f4be85280f2d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680684893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.2680684893
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.1026137764
Short name T208
Test name
Test status
Simulation time 475734944 ps
CPU time 1.85 seconds
Started Dec 24 12:26:03 PM PST 23
Finished Dec 24 12:26:10 PM PST 23
Peak memory 199532 kb
Host smart-7225b04a-572f-4316-b7fd-355d49c24cf9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026137764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.1026137764
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.2756835639
Short name T173
Test name
Test status
Simulation time 102533197 ps
CPU time 1.21 seconds
Started Dec 24 12:27:54 PM PST 23
Finished Dec 24 12:28:05 PM PST 23
Peak memory 199380 kb
Host smart-7cc339a0-569d-4b4e-81ed-8d2b2b404dfc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756835639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.2
756835639
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.869894359
Short name T214
Test name
Test status
Simulation time 274610309 ps
CPU time 3.29 seconds
Started Dec 24 12:27:27 PM PST 23
Finished Dec 24 12:27:33 PM PST 23
Peak memory 199544 kb
Host smart-3bf79146-4cea-4a75-8869-10d10750fbfd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869894359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.869894359
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.3174229724
Short name T200
Test name
Test status
Simulation time 148480855 ps
CPU time 0.93 seconds
Started Dec 24 12:29:35 PM PST 23
Finished Dec 24 12:29:50 PM PST 23
Peak memory 199420 kb
Host smart-1c739a25-8798-4b15-9361-ac22cea84271
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174229724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.3
174229724
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.99226733
Short name T190
Test name
Test status
Simulation time 118291559 ps
CPU time 1.01 seconds
Started Dec 24 12:27:42 PM PST 23
Finished Dec 24 12:27:50 PM PST 23
Peak memory 199560 kb
Host smart-9edcd3c6-64ae-4d03-8f93-7f6fd916ac0b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99226733 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.99226733
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.2702767538
Short name T187
Test name
Test status
Simulation time 89986955 ps
CPU time 0.91 seconds
Started Dec 24 12:26:23 PM PST 23
Finished Dec 24 12:26:27 PM PST 23
Peak memory 199296 kb
Host smart-e3dcd03a-5e38-4f9b-8590-2752caf41ef3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702767538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.2702767538
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.3835496525
Short name T202
Test name
Test status
Simulation time 94494723 ps
CPU time 1.16 seconds
Started Dec 24 12:28:37 PM PST 23
Finished Dec 24 12:28:44 PM PST 23
Peak memory 199556 kb
Host smart-6d43fdd8-193e-48a8-9038-ff7527ae8fc3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835496525 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.3835496525
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.1847134996
Short name T192
Test name
Test status
Simulation time 461122584 ps
CPU time 3.4 seconds
Started Dec 24 12:28:50 PM PST 23
Finished Dec 24 12:29:05 PM PST 23
Peak memory 199176 kb
Host smart-6244477d-461f-465f-a351-91c352e81c2a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847134996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.1847134996
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.1879145073
Short name T88
Test name
Test status
Simulation time 1049121249 ps
CPU time 3.06 seconds
Started Dec 24 12:28:09 PM PST 23
Finished Dec 24 12:28:26 PM PST 23
Peak memory 199580 kb
Host smart-9951b5de-5f61-461c-919c-ddfe7081dc3f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879145073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.1879145073
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.1964575214
Short name T193
Test name
Test status
Simulation time 115367134 ps
CPU time 0.9 seconds
Started Dec 24 12:28:38 PM PST 23
Finished Dec 24 12:28:45 PM PST 23
Peak memory 199620 kb
Host smart-5f8163c0-f904-4289-84d4-59fb29d02b19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964575214 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.1964575214
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.800140610
Short name T170
Test name
Test status
Simulation time 79120970 ps
CPU time 0.81 seconds
Started Dec 24 12:26:12 PM PST 23
Finished Dec 24 12:26:15 PM PST 23
Peak memory 199424 kb
Host smart-d5557f27-3d1c-4022-8391-778bbf69ec81
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800140610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.800140610
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.1696018094
Short name T224
Test name
Test status
Simulation time 122245373 ps
CPU time 1.04 seconds
Started Dec 24 12:27:55 PM PST 23
Finished Dec 24 12:28:07 PM PST 23
Peak memory 199396 kb
Host smart-7723aa32-9b57-43b1-b281-ce0af820fe72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696018094 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.1696018094
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.3587044514
Short name T69
Test name
Test status
Simulation time 175694666 ps
CPU time 2.26 seconds
Started Dec 24 12:30:00 PM PST 23
Finished Dec 24 12:30:29 PM PST 23
Peak memory 199660 kb
Host smart-4167fbc1-09b2-474d-93b8-b7ecc5e67cb3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587044514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.3587044514
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.2934140473
Short name T199
Test name
Test status
Simulation time 468456264 ps
CPU time 2.05 seconds
Started Dec 24 12:27:04 PM PST 23
Finished Dec 24 12:27:10 PM PST 23
Peak memory 199596 kb
Host smart-0da0f68a-717b-462e-ba1a-3a5e833426e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934140473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.2934140473
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.3160492418
Short name T204
Test name
Test status
Simulation time 61855810 ps
CPU time 0.78 seconds
Started Dec 24 12:27:58 PM PST 23
Finished Dec 24 12:28:12 PM PST 23
Peak memory 199452 kb
Host smart-cde761f0-1eb5-4bfe-a986-4ef2c23ee8cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160492418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.3160492418
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.1308587413
Short name T189
Test name
Test status
Simulation time 87897781 ps
CPU time 0.99 seconds
Started Dec 24 12:27:43 PM PST 23
Finished Dec 24 12:27:50 PM PST 23
Peak memory 199500 kb
Host smart-c2b04fd0-db70-405c-8a46-c241fa7baad5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308587413 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.1308587413
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.3715784450
Short name T169
Test name
Test status
Simulation time 271406944 ps
CPU time 2.08 seconds
Started Dec 24 12:28:00 PM PST 23
Finished Dec 24 12:28:16 PM PST 23
Peak memory 207832 kb
Host smart-6c3614af-bd7f-448b-9753-f4a5b42099ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715784450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.3715784450
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.2679014624
Short name T121
Test name
Test status
Simulation time 816535880 ps
CPU time 2.71 seconds
Started Dec 24 12:27:51 PM PST 23
Finished Dec 24 12:28:02 PM PST 23
Peak memory 199596 kb
Host smart-18989a32-0408-4667-8e6b-ebe2a1dbd46f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679014624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.2679014624
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.1722353107
Short name T236
Test name
Test status
Simulation time 92022813 ps
CPU time 0.85 seconds
Started Dec 24 12:26:55 PM PST 23
Finished Dec 24 12:26:59 PM PST 23
Peak memory 199556 kb
Host smart-b4465845-cacf-4ba8-9eed-bdd8dcf2785a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722353107 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.1722353107
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.683766627
Short name T183
Test name
Test status
Simulation time 60655119 ps
CPU time 0.71 seconds
Started Dec 24 12:30:20 PM PST 23
Finished Dec 24 12:30:43 PM PST 23
Peak memory 199272 kb
Host smart-b4261b60-4afb-424a-b764-79f29d4428da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683766627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.683766627
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3781663276
Short name T240
Test name
Test status
Simulation time 112541236 ps
CPU time 1.27 seconds
Started Dec 24 12:28:34 PM PST 23
Finished Dec 24 12:28:43 PM PST 23
Peak memory 199408 kb
Host smart-542c97ca-15ea-49f6-b232-c2a83d9ac4dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781663276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.3781663276
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.1507196981
Short name T106
Test name
Test status
Simulation time 145691652 ps
CPU time 1.99 seconds
Started Dec 24 12:26:54 PM PST 23
Finished Dec 24 12:26:59 PM PST 23
Peak memory 199456 kb
Host smart-a0ffb2cc-0cf5-4c64-896d-4f96f34c4ba4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507196981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.1507196981
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.1319130488
Short name T126
Test name
Test status
Simulation time 889495178 ps
CPU time 2.93 seconds
Started Dec 24 12:27:30 PM PST 23
Finished Dec 24 12:27:35 PM PST 23
Peak memory 199600 kb
Host smart-451198bf-a770-4f56-8473-979b912eaaf9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319130488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.1319130488
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1296734603
Short name T171
Test name
Test status
Simulation time 94956763 ps
CPU time 0.96 seconds
Started Dec 24 12:28:06 PM PST 23
Finished Dec 24 12:28:19 PM PST 23
Peak memory 199380 kb
Host smart-40a26362-d502-4518-9ec1-c3d38de714c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296734603 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.1296734603
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.1647575607
Short name T132
Test name
Test status
Simulation time 70405458 ps
CPU time 0.73 seconds
Started Dec 24 12:27:30 PM PST 23
Finished Dec 24 12:27:33 PM PST 23
Peak memory 199324 kb
Host smart-e0aa8b31-a3f9-40fa-9c08-e81efbc42310
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647575607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.1647575607
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.4058675267
Short name T242
Test name
Test status
Simulation time 153688816 ps
CPU time 1.15 seconds
Started Dec 24 12:26:08 PM PST 23
Finished Dec 24 12:26:12 PM PST 23
Peak memory 199320 kb
Host smart-08e20cbc-a573-4b54-ab97-d47e0d293b88
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058675267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.4058675267
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.3026907280
Short name T128
Test name
Test status
Simulation time 165659524 ps
CPU time 2.25 seconds
Started Dec 24 12:30:02 PM PST 23
Finished Dec 24 12:30:29 PM PST 23
Peak memory 199584 kb
Host smart-dcf432b4-4379-48e1-9375-f4215d79f288
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026907280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.3026907280
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.2138208762
Short name T122
Test name
Test status
Simulation time 782960841 ps
CPU time 2.69 seconds
Started Dec 24 12:29:15 PM PST 23
Finished Dec 24 12:29:22 PM PST 23
Peak memory 198732 kb
Host smart-8bc63dd4-5530-45d9-a981-4e44d091370a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138208762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.2138208762
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.4147081333
Short name T107
Test name
Test status
Simulation time 108565743 ps
CPU time 0.86 seconds
Started Dec 24 12:27:47 PM PST 23
Finished Dec 24 12:27:58 PM PST 23
Peak memory 199472 kb
Host smart-cfbc6652-cb04-4c06-9e13-e29031cd04f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147081333 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.4147081333
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.3997067888
Short name T184
Test name
Test status
Simulation time 76654373 ps
CPU time 0.82 seconds
Started Dec 24 12:29:01 PM PST 23
Finished Dec 24 12:29:13 PM PST 23
Peak memory 198604 kb
Host smart-2e5c6acc-26fb-4d8b-98f1-f11f9ee7ca8a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997067888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.3997067888
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.715132426
Short name T108
Test name
Test status
Simulation time 235208888 ps
CPU time 1.48 seconds
Started Dec 24 12:28:35 PM PST 23
Finished Dec 24 12:28:43 PM PST 23
Peak memory 199548 kb
Host smart-8370b42c-3cc4-4e6f-b130-cd4f8d461446
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715132426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sam
e_csr_outstanding.715132426
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.1804904624
Short name T220
Test name
Test status
Simulation time 432748769 ps
CPU time 3.14 seconds
Started Dec 24 12:26:12 PM PST 23
Finished Dec 24 12:26:18 PM PST 23
Peak memory 199512 kb
Host smart-3b6778fa-a225-4e99-84f3-d5a420b556fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804904624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.1804904624
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.1315966950
Short name T137
Test name
Test status
Simulation time 847331446 ps
CPU time 2.74 seconds
Started Dec 24 12:27:13 PM PST 23
Finished Dec 24 12:27:19 PM PST 23
Peak memory 199616 kb
Host smart-feb819c7-c0d8-43ab-bed6-5e3d663ecdff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315966950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.1315966950
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.650601522
Short name T446
Test name
Test status
Simulation time 66530121 ps
CPU time 0.67 seconds
Started Dec 24 12:33:10 PM PST 23
Finished Dec 24 12:33:51 PM PST 23
Peak memory 198792 kb
Host smart-a76c6d28-192d-46c2-870c-bbba849bb786
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650601522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.650601522
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.2362987752
Short name T268
Test name
Test status
Simulation time 2368632846 ps
CPU time 8.77 seconds
Started Dec 24 12:32:45 PM PST 23
Finished Dec 24 12:33:22 PM PST 23
Peak memory 215748 kb
Host smart-ccb47669-676d-449b-931b-bf8089420d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362987752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.2362987752
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.3593148234
Short name T393
Test name
Test status
Simulation time 244704809 ps
CPU time 1.14 seconds
Started Dec 24 12:56:03 PM PST 23
Finished Dec 24 12:56:08 PM PST 23
Peak memory 216524 kb
Host smart-09441c34-4e0f-4f59-b1e0-ea64bfa49af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593148234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.3593148234
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.2481644147
Short name T504
Test name
Test status
Simulation time 89732927 ps
CPU time 0.71 seconds
Started Dec 24 12:25:34 PM PST 23
Finished Dec 24 12:25:37 PM PST 23
Peak memory 199004 kb
Host smart-c9bb8e41-52ca-4346-b368-448e7511869d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481644147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.2481644147
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.743297062
Short name T524
Test name
Test status
Simulation time 821655151 ps
CPU time 4.05 seconds
Started Dec 24 12:26:23 PM PST 23
Finished Dec 24 12:26:29 PM PST 23
Peak memory 199064 kb
Host smart-98059dfc-9e3d-4ccb-8e39-9bdd5fb1e7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743297062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.743297062
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.4200294593
Short name T315
Test name
Test status
Simulation time 138249519 ps
CPU time 1.02 seconds
Started Dec 24 12:25:28 PM PST 23
Finished Dec 24 12:25:30 PM PST 23
Peak memory 199260 kb
Host smart-5ebdb952-0ced-4627-8a6b-00690000540e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200294593 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.4200294593
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.3014314017
Short name T617
Test name
Test status
Simulation time 253744760 ps
CPU time 1.52 seconds
Started Dec 24 12:27:10 PM PST 23
Finished Dec 24 12:27:15 PM PST 23
Peak memory 198204 kb
Host smart-caf332e2-2f69-41fb-bb46-0f7317986db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014314017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.3014314017
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.4008519637
Short name T372
Test name
Test status
Simulation time 7414465670 ps
CPU time 30.09 seconds
Started Dec 24 12:25:47 PM PST 23
Finished Dec 24 12:26:20 PM PST 23
Peak memory 197644 kb
Host smart-c4bf8ee3-12c1-4c27-a5c5-b26c8a668912
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008519637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.4008519637
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.1905012253
Short name T578
Test name
Test status
Simulation time 413495381 ps
CPU time 2.32 seconds
Started Dec 24 12:25:19 PM PST 23
Finished Dec 24 12:25:22 PM PST 23
Peak memory 198856 kb
Host smart-5da60ef3-f2ec-4b43-b9c7-aa06ff7dc476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905012253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.1905012253
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.934131966
Short name T477
Test name
Test status
Simulation time 180814138 ps
CPU time 1.16 seconds
Started Dec 24 12:25:33 PM PST 23
Finished Dec 24 12:25:35 PM PST 23
Peak memory 198408 kb
Host smart-ebba6366-3f49-437c-b2e9-4a95bce55503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934131966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.934131966
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.1434015095
Short name T73
Test name
Test status
Simulation time 81409702 ps
CPU time 0.77 seconds
Started Dec 24 12:26:12 PM PST 23
Finished Dec 24 12:26:14 PM PST 23
Peak memory 198952 kb
Host smart-bdb2034a-aceb-4fef-bcdc-dcb72cabdf6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434015095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.1434015095
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.1742844711
Short name T60
Test name
Test status
Simulation time 2359089071 ps
CPU time 7.97 seconds
Started Dec 24 12:33:10 PM PST 23
Finished Dec 24 12:33:58 PM PST 23
Peak memory 216736 kb
Host smart-0a2d7f2e-40a5-474d-a603-84dfa1f318d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742844711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.1742844711
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.2239559189
Short name T55
Test name
Test status
Simulation time 244526275 ps
CPU time 1.09 seconds
Started Dec 24 12:28:33 PM PST 23
Finished Dec 24 12:28:40 PM PST 23
Peak memory 216576 kb
Host smart-6898a73f-e8a5-4e5d-80c2-166176a25c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239559189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.2239559189
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.1376327305
Short name T435
Test name
Test status
Simulation time 204327755 ps
CPU time 0.83 seconds
Started Dec 24 12:25:58 PM PST 23
Finished Dec 24 12:26:02 PM PST 23
Peak memory 198980 kb
Host smart-2a908a8b-33b6-4659-888c-59c3f1db5cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376327305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.1376327305
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.1375869762
Short name T517
Test name
Test status
Simulation time 1277753742 ps
CPU time 4.88 seconds
Started Dec 24 12:33:30 PM PST 23
Finished Dec 24 12:34:10 PM PST 23
Peak memory 199356 kb
Host smart-a17ee831-2380-472e-ae9e-28481c7be5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375869762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.1375869762
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.774513918
Short name T71
Test name
Test status
Simulation time 16511862625 ps
CPU time 29.14 seconds
Started Dec 24 12:28:50 PM PST 23
Finished Dec 24 12:29:31 PM PST 23
Peak memory 217244 kb
Host smart-90efb230-15be-4fbc-809b-97e85110ff03
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774513918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.774513918
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.3781680198
Short name T161
Test name
Test status
Simulation time 176946294 ps
CPU time 1.25 seconds
Started Dec 24 12:25:47 PM PST 23
Finished Dec 24 12:25:51 PM PST 23
Peak memory 197312 kb
Host smart-d2913566-b569-4ed4-a09c-86819096f448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781680198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.3781680198
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.1732507129
Short name T378
Test name
Test status
Simulation time 187275599 ps
CPU time 1.36 seconds
Started Dec 24 12:25:23 PM PST 23
Finished Dec 24 12:25:25 PM PST 23
Peak memory 199408 kb
Host smart-adb3e19c-0b41-45f3-9b71-3e97fad7e787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732507129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.1732507129
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.2396699240
Short name T45
Test name
Test status
Simulation time 79036434 ps
CPU time 0.76 seconds
Started Dec 24 12:23:26 PM PST 23
Finished Dec 24 12:23:27 PM PST 23
Peak memory 198992 kb
Host smart-4737b70a-2c7b-4bc9-81f4-c33afdbf1897
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396699240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.2396699240
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.2603377085
Short name T564
Test name
Test status
Simulation time 551747013 ps
CPU time 3.07 seconds
Started Dec 24 12:26:39 PM PST 23
Finished Dec 24 12:26:46 PM PST 23
Peak memory 199092 kb
Host smart-0af16ad3-1893-48cc-b939-b521f38f4b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603377085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.2603377085
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.1463759644
Short name T613
Test name
Test status
Simulation time 133327831 ps
CPU time 0.97 seconds
Started Dec 24 12:26:38 PM PST 23
Finished Dec 24 12:26:43 PM PST 23
Peak memory 199144 kb
Host smart-73899db8-2bbe-4911-b745-6423b9d32faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463759644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.1463759644
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.1698599721
Short name T141
Test name
Test status
Simulation time 89164808 ps
CPU time 0.85 seconds
Started Dec 24 12:28:05 PM PST 23
Finished Dec 24 12:28:18 PM PST 23
Peak memory 199116 kb
Host smart-d7b4e868-f645-40b1-b2c2-503b67923c88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698599721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.1698599721
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.752399827
Short name T360
Test name
Test status
Simulation time 244027168 ps
CPU time 1.05 seconds
Started Dec 24 12:26:14 PM PST 23
Finished Dec 24 12:26:18 PM PST 23
Peak memory 215976 kb
Host smart-5471a6d1-7db8-45be-a801-6dffedd82bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752399827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.752399827
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.251291796
Short name T569
Test name
Test status
Simulation time 91815303 ps
CPU time 0.77 seconds
Started Dec 24 12:26:50 PM PST 23
Finished Dec 24 12:26:52 PM PST 23
Peak memory 198752 kb
Host smart-020dc930-b55a-4332-be56-38379db5387d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251291796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.251291796
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.688578713
Short name T167
Test name
Test status
Simulation time 1294258519 ps
CPU time 5.37 seconds
Started Dec 24 12:26:21 PM PST 23
Finished Dec 24 12:26:29 PM PST 23
Peak memory 199732 kb
Host smart-8b28a29e-099f-4f8f-b1c2-d95db327c859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688578713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.688578713
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.434583528
Short name T359
Test name
Test status
Simulation time 201114825 ps
CPU time 1.52 seconds
Started Dec 24 12:24:26 PM PST 23
Finished Dec 24 12:24:33 PM PST 23
Peak memory 199348 kb
Host smart-3802f642-cc43-4598-aade-ead8bc82188a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434583528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.434583528
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.161466099
Short name T491
Test name
Test status
Simulation time 4890232787 ps
CPU time 18.39 seconds
Started Dec 24 12:26:50 PM PST 23
Finished Dec 24 12:27:10 PM PST 23
Peak memory 199204 kb
Host smart-73397e55-0dc9-4f4a-b349-bd18a8e39183
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161466099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.161466099
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.1930618734
Short name T415
Test name
Test status
Simulation time 273122612 ps
CPU time 1.88 seconds
Started Dec 24 12:27:43 PM PST 23
Finished Dec 24 12:27:55 PM PST 23
Peak memory 199168 kb
Host smart-5846715d-fb39-449f-af23-6369cbb744fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930618734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.1930618734
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.1869605497
Short name T84
Test name
Test status
Simulation time 64950805 ps
CPU time 0.75 seconds
Started Dec 24 12:23:56 PM PST 23
Finished Dec 24 12:23:58 PM PST 23
Peak memory 199000 kb
Host smart-e120de3e-acb8-4660-a95b-b226c0c3aafb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869605497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.1869605497
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.1283320359
Short name T353
Test name
Test status
Simulation time 1896413270 ps
CPU time 7.59 seconds
Started Dec 24 12:25:13 PM PST 23
Finished Dec 24 12:25:23 PM PST 23
Peak memory 220588 kb
Host smart-f5a4cc23-6be4-44e5-ac63-0835201c4f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283320359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.1283320359
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.867083808
Short name T255
Test name
Test status
Simulation time 244363121 ps
CPU time 1.07 seconds
Started Dec 24 12:24:44 PM PST 23
Finished Dec 24 12:24:46 PM PST 23
Peak memory 216360 kb
Host smart-cb451a83-22bb-44ea-96f4-17d98044480e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867083808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.867083808
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.1646459881
Short name T559
Test name
Test status
Simulation time 145790121 ps
CPU time 0.89 seconds
Started Dec 24 12:26:17 PM PST 23
Finished Dec 24 12:26:21 PM PST 23
Peak memory 199036 kb
Host smart-8f3b9df1-d200-4928-9554-1cb1bba045ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646459881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.1646459881
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.3398043635
Short name T14
Test name
Test status
Simulation time 2051346523 ps
CPU time 7.89 seconds
Started Dec 24 12:27:47 PM PST 23
Finished Dec 24 12:28:05 PM PST 23
Peak memory 199420 kb
Host smart-0467a616-07c8-440f-a016-cb7bb3a3d7f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398043635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.3398043635
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.1390574311
Short name T537
Test name
Test status
Simulation time 99194839 ps
CPU time 0.94 seconds
Started Dec 24 12:25:34 PM PST 23
Finished Dec 24 12:25:36 PM PST 23
Peak memory 199204 kb
Host smart-b335812d-cfd8-42a6-a301-86862c73be03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390574311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.1390574311
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.3328504186
Short name T407
Test name
Test status
Simulation time 117108534 ps
CPU time 1.13 seconds
Started Dec 24 12:26:48 PM PST 23
Finished Dec 24 12:26:51 PM PST 23
Peak memory 198496 kb
Host smart-00d17319-7b6e-4faa-9e36-23cce59207dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328504186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.3328504186
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.3075182928
Short name T539
Test name
Test status
Simulation time 122781515 ps
CPU time 1.04 seconds
Started Dec 24 12:23:57 PM PST 23
Finished Dec 24 12:23:59 PM PST 23
Peak memory 198996 kb
Host smart-34ff59f2-94c6-49bb-aae8-16368901cc6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075182928 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.3075182928
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.853059745
Short name T506
Test name
Test status
Simulation time 331208542 ps
CPU time 1.96 seconds
Started Dec 24 12:29:56 PM PST 23
Finished Dec 24 12:30:25 PM PST 23
Peak memory 199092 kb
Host smart-415cf05c-fa60-40fa-9a13-df42646af529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853059745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.853059745
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.701022556
Short name T275
Test name
Test status
Simulation time 112441282 ps
CPU time 0.94 seconds
Started Dec 24 12:27:53 PM PST 23
Finished Dec 24 12:28:02 PM PST 23
Peak memory 199232 kb
Host smart-64fd2131-1124-4775-afc0-ce1c9e4404f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701022556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.701022556
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.3458855246
Short name T40
Test name
Test status
Simulation time 64481067 ps
CPU time 0.68 seconds
Started Dec 24 12:29:35 PM PST 23
Finished Dec 24 12:29:49 PM PST 23
Peak memory 199128 kb
Host smart-49d2f393-b173-4f18-a902-21ce1fd3b21a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458855246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.3458855246
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.2978015680
Short name T31
Test name
Test status
Simulation time 1219001764 ps
CPU time 5.9 seconds
Started Dec 24 12:27:11 PM PST 23
Finished Dec 24 12:27:20 PM PST 23
Peak memory 217064 kb
Host smart-a3b7301d-6acf-405c-b85f-134f1bde11d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978015680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.2978015680
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.1198662070
Short name T1
Test name
Test status
Simulation time 244291476 ps
CPU time 1.06 seconds
Started Dec 24 12:26:57 PM PST 23
Finished Dec 24 12:27:02 PM PST 23
Peak memory 216304 kb
Host smart-c0765d0a-4a87-4972-be60-7ee4984ad537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198662070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.1198662070
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_reset.3048886410
Short name T404
Test name
Test status
Simulation time 782413527 ps
CPU time 3.98 seconds
Started Dec 24 12:24:54 PM PST 23
Finished Dec 24 12:25:02 PM PST 23
Peak memory 199352 kb
Host smart-a7eacdaa-9078-45e8-8565-0b37664c8570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048886410 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.3048886410
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.267394360
Short name T23
Test name
Test status
Simulation time 176106726 ps
CPU time 1.2 seconds
Started Dec 24 12:27:00 PM PST 23
Finished Dec 24 12:27:07 PM PST 23
Peak memory 199256 kb
Host smart-b1ffc01a-66a3-4cdd-8f07-e380367b2bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267394360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.267394360
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.1360029310
Short name T436
Test name
Test status
Simulation time 199954431 ps
CPU time 1.36 seconds
Started Dec 24 12:24:15 PM PST 23
Finished Dec 24 12:24:17 PM PST 23
Peak memory 199324 kb
Host smart-79f9c096-3cb1-4ba5-bc76-b14ee09ac2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360029310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.1360029310
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.3106421093
Short name T463
Test name
Test status
Simulation time 1860798225 ps
CPU time 6.74 seconds
Started Dec 24 12:25:28 PM PST 23
Finished Dec 24 12:25:36 PM PST 23
Peak memory 199320 kb
Host smart-755ee2e0-fd6a-4f4e-baaf-64c4520f2486
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106421093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.3106421093
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.1542640013
Short name T554
Test name
Test status
Simulation time 368486954 ps
CPU time 2.14 seconds
Started Dec 24 12:26:53 PM PST 23
Finished Dec 24 12:26:58 PM PST 23
Peak memory 199212 kb
Host smart-4db625b8-99c9-4a0c-a925-8946f16a983b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542640013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.1542640013
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.3820685694
Short name T392
Test name
Test status
Simulation time 260826692 ps
CPU time 1.42 seconds
Started Dec 24 12:25:58 PM PST 23
Finished Dec 24 12:26:04 PM PST 23
Peak memory 199196 kb
Host smart-19b6c199-cfab-481b-b58a-7e34cb2b462b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820685694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.3820685694
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.3723999678
Short name T598
Test name
Test status
Simulation time 72493462 ps
CPU time 0.73 seconds
Started Dec 24 12:25:55 PM PST 23
Finished Dec 24 12:25:57 PM PST 23
Peak memory 198948 kb
Host smart-aecdb78c-e896-415f-bc66-5ae441bef15c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723999678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.3723999678
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.1797106282
Short name T611
Test name
Test status
Simulation time 1885244227 ps
CPU time 8.11 seconds
Started Dec 24 12:25:52 PM PST 23
Finished Dec 24 12:26:02 PM PST 23
Peak memory 216080 kb
Host smart-f97066e1-87cd-4d56-a57c-526b7b1a34d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797106282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.1797106282
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.3875156650
Short name T516
Test name
Test status
Simulation time 244166753 ps
CPU time 1.07 seconds
Started Dec 24 12:26:39 PM PST 23
Finished Dec 24 12:26:44 PM PST 23
Peak memory 216356 kb
Host smart-7ee7ee1a-2c13-4d49-ba09-890489ae7051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875156650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.3875156650
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.3104427231
Short name T347
Test name
Test status
Simulation time 89331159 ps
CPU time 0.77 seconds
Started Dec 24 12:25:55 PM PST 23
Finished Dec 24 12:25:56 PM PST 23
Peak memory 199104 kb
Host smart-6c88b6c6-088b-496a-8925-8a6e0d9a2271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104427231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.3104427231
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.2459323727
Short name T166
Test name
Test status
Simulation time 1013630321 ps
CPU time 4.67 seconds
Started Dec 24 12:27:28 PM PST 23
Finished Dec 24 12:27:35 PM PST 23
Peak memory 199332 kb
Host smart-2ceb5c62-3e74-4db7-99eb-2a088166e1e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459323727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.2459323727
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.819392486
Short name T600
Test name
Test status
Simulation time 174696607 ps
CPU time 1.13 seconds
Started Dec 24 12:24:16 PM PST 23
Finished Dec 24 12:24:18 PM PST 23
Peak memory 199156 kb
Host smart-8d4fb927-23f6-4ab6-9fcd-70d179026dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819392486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.819392486
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.3577807715
Short name T591
Test name
Test status
Simulation time 269204336 ps
CPU time 1.51 seconds
Started Dec 24 12:27:06 PM PST 23
Finished Dec 24 12:27:12 PM PST 23
Peak memory 199324 kb
Host smart-ea27bfaf-e61d-4f37-aac3-8d4acfe824f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577807715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.3577807715
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.1493836459
Short name T577
Test name
Test status
Simulation time 14166152160 ps
CPU time 46.77 seconds
Started Dec 24 12:25:26 PM PST 23
Finished Dec 24 12:26:14 PM PST 23
Peak memory 199452 kb
Host smart-ffe26517-422b-4a0a-b92a-b70ccca3af91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493836459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.1493836459
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.2937449493
Short name T38
Test name
Test status
Simulation time 118957358 ps
CPU time 1.41 seconds
Started Dec 24 12:27:29 PM PST 23
Finished Dec 24 12:27:33 PM PST 23
Peak memory 199136 kb
Host smart-512880e5-2c24-4727-839a-c5e087999ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937449493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.2937449493
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.1766520526
Short name T134
Test name
Test status
Simulation time 207082159 ps
CPU time 1.32 seconds
Started Dec 24 12:25:30 PM PST 23
Finished Dec 24 12:25:33 PM PST 23
Peak memory 199168 kb
Host smart-276e708f-ae73-4d27-8df6-271137e8a6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766520526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.1766520526
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.1354535982
Short name T257
Test name
Test status
Simulation time 77577482 ps
CPU time 0.73 seconds
Started Dec 24 12:25:57 PM PST 23
Finished Dec 24 12:26:00 PM PST 23
Peak memory 199000 kb
Host smart-f92ec0ca-038d-47d5-bae4-3bf75934e79a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354535982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.1354535982
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.403147887
Short name T426
Test name
Test status
Simulation time 1898594494 ps
CPU time 6.57 seconds
Started Dec 24 12:29:35 PM PST 23
Finished Dec 24 12:29:56 PM PST 23
Peak memory 220616 kb
Host smart-4d54661c-a33d-4678-91db-b69631a268bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403147887 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.403147887
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.1381235229
Short name T162
Test name
Test status
Simulation time 243398473 ps
CPU time 1.12 seconds
Started Dec 24 12:25:57 PM PST 23
Finished Dec 24 12:26:00 PM PST 23
Peak memory 216336 kb
Host smart-3073ae81-4efd-4d27-952b-ab711f0e0ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381235229 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.1381235229
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.3231617624
Short name T265
Test name
Test status
Simulation time 114288560 ps
CPU time 0.8 seconds
Started Dec 24 12:24:13 PM PST 23
Finished Dec 24 12:24:15 PM PST 23
Peak memory 198980 kb
Host smart-16b28938-54c9-4492-b84e-69ce255b3b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231617624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.3231617624
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.3668106041
Short name T522
Test name
Test status
Simulation time 2021709897 ps
CPU time 6.81 seconds
Started Dec 24 12:24:08 PM PST 23
Finished Dec 24 12:24:16 PM PST 23
Peak memory 199728 kb
Host smart-7829528c-daaf-4e76-994d-5bcd2ce1524a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668106041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.3668106041
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.745928676
Short name T297
Test name
Test status
Simulation time 139361420 ps
CPU time 1.08 seconds
Started Dec 24 12:27:01 PM PST 23
Finished Dec 24 12:27:08 PM PST 23
Peak memory 198392 kb
Host smart-0584b719-f29b-45d9-88f8-da7db3d04e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745928676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.745928676
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.2058628889
Short name T420
Test name
Test status
Simulation time 122039111 ps
CPU time 1.22 seconds
Started Dec 24 12:24:55 PM PST 23
Finished Dec 24 12:24:59 PM PST 23
Peak memory 199396 kb
Host smart-b45884a5-46a1-4ef0-8269-a441e18ee879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058628889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.2058628889
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.582791933
Short name T112
Test name
Test status
Simulation time 6976580912 ps
CPU time 26.78 seconds
Started Dec 24 12:27:28 PM PST 23
Finished Dec 24 12:27:57 PM PST 23
Peak memory 199420 kb
Host smart-6bf3da34-72f3-4d4c-972d-14a410b0f114
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582791933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.582791933
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.1974861696
Short name T425
Test name
Test status
Simulation time 132369264 ps
CPU time 1.7 seconds
Started Dec 24 12:27:29 PM PST 23
Finished Dec 24 12:27:33 PM PST 23
Peak memory 199184 kb
Host smart-a9066ad0-3576-46fe-8f3a-09fde3bda90d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974861696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.1974861696
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.1968812753
Short name T563
Test name
Test status
Simulation time 125943498 ps
CPU time 1.01 seconds
Started Dec 24 12:25:52 PM PST 23
Finished Dec 24 12:25:54 PM PST 23
Peak memory 199124 kb
Host smart-1645e2f7-3804-4a6a-a027-60bb487356d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968812753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.1968812753
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.4116938193
Short name T413
Test name
Test status
Simulation time 80578194 ps
CPU time 0.78 seconds
Started Dec 24 12:24:32 PM PST 23
Finished Dec 24 12:24:37 PM PST 23
Peak memory 198972 kb
Host smart-76a68355-ea00-4951-a5e6-9faaf48cfa20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116938193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.4116938193
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.2398270662
Short name T4
Test name
Test status
Simulation time 1236918579 ps
CPU time 5.49 seconds
Started Dec 24 12:28:18 PM PST 23
Finished Dec 24 12:28:35 PM PST 23
Peak memory 214196 kb
Host smart-fed652fb-8b92-41ba-a90e-b510f62378c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398270662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.2398270662
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.1429494742
Short name T570
Test name
Test status
Simulation time 244154235 ps
CPU time 1.09 seconds
Started Dec 24 12:29:13 PM PST 23
Finished Dec 24 12:29:28 PM PST 23
Peak memory 215656 kb
Host smart-0f8b5c6f-2c37-44e8-b5da-675d5ad6946a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429494742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.1429494742
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.1162319055
Short name T300
Test name
Test status
Simulation time 138082551 ps
CPU time 0.76 seconds
Started Dec 24 12:24:57 PM PST 23
Finished Dec 24 12:25:00 PM PST 23
Peak memory 199004 kb
Host smart-9e4e2855-3a8c-4a4b-b684-64ea87a8a421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162319055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.1162319055
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.3765602212
Short name T269
Test name
Test status
Simulation time 1432498645 ps
CPU time 5.32 seconds
Started Dec 24 12:28:04 PM PST 23
Finished Dec 24 12:28:21 PM PST 23
Peak memory 199444 kb
Host smart-d8619de0-c157-4f83-af3a-a398f2cd1bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765602212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.3765602212
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.3056786141
Short name T544
Test name
Test status
Simulation time 110398661 ps
CPU time 0.98 seconds
Started Dec 24 12:26:39 PM PST 23
Finished Dec 24 12:26:44 PM PST 23
Peak memory 199240 kb
Host smart-b38b72e1-eed2-4226-a425-4455c6cebb63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056786141 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.3056786141
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.2586558045
Short name T459
Test name
Test status
Simulation time 112533382 ps
CPU time 1.2 seconds
Started Dec 24 12:25:25 PM PST 23
Finished Dec 24 12:25:27 PM PST 23
Peak memory 199732 kb
Host smart-a8a005e7-7905-4e45-86ab-215a3f6c0a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586558045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.2586558045
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.3590449200
Short name T455
Test name
Test status
Simulation time 4872477127 ps
CPU time 17.9 seconds
Started Dec 24 12:27:22 PM PST 23
Finished Dec 24 12:27:44 PM PST 23
Peak memory 199348 kb
Host smart-e4d5778d-6775-4c77-bc1a-04c6debf7597
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590449200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.3590449200
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.707310096
Short name T462
Test name
Test status
Simulation time 103357120 ps
CPU time 0.96 seconds
Started Dec 24 12:27:06 PM PST 23
Finished Dec 24 12:27:12 PM PST 23
Peak memory 198132 kb
Host smart-bdaebf9c-e9cd-4c57-8191-fd063390a43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707310096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.707310096
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.4058545050
Short name T302
Test name
Test status
Simulation time 73237902 ps
CPU time 0.74 seconds
Started Dec 24 12:25:30 PM PST 23
Finished Dec 24 12:25:32 PM PST 23
Peak memory 199088 kb
Host smart-60bf9c8e-001c-4510-8431-d3153aeaa16c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058545050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.4058545050
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.2443504736
Short name T574
Test name
Test status
Simulation time 2151663361 ps
CPU time 7.64 seconds
Started Dec 24 12:27:27 PM PST 23
Finished Dec 24 12:27:37 PM PST 23
Peak memory 218136 kb
Host smart-9dc4ec35-4cfe-4fd9-ba0a-057d6fc77f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443504736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.2443504736
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.3886460376
Short name T618
Test name
Test status
Simulation time 244440787 ps
CPU time 1.1 seconds
Started Dec 24 12:25:42 PM PST 23
Finished Dec 24 12:25:46 PM PST 23
Peak memory 216272 kb
Host smart-3aabf753-c80c-4dfb-97ac-7fe94e75385a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886460376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.3886460376
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.379017050
Short name T482
Test name
Test status
Simulation time 179030793 ps
CPU time 0.91 seconds
Started Dec 24 12:25:07 PM PST 23
Finished Dec 24 12:25:09 PM PST 23
Peak memory 199040 kb
Host smart-f45cc3fb-33f9-4882-8d91-15b367534b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379017050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.379017050
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.645783526
Short name T579
Test name
Test status
Simulation time 1778165058 ps
CPU time 6.15 seconds
Started Dec 24 12:25:35 PM PST 23
Finished Dec 24 12:25:43 PM PST 23
Peak memory 199316 kb
Host smart-1a5ae29f-e702-4113-a028-41a309c72689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645783526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.645783526
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.3673207570
Short name T384
Test name
Test status
Simulation time 148609275 ps
CPU time 1.03 seconds
Started Dec 24 12:26:35 PM PST 23
Finished Dec 24 12:26:38 PM PST 23
Peak memory 199200 kb
Host smart-36d2f705-1ed4-4782-a904-608965f909ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673207570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.3673207570
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.3173648819
Short name T594
Test name
Test status
Simulation time 205116750 ps
CPU time 1.37 seconds
Started Dec 24 12:26:47 PM PST 23
Finished Dec 24 12:26:50 PM PST 23
Peak memory 199332 kb
Host smart-baf3c8c6-018d-4cd1-a51c-1a9bc6dfb67c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173648819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.3173648819
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.1043368096
Short name T399
Test name
Test status
Simulation time 1160205799 ps
CPU time 5.39 seconds
Started Dec 24 12:29:13 PM PST 23
Finished Dec 24 12:29:22 PM PST 23
Peak memory 198360 kb
Host smart-cf47a3de-f0c1-4e56-8550-63f6eea76e60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043368096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.1043368096
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.3168109798
Short name T261
Test name
Test status
Simulation time 129534703 ps
CPU time 1.65 seconds
Started Dec 24 12:27:26 PM PST 23
Finished Dec 24 12:27:31 PM PST 23
Peak memory 199260 kb
Host smart-cbab7297-f105-4136-8099-df2c38cd9c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168109798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.3168109798
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.1150977960
Short name T39
Test name
Test status
Simulation time 298946557 ps
CPU time 1.69 seconds
Started Dec 24 12:27:20 PM PST 23
Finished Dec 24 12:27:25 PM PST 23
Peak memory 199368 kb
Host smart-9abf3126-c4bd-4222-8fdb-77ae79fdbd68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150977960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.1150977960
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.1516770096
Short name T290
Test name
Test status
Simulation time 76281395 ps
CPU time 0.75 seconds
Started Dec 24 12:25:44 PM PST 23
Finished Dec 24 12:25:47 PM PST 23
Peak memory 198988 kb
Host smart-4c7579c5-1993-4725-a250-d43fe5ce9c8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516770096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.1516770096
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.1523775307
Short name T352
Test name
Test status
Simulation time 1893426355 ps
CPU time 6.72 seconds
Started Dec 24 12:28:45 PM PST 23
Finished Dec 24 12:29:00 PM PST 23
Peak memory 217224 kb
Host smart-503ad40f-42e1-4c2a-9017-2d0659d5ed29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523775307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.1523775307
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.2990026882
Short name T148
Test name
Test status
Simulation time 243783590 ps
CPU time 1.1 seconds
Started Dec 24 12:28:51 PM PST 23
Finished Dec 24 12:29:03 PM PST 23
Peak memory 216444 kb
Host smart-442f5325-0a3e-49b0-a3d6-42b37283fd66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990026882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.2990026882
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.3718795978
Short name T277
Test name
Test status
Simulation time 132915532 ps
CPU time 0.9 seconds
Started Dec 24 12:26:03 PM PST 23
Finished Dec 24 12:26:09 PM PST 23
Peak memory 199052 kb
Host smart-a32a1f43-f926-4f42-94c7-55de127bc988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718795978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.3718795978
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.1850597284
Short name T602
Test name
Test status
Simulation time 1040917084 ps
CPU time 4.9 seconds
Started Dec 24 12:27:02 PM PST 23
Finished Dec 24 12:27:11 PM PST 23
Peak memory 199456 kb
Host smart-17374348-aa80-464c-8107-34d49ed1de93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850597284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.1850597284
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.1823243183
Short name T405
Test name
Test status
Simulation time 185655987 ps
CPU time 1.12 seconds
Started Dec 24 12:25:07 PM PST 23
Finished Dec 24 12:25:09 PM PST 23
Peak memory 199120 kb
Host smart-e5143a6f-4ae9-4ae6-a198-6c21d709f0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823243183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.1823243183
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.2429583368
Short name T437
Test name
Test status
Simulation time 249482743 ps
CPU time 1.54 seconds
Started Dec 24 12:26:15 PM PST 23
Finished Dec 24 12:26:19 PM PST 23
Peak memory 199404 kb
Host smart-f257c3f1-b2b3-476a-ac5a-99144a47ff1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429583368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.2429583368
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.3391016558
Short name T95
Test name
Test status
Simulation time 3574473622 ps
CPU time 10.94 seconds
Started Dec 24 12:29:43 PM PST 23
Finished Dec 24 12:30:14 PM PST 23
Peak memory 199460 kb
Host smart-aff654bc-5f9f-4c87-b8fd-a31d5cd9228c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391016558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.3391016558
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.4105769864
Short name T534
Test name
Test status
Simulation time 128985461 ps
CPU time 1.72 seconds
Started Dec 24 12:25:44 PM PST 23
Finished Dec 24 12:25:48 PM PST 23
Peak memory 199124 kb
Host smart-89efe499-8eea-46e2-842b-e87be55ac5ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105769864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.4105769864
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.3180666786
Short name T423
Test name
Test status
Simulation time 72609077 ps
CPU time 0.73 seconds
Started Dec 24 12:26:43 PM PST 23
Finished Dec 24 12:26:46 PM PST 23
Peak memory 199140 kb
Host smart-133e3919-a8f5-4c6b-b2be-f7f4921a44c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180666786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.3180666786
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.105121344
Short name T580
Test name
Test status
Simulation time 93272585 ps
CPU time 0.85 seconds
Started Dec 24 12:25:39 PM PST 23
Finished Dec 24 12:25:43 PM PST 23
Peak memory 198976 kb
Host smart-eb9dac56-af73-4b01-a78f-e764ea1cc8de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105121344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.105121344
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.2023887044
Short name T398
Test name
Test status
Simulation time 1900831875 ps
CPU time 7.16 seconds
Started Dec 24 12:26:14 PM PST 23
Finished Dec 24 12:26:24 PM PST 23
Peak memory 216564 kb
Host smart-3dcbc11f-157b-45d3-9ec8-103b80ec43ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023887044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.2023887044
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.1175176165
Short name T503
Test name
Test status
Simulation time 244197051 ps
CPU time 1.05 seconds
Started Dec 24 12:25:07 PM PST 23
Finished Dec 24 12:25:09 PM PST 23
Peak memory 216352 kb
Host smart-f1150ee8-51c9-4b32-ba5e-08c9be099ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175176165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.1175176165
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.831491463
Short name T21
Test name
Test status
Simulation time 118363826 ps
CPU time 0.84 seconds
Started Dec 24 12:26:51 PM PST 23
Finished Dec 24 12:26:54 PM PST 23
Peak memory 199064 kb
Host smart-f49e937c-2d0f-4e29-856c-6e135987f9f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831491463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.831491463
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.261601910
Short name T363
Test name
Test status
Simulation time 828077859 ps
CPU time 4.08 seconds
Started Dec 24 12:26:31 PM PST 23
Finished Dec 24 12:26:36 PM PST 23
Peak memory 199360 kb
Host smart-b978159c-38bb-415f-b7d2-705dfb9dc35b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261601910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.261601910
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.1014318377
Short name T409
Test name
Test status
Simulation time 180985878 ps
CPU time 1.19 seconds
Started Dec 24 12:25:40 PM PST 23
Finished Dec 24 12:25:43 PM PST 23
Peak memory 199196 kb
Host smart-e614e061-a27b-43d8-8d95-ce0c70ecf917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014318377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.1014318377
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.1036077420
Short name T443
Test name
Test status
Simulation time 112452014 ps
CPU time 1.13 seconds
Started Dec 24 12:29:35 PM PST 23
Finished Dec 24 12:29:50 PM PST 23
Peak memory 199324 kb
Host smart-679a6a5b-5081-4f8e-bd0e-07636e7a540c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036077420 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.1036077420
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.3496894610
Short name T96
Test name
Test status
Simulation time 2889808430 ps
CPU time 12.32 seconds
Started Dec 24 12:29:48 PM PST 23
Finished Dec 24 12:30:22 PM PST 23
Peak memory 199464 kb
Host smart-72358bcd-ac0f-4c0d-92fe-8715e32c92b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496894610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.3496894610
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.3472085114
Short name T497
Test name
Test status
Simulation time 351359894 ps
CPU time 1.9 seconds
Started Dec 24 12:29:50 PM PST 23
Finished Dec 24 12:30:16 PM PST 23
Peak memory 199236 kb
Host smart-9accd2f1-a68e-4b35-9d5b-1a3c1c5a4d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472085114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.3472085114
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.3093558997
Short name T365
Test name
Test status
Simulation time 60869484 ps
CPU time 0.72 seconds
Started Dec 24 12:26:28 PM PST 23
Finished Dec 24 12:26:31 PM PST 23
Peak memory 199172 kb
Host smart-5119a059-a72d-448f-97a2-07c29a5e08c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093558997 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.3093558997
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.2812006127
Short name T483
Test name
Test status
Simulation time 67273859 ps
CPU time 0.8 seconds
Started Dec 24 12:27:19 PM PST 23
Finished Dec 24 12:27:23 PM PST 23
Peak memory 197988 kb
Host smart-970b855a-123d-446f-9e4f-5ccf60e3b815
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812006127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.2812006127
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.792352279
Short name T584
Test name
Test status
Simulation time 2382217988 ps
CPU time 7.87 seconds
Started Dec 24 12:28:50 PM PST 23
Finished Dec 24 12:29:09 PM PST 23
Peak memory 217028 kb
Host smart-bcba0484-b1d8-4e63-9806-681554979496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792352279 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.792352279
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.3133873454
Short name T509
Test name
Test status
Simulation time 243651920 ps
CPU time 1.04 seconds
Started Dec 24 12:28:51 PM PST 23
Finished Dec 24 12:29:03 PM PST 23
Peak memory 216320 kb
Host smart-130f586d-1b10-488b-b18a-b27f8c9638c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133873454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.3133873454
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.1669150258
Short name T609
Test name
Test status
Simulation time 138990214 ps
CPU time 0.87 seconds
Started Dec 24 12:28:18 PM PST 23
Finished Dec 24 12:28:31 PM PST 23
Peak memory 197460 kb
Host smart-4c57bdf0-1f68-431d-9f33-a6b069bf9863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669150258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.1669150258
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.2312107359
Short name T258
Test name
Test status
Simulation time 813788502 ps
CPU time 4.09 seconds
Started Dec 24 12:26:36 PM PST 23
Finished Dec 24 12:26:42 PM PST 23
Peak memory 199444 kb
Host smart-b6a3f512-b9a8-41dd-ac6b-159157f050a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312107359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.2312107359
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.2163507434
Short name T24
Test name
Test status
Simulation time 105457329 ps
CPU time 0.98 seconds
Started Dec 24 12:26:36 PM PST 23
Finished Dec 24 12:26:39 PM PST 23
Peak memory 199260 kb
Host smart-4e72f5e6-9f53-4db9-9021-1fc99769fc03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163507434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.2163507434
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.296494676
Short name T144
Test name
Test status
Simulation time 206452490 ps
CPU time 1.35 seconds
Started Dec 24 12:27:32 PM PST 23
Finished Dec 24 12:27:35 PM PST 23
Peak memory 199384 kb
Host smart-cc103bf8-cc66-471c-95fe-cc7bec39ce77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296494676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.296494676
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.1739001892
Short name T80
Test name
Test status
Simulation time 2835056989 ps
CPU time 13.69 seconds
Started Dec 24 12:28:49 PM PST 23
Finished Dec 24 12:29:18 PM PST 23
Peak memory 199476 kb
Host smart-4e365ba9-d308-4e68-b0fe-5b0541b7bd3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739001892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.1739001892
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.495344193
Short name T298
Test name
Test status
Simulation time 490663749 ps
CPU time 2.34 seconds
Started Dec 24 12:29:50 PM PST 23
Finished Dec 24 12:30:16 PM PST 23
Peak memory 199208 kb
Host smart-9cdca504-b3b8-426b-a670-e26e1d09d587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495344193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.495344193
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.2989105571
Short name T319
Test name
Test status
Simulation time 69943447 ps
CPU time 0.79 seconds
Started Dec 24 12:27:19 PM PST 23
Finished Dec 24 12:27:23 PM PST 23
Peak memory 198012 kb
Host smart-a399e392-8b5c-4f81-8f32-6bb8fea43cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989105571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.2989105571
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.3028859904
Short name T279
Test name
Test status
Simulation time 332785302 ps
CPU time 1.42 seconds
Started Dec 24 12:26:13 PM PST 23
Finished Dec 24 12:26:17 PM PST 23
Peak memory 197000 kb
Host smart-28bcdb3b-fd3f-41fb-9cdb-7306f177e740
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028859904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.3028859904
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.2165449863
Short name T354
Test name
Test status
Simulation time 244696365 ps
CPU time 1.11 seconds
Started Dec 24 12:23:32 PM PST 23
Finished Dec 24 12:23:33 PM PST 23
Peak memory 216584 kb
Host smart-962820e1-59f8-424e-b672-b58912d74211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165449863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.2165449863
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.1208670450
Short name T9
Test name
Test status
Simulation time 122781513 ps
CPU time 0.92 seconds
Started Dec 24 12:26:13 PM PST 23
Finished Dec 24 12:26:17 PM PST 23
Peak memory 196968 kb
Host smart-accb2fdb-3bff-4b54-a5f1-637260e895e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208670450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.1208670450
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.659744592
Short name T386
Test name
Test status
Simulation time 1388337756 ps
CPU time 5.35 seconds
Started Dec 24 12:25:59 PM PST 23
Finished Dec 24 12:26:09 PM PST 23
Peak memory 199328 kb
Host smart-09a76bec-58d9-42f7-ad85-cf7523f96b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659744592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.659744592
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.2466637552
Short name T72
Test name
Test status
Simulation time 8284605059 ps
CPU time 16.04 seconds
Started Dec 24 12:33:20 PM PST 23
Finished Dec 24 12:34:14 PM PST 23
Peak memory 215924 kb
Host smart-9df53fb7-8da6-4a87-b3c6-44b14396c404
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466637552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.2466637552
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.1055046080
Short name T472
Test name
Test status
Simulation time 175865353 ps
CPU time 1.18 seconds
Started Dec 24 12:25:26 PM PST 23
Finished Dec 24 12:25:28 PM PST 23
Peak memory 199204 kb
Host smart-cef468d1-5935-4cdd-a1b5-ad5277812eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055046080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.1055046080
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.766874237
Short name T603
Test name
Test status
Simulation time 235167066 ps
CPU time 1.35 seconds
Started Dec 24 12:25:59 PM PST 23
Finished Dec 24 12:26:05 PM PST 23
Peak memory 199328 kb
Host smart-dd8be9af-c7dc-4cfe-86e9-8bd265314bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766874237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.766874237
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.4104479189
Short name T97
Test name
Test status
Simulation time 4503771716 ps
CPU time 19.06 seconds
Started Dec 24 12:30:26 PM PST 23
Finished Dec 24 12:31:10 PM PST 23
Peak memory 199356 kb
Host smart-5b40e13d-9601-4485-8a0c-5ce144bb303a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104479189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.4104479189
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.229726599
Short name T163
Test name
Test status
Simulation time 260857376 ps
CPU time 1.92 seconds
Started Dec 24 12:26:38 PM PST 23
Finished Dec 24 12:26:43 PM PST 23
Peak memory 198004 kb
Host smart-4a1dcaef-ff6e-44e4-8d52-6f0d4b420cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229726599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.229726599
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.3131675687
Short name T366
Test name
Test status
Simulation time 209407699 ps
CPU time 1.28 seconds
Started Dec 24 12:23:32 PM PST 23
Finished Dec 24 12:23:33 PM PST 23
Peak memory 199184 kb
Host smart-8281cf22-c40e-4dd2-a27f-18037c9f4ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131675687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.3131675687
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.1462891549
Short name T379
Test name
Test status
Simulation time 64980769 ps
CPU time 0.86 seconds
Started Dec 24 12:26:51 PM PST 23
Finished Dec 24 12:26:55 PM PST 23
Peak memory 197168 kb
Host smart-fac65d12-e81b-43ce-8a28-dad2f90d859b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462891549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.1462891549
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.3158804885
Short name T33
Test name
Test status
Simulation time 2162465563 ps
CPU time 7.97 seconds
Started Dec 24 12:25:25 PM PST 23
Finished Dec 24 12:25:34 PM PST 23
Peak memory 216328 kb
Host smart-03b1bc7a-d703-4704-8d22-3a0dd6874ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158804885 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.3158804885
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.3103054205
Short name T558
Test name
Test status
Simulation time 244824945 ps
CPU time 1.06 seconds
Started Dec 24 12:25:40 PM PST 23
Finished Dec 24 12:25:43 PM PST 23
Peak memory 216508 kb
Host smart-da05ecbc-440b-4ae1-89a5-eacdab0cd0a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103054205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.3103054205
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.824415716
Short name T620
Test name
Test status
Simulation time 240322205 ps
CPU time 0.92 seconds
Started Dec 24 12:29:35 PM PST 23
Finished Dec 24 12:29:49 PM PST 23
Peak memory 198980 kb
Host smart-b0d8721e-782d-4384-89f7-29578efef793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824415716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.824415716
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.3282687023
Short name T110
Test name
Test status
Simulation time 1342407272 ps
CPU time 6 seconds
Started Dec 24 12:24:58 PM PST 23
Finished Dec 24 12:25:07 PM PST 23
Peak memory 199020 kb
Host smart-3a307bbf-eb22-44f4-86ec-3c4963753e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282687023 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.3282687023
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.3119800910
Short name T340
Test name
Test status
Simulation time 147998335 ps
CPU time 1.12 seconds
Started Dec 24 12:25:34 PM PST 23
Finished Dec 24 12:25:36 PM PST 23
Peak memory 199204 kb
Host smart-a79a193a-ad88-40e5-bb72-0a4f676be1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119800910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.3119800910
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.3828857614
Short name T346
Test name
Test status
Simulation time 112664934 ps
CPU time 1.19 seconds
Started Dec 24 12:27:40 PM PST 23
Finished Dec 24 12:27:45 PM PST 23
Peak memory 199400 kb
Host smart-ead110d3-2c39-40e1-b514-21f0ae7ac321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828857614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.3828857614
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.3951121359
Short name T439
Test name
Test status
Simulation time 6673830765 ps
CPU time 22.07 seconds
Started Dec 24 12:25:55 PM PST 23
Finished Dec 24 12:26:18 PM PST 23
Peak memory 199312 kb
Host smart-4fa784ff-8715-41b9-9b28-ab4a9e9da7c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951121359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.3951121359
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.3390968012
Short name T318
Test name
Test status
Simulation time 330659647 ps
CPU time 2.39 seconds
Started Dec 24 12:26:59 PM PST 23
Finished Dec 24 12:27:06 PM PST 23
Peak memory 199036 kb
Host smart-5e1daa98-8cd3-4c4c-8c58-fab4335796c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390968012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.3390968012
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.1195919969
Short name T355
Test name
Test status
Simulation time 168198755 ps
CPU time 1.26 seconds
Started Dec 24 12:25:58 PM PST 23
Finished Dec 24 12:26:04 PM PST 23
Peak memory 199464 kb
Host smart-384801b0-2d8d-46de-9f38-fea254154eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195919969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.1195919969
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.2287463070
Short name T556
Test name
Test status
Simulation time 65820761 ps
CPU time 0.73 seconds
Started Dec 24 12:26:52 PM PST 23
Finished Dec 24 12:26:55 PM PST 23
Peak memory 198088 kb
Host smart-4caa5b15-feaa-4a5a-8d88-0b10f02f138b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287463070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.2287463070
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.804562977
Short name T389
Test name
Test status
Simulation time 1220422309 ps
CPU time 5.83 seconds
Started Dec 24 12:25:18 PM PST 23
Finished Dec 24 12:25:25 PM PST 23
Peak memory 217152 kb
Host smart-2c57d751-c62a-4c4b-927d-51f11ea995b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804562977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.804562977
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.1086180010
Short name T271
Test name
Test status
Simulation time 244030642 ps
CPU time 1.06 seconds
Started Dec 24 12:26:52 PM PST 23
Finished Dec 24 12:26:55 PM PST 23
Peak memory 216056 kb
Host smart-065175ac-e07e-44cf-a1d0-e018fd93debe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086180010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.1086180010
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.3560933589
Short name T387
Test name
Test status
Simulation time 199741778 ps
CPU time 0.89 seconds
Started Dec 24 12:26:52 PM PST 23
Finished Dec 24 12:26:55 PM PST 23
Peak memory 198656 kb
Host smart-663fcee2-074f-4079-9fd1-0885091dab54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560933589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.3560933589
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.870420919
Short name T138
Test name
Test status
Simulation time 148326084 ps
CPU time 1.08 seconds
Started Dec 24 12:27:25 PM PST 23
Finished Dec 24 12:27:30 PM PST 23
Peak memory 199212 kb
Host smart-78952357-eca5-41ec-b980-b63329ec3b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870420919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.870420919
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.4260885015
Short name T349
Test name
Test status
Simulation time 257117291 ps
CPU time 1.41 seconds
Started Dec 24 12:27:15 PM PST 23
Finished Dec 24 12:27:20 PM PST 23
Peak memory 199728 kb
Host smart-6f0a94e0-0a37-449d-ab8b-6fdce8a11853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260885015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.4260885015
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.55705690
Short name T403
Test name
Test status
Simulation time 1428115568 ps
CPU time 6.46 seconds
Started Dec 24 12:26:51 PM PST 23
Finished Dec 24 12:27:01 PM PST 23
Peak memory 197580 kb
Host smart-a7d92f4b-f599-4d6f-87b4-3ac21e507b21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55705690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.55705690
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.3635957702
Short name T568
Test name
Test status
Simulation time 268833184 ps
CPU time 1.8 seconds
Started Dec 24 12:25:49 PM PST 23
Finished Dec 24 12:25:52 PM PST 23
Peak memory 199432 kb
Host smart-6d79b4c3-83a5-4cfe-a877-9a01b82f78ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635957702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.3635957702
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.3573959061
Short name T260
Test name
Test status
Simulation time 140832827 ps
CPU time 1.02 seconds
Started Dec 24 12:26:51 PM PST 23
Finished Dec 24 12:26:55 PM PST 23
Peak memory 198012 kb
Host smart-c1279f69-1624-47e4-a4f4-e8797ede8f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573959061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.3573959061
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.3886946971
Short name T370
Test name
Test status
Simulation time 65405926 ps
CPU time 0.77 seconds
Started Dec 24 12:25:07 PM PST 23
Finished Dec 24 12:25:09 PM PST 23
Peak memory 198956 kb
Host smart-9e17236e-1da2-4e42-89ef-e0a7596726f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886946971 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.3886946971
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.669295559
Short name T52
Test name
Test status
Simulation time 2174681636 ps
CPU time 7.67 seconds
Started Dec 24 12:26:03 PM PST 23
Finished Dec 24 12:26:16 PM PST 23
Peak memory 217052 kb
Host smart-813220ed-17e2-4616-917b-bac0d83bdc3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669295559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.669295559
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.1090487825
Short name T356
Test name
Test status
Simulation time 244030601 ps
CPU time 1.19 seconds
Started Dec 24 12:25:15 PM PST 23
Finished Dec 24 12:25:17 PM PST 23
Peak memory 216204 kb
Host smart-7b35e1d7-a553-4cd9-872c-4f48fe2e7f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090487825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.1090487825
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.1760179607
Short name T531
Test name
Test status
Simulation time 102327211 ps
CPU time 0.76 seconds
Started Dec 24 12:25:20 PM PST 23
Finished Dec 24 12:25:21 PM PST 23
Peak memory 198748 kb
Host smart-2cc847e5-bf10-4fde-a2e9-a8dd91f800c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760179607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.1760179607
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.412804830
Short name T296
Test name
Test status
Simulation time 912614358 ps
CPU time 4.4 seconds
Started Dec 24 12:25:40 PM PST 23
Finished Dec 24 12:25:47 PM PST 23
Peak memory 199404 kb
Host smart-f3833dc1-12b0-4104-9c82-5b5abcc4fc4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412804830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.412804830
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.3404872748
Short name T388
Test name
Test status
Simulation time 146373882 ps
CPU time 1.05 seconds
Started Dec 24 12:25:38 PM PST 23
Finished Dec 24 12:25:42 PM PST 23
Peak memory 199076 kb
Host smart-39deb628-76ee-4fc0-a410-3d5f0a24bc88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404872748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.3404872748
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.4129458717
Short name T369
Test name
Test status
Simulation time 124028259 ps
CPU time 1.1 seconds
Started Dec 24 12:25:36 PM PST 23
Finished Dec 24 12:25:40 PM PST 23
Peak memory 199084 kb
Host smart-1dc29b5e-ecc5-4ec6-a1a0-c141525192a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129458717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.4129458717
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.3410202099
Short name T479
Test name
Test status
Simulation time 3351013994 ps
CPU time 16.19 seconds
Started Dec 24 12:26:51 PM PST 23
Finished Dec 24 12:27:10 PM PST 23
Peak memory 197804 kb
Host smart-2520b646-e346-47ec-ac6c-1055bc7bae4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410202099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.3410202099
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.849544300
Short name T145
Test name
Test status
Simulation time 109160315 ps
CPU time 1.38 seconds
Started Dec 24 12:25:49 PM PST 23
Finished Dec 24 12:25:52 PM PST 23
Peak memory 198764 kb
Host smart-2e3d00a7-c946-4ee9-b5c1-fd2db247d280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849544300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.849544300
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.486648624
Short name T549
Test name
Test status
Simulation time 184150059 ps
CPU time 1.22 seconds
Started Dec 24 12:26:17 PM PST 23
Finished Dec 24 12:26:21 PM PST 23
Peak memory 199172 kb
Host smart-cc08855f-21f2-48b2-8fb9-40318a50e8d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486648624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.486648624
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.2372870162
Short name T381
Test name
Test status
Simulation time 55616250 ps
CPU time 0.7 seconds
Started Dec 24 12:25:17 PM PST 23
Finished Dec 24 12:25:19 PM PST 23
Peak memory 198992 kb
Host smart-20fd7c4d-d7bd-4701-bdb2-0c3736f1ab9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372870162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.2372870162
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.853224451
Short name T523
Test name
Test status
Simulation time 2157965618 ps
CPU time 9.29 seconds
Started Dec 24 12:24:39 PM PST 23
Finished Dec 24 12:24:49 PM PST 23
Peak memory 220684 kb
Host smart-90b1dbb2-ff6b-4340-a29a-ca9f0bcbb0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853224451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.853224451
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.1573360058
Short name T301
Test name
Test status
Simulation time 244533110 ps
CPU time 1.24 seconds
Started Dec 24 12:25:55 PM PST 23
Finished Dec 24 12:25:57 PM PST 23
Peak memory 216196 kb
Host smart-d0e402a9-6e59-4f4d-b505-97b0f42479dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573360058 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.1573360058
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.2948006689
Short name T502
Test name
Test status
Simulation time 176704686 ps
CPU time 0.89 seconds
Started Dec 24 12:25:38 PM PST 23
Finished Dec 24 12:25:42 PM PST 23
Peak memory 198968 kb
Host smart-263aca41-896c-4388-be45-04d57b7920e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948006689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.2948006689
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.2664758763
Short name T528
Test name
Test status
Simulation time 1432325835 ps
CPU time 5.44 seconds
Started Dec 24 12:26:25 PM PST 23
Finished Dec 24 12:26:33 PM PST 23
Peak memory 199232 kb
Host smart-a25716c9-e533-422b-a3b5-82b99a54da34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664758763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.2664758763
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.764199185
Short name T317
Test name
Test status
Simulation time 110330678 ps
CPU time 1.01 seconds
Started Dec 24 12:25:05 PM PST 23
Finished Dec 24 12:25:07 PM PST 23
Peak memory 199100 kb
Host smart-9c9c251a-24f4-4a68-931f-26aecdfad549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764199185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.764199185
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.2198542357
Short name T135
Test name
Test status
Simulation time 247902462 ps
CPU time 1.39 seconds
Started Dec 24 12:26:25 PM PST 23
Finished Dec 24 12:26:29 PM PST 23
Peak memory 199232 kb
Host smart-e65b9519-5804-4d28-942c-203c43196325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198542357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.2198542357
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.4131110888
Short name T345
Test name
Test status
Simulation time 5580158492 ps
CPU time 19.08 seconds
Started Dec 24 12:24:36 PM PST 23
Finished Dec 24 12:24:57 PM PST 23
Peak memory 199296 kb
Host smart-01457be5-854a-4582-8c98-f87afe4aa0fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131110888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.4131110888
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.75585712
Short name T583
Test name
Test status
Simulation time 131194976 ps
CPU time 1.65 seconds
Started Dec 24 12:26:25 PM PST 23
Finished Dec 24 12:26:35 PM PST 23
Peak memory 199384 kb
Host smart-00674827-cb89-4d53-b4bd-afd3a7d84536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75585712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.75585712
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.3576768129
Short name T395
Test name
Test status
Simulation time 207326946 ps
CPU time 1.34 seconds
Started Dec 24 12:25:06 PM PST 23
Finished Dec 24 12:25:09 PM PST 23
Peak memory 199164 kb
Host smart-3e91fbed-84e3-479a-afcd-24b4e8d87acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576768129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.3576768129
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.3548755319
Short name T615
Test name
Test status
Simulation time 78285099 ps
CPU time 0.77 seconds
Started Dec 24 12:24:43 PM PST 23
Finished Dec 24 12:24:45 PM PST 23
Peak memory 198992 kb
Host smart-2718cd2d-5487-4496-9cb9-50552094dcaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548755319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.3548755319
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.1899925925
Short name T28
Test name
Test status
Simulation time 1889203521 ps
CPU time 6.64 seconds
Started Dec 24 12:27:28 PM PST 23
Finished Dec 24 12:27:37 PM PST 23
Peak memory 216464 kb
Host smart-93c9d666-1f3a-4dd2-a994-4df7bb4a417b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899925925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.1899925925
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.4062638007
Short name T501
Test name
Test status
Simulation time 244281165 ps
CPU time 1.13 seconds
Started Dec 24 12:25:47 PM PST 23
Finished Dec 24 12:25:50 PM PST 23
Peak memory 216336 kb
Host smart-54bdf758-f816-4f9d-a096-654c863994c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062638007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.4062638007
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.1670259081
Short name T464
Test name
Test status
Simulation time 131536396 ps
CPU time 0.77 seconds
Started Dec 24 12:27:14 PM PST 23
Finished Dec 24 12:27:17 PM PST 23
Peak memory 199100 kb
Host smart-51d21fdf-b443-4135-9a8f-bcac04a514ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670259081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.1670259081
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.834371913
Short name T543
Test name
Test status
Simulation time 1654374378 ps
CPU time 6.5 seconds
Started Dec 24 12:24:42 PM PST 23
Finished Dec 24 12:24:50 PM PST 23
Peak memory 199468 kb
Host smart-9bb242d1-bdb1-4035-8bf8-b93c0fa73567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834371913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.834371913
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.1818001438
Short name T552
Test name
Test status
Simulation time 182565963 ps
CPU time 1.19 seconds
Started Dec 24 12:24:45 PM PST 23
Finished Dec 24 12:24:48 PM PST 23
Peak memory 199156 kb
Host smart-06dcf0f7-485d-40f5-9e1f-0c1306c86764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818001438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.1818001438
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.1770467436
Short name T604
Test name
Test status
Simulation time 188790910 ps
CPU time 1.51 seconds
Started Dec 24 12:24:40 PM PST 23
Finished Dec 24 12:24:43 PM PST 23
Peak memory 199324 kb
Host smart-190af539-3f40-448a-abcc-d4263444c53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770467436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.1770467436
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.2835177100
Short name T454
Test name
Test status
Simulation time 8811510009 ps
CPU time 34.92 seconds
Started Dec 24 12:26:52 PM PST 23
Finished Dec 24 12:27:29 PM PST 23
Peak memory 198636 kb
Host smart-a7da1915-66de-4c13-b7f6-f2a6d9c9e78f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835177100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.2835177100
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.4051533465
Short name T367
Test name
Test status
Simulation time 139742422 ps
CPU time 1.75 seconds
Started Dec 24 12:26:53 PM PST 23
Finished Dec 24 12:26:57 PM PST 23
Peak memory 199280 kb
Host smart-73a0b655-d1a9-476d-8b0d-430bfb05c81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051533465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.4051533465
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.3639117839
Short name T513
Test name
Test status
Simulation time 91272395 ps
CPU time 0.87 seconds
Started Dec 24 12:24:35 PM PST 23
Finished Dec 24 12:24:37 PM PST 23
Peak memory 199184 kb
Host smart-464641b2-949d-4d5a-91e3-ed2cffd3dd69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639117839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.3639117839
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.2162294183
Short name T26
Test name
Test status
Simulation time 2169042848 ps
CPU time 8.06 seconds
Started Dec 24 12:27:51 PM PST 23
Finished Dec 24 12:28:07 PM PST 23
Peak memory 220684 kb
Host smart-82b59eff-5c1c-4c25-9d40-b32ce7426817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162294183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.2162294183
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.954015903
Short name T159
Test name
Test status
Simulation time 244232360 ps
CPU time 1.06 seconds
Started Dec 24 12:25:04 PM PST 23
Finished Dec 24 12:25:07 PM PST 23
Peak memory 216324 kb
Host smart-6933bc31-cc55-457d-b681-9b50b5824ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954015903 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.954015903
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.783145098
Short name T488
Test name
Test status
Simulation time 195564270 ps
CPU time 1 seconds
Started Dec 24 12:26:38 PM PST 23
Finished Dec 24 12:26:42 PM PST 23
Peak memory 198968 kb
Host smart-5edbf54b-bebb-487d-9cd0-a353183361df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783145098 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.783145098
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.1347096461
Short name T267
Test name
Test status
Simulation time 1473784081 ps
CPU time 5.49 seconds
Started Dec 24 12:24:44 PM PST 23
Finished Dec 24 12:24:50 PM PST 23
Peak memory 199776 kb
Host smart-2fee68d9-3f73-493c-b0d6-84bdb4560234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347096461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.1347096461
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.1647064534
Short name T266
Test name
Test status
Simulation time 107944339 ps
CPU time 0.98 seconds
Started Dec 24 12:28:08 PM PST 23
Finished Dec 24 12:28:22 PM PST 23
Peak memory 199232 kb
Host smart-3d0c00d7-6fc8-4190-8601-d1e950ddb9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647064534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.1647064534
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.1203162724
Short name T492
Test name
Test status
Simulation time 118943334 ps
CPU time 1.2 seconds
Started Dec 24 12:26:40 PM PST 23
Finished Dec 24 12:26:45 PM PST 23
Peak memory 199380 kb
Host smart-9985baf3-3e4a-41b6-a470-8d4930fc76d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203162724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.1203162724
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.3408573629
Short name T308
Test name
Test status
Simulation time 8480215020 ps
CPU time 32.5 seconds
Started Dec 24 12:25:32 PM PST 23
Finished Dec 24 12:26:06 PM PST 23
Peak memory 199428 kb
Host smart-1cbf5573-5b21-4cea-ba01-3c78cce09675
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408573629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.3408573629
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.1334785671
Short name T494
Test name
Test status
Simulation time 312232469 ps
CPU time 1.95 seconds
Started Dec 24 12:26:55 PM PST 23
Finished Dec 24 12:27:01 PM PST 23
Peak memory 199160 kb
Host smart-b3ae3e00-2340-418c-81bc-1bdfd770f58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334785671 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.1334785671
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.3971811860
Short name T592
Test name
Test status
Simulation time 279329315 ps
CPU time 1.48 seconds
Started Dec 24 12:26:51 PM PST 23
Finished Dec 24 12:26:54 PM PST 23
Peak memory 199272 kb
Host smart-87117391-2a4f-4fcc-ae9b-ea7c78b8d3a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971811860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.3971811860
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.2997866537
Short name T154
Test name
Test status
Simulation time 96485532 ps
CPU time 0.74 seconds
Started Dec 24 12:26:38 PM PST 23
Finished Dec 24 12:26:43 PM PST 23
Peak memory 198684 kb
Host smart-da468062-1a3b-4a95-946c-fa9a364d964b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997866537 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.2997866537
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.720274969
Short name T299
Test name
Test status
Simulation time 1227447879 ps
CPU time 5.07 seconds
Started Dec 24 12:26:38 PM PST 23
Finished Dec 24 12:26:47 PM PST 23
Peak memory 216664 kb
Host smart-29ecd067-50ea-496a-a6e3-7ed918d95624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720274969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.720274969
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.3997567316
Short name T280
Test name
Test status
Simulation time 244541439 ps
CPU time 1.02 seconds
Started Dec 24 12:26:27 PM PST 23
Finished Dec 24 12:26:30 PM PST 23
Peak memory 216368 kb
Host smart-bfd1db4a-9bd6-4705-ab31-9ca1cb663a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997567316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.3997567316
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.2305870718
Short name T342
Test name
Test status
Simulation time 209871027 ps
CPU time 0.88 seconds
Started Dec 24 12:26:44 PM PST 23
Finished Dec 24 12:26:48 PM PST 23
Peak memory 199108 kb
Host smart-a30da9d1-e719-4412-9b36-f7116228df20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305870718 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.2305870718
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.2069132779
Short name T481
Test name
Test status
Simulation time 1413159810 ps
CPU time 5.38 seconds
Started Dec 24 12:26:39 PM PST 23
Finished Dec 24 12:26:48 PM PST 23
Peak memory 199168 kb
Host smart-9d02e4ab-ab7b-4654-826c-c239e0bf9401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069132779 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.2069132779
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.2283075896
Short name T465
Test name
Test status
Simulation time 102027749 ps
CPU time 1 seconds
Started Dec 24 12:26:15 PM PST 23
Finished Dec 24 12:26:18 PM PST 23
Peak memory 199148 kb
Host smart-7e16d762-33e6-41c8-83b3-66e3f7508e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283075896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.2283075896
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.2242873996
Short name T526
Test name
Test status
Simulation time 125821372 ps
CPU time 1.17 seconds
Started Dec 24 12:24:50 PM PST 23
Finished Dec 24 12:24:53 PM PST 23
Peak memory 199228 kb
Host smart-f8a31761-9789-4fd0-a358-3b001f6eea36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242873996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.2242873996
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.3242683590
Short name T550
Test name
Test status
Simulation time 1321286687 ps
CPU time 5.55 seconds
Started Dec 24 12:26:38 PM PST 23
Finished Dec 24 12:26:47 PM PST 23
Peak memory 198292 kb
Host smart-0dd2f5fd-2624-4d86-9ede-07c73ca2e61b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242683590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.3242683590
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.2403909939
Short name T390
Test name
Test status
Simulation time 129784137 ps
CPU time 1.57 seconds
Started Dec 24 12:25:58 PM PST 23
Finished Dec 24 12:26:02 PM PST 23
Peak memory 199000 kb
Host smart-46762974-f6f8-49e3-b1cc-9a1e889ab4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403909939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.2403909939
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.4160944553
Short name T474
Test name
Test status
Simulation time 274818549 ps
CPU time 1.44 seconds
Started Dec 24 12:26:38 PM PST 23
Finished Dec 24 12:26:43 PM PST 23
Peak memory 198216 kb
Host smart-2cba8e52-7650-4d24-ad2b-aab15b546c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160944553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.4160944553
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.1426571706
Short name T341
Test name
Test status
Simulation time 75741380 ps
CPU time 0.88 seconds
Started Dec 24 12:25:57 PM PST 23
Finished Dec 24 12:26:00 PM PST 23
Peak memory 199072 kb
Host smart-2498b7c1-7adf-404e-b6b5-741b96d60139
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426571706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.1426571706
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.2159107080
Short name T441
Test name
Test status
Simulation time 2178886214 ps
CPU time 7.52 seconds
Started Dec 24 12:28:40 PM PST 23
Finished Dec 24 12:28:54 PM PST 23
Peak memory 216088 kb
Host smart-fe8feae6-2711-4852-a846-351b016a7477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159107080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.2159107080
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.500384851
Short name T587
Test name
Test status
Simulation time 244077646 ps
CPU time 1.13 seconds
Started Dec 24 12:26:02 PM PST 23
Finished Dec 24 12:26:09 PM PST 23
Peak memory 216416 kb
Host smart-8507b3c6-d553-42c7-8bee-ee2c95c431a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500384851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.500384851
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.2630624770
Short name T500
Test name
Test status
Simulation time 210608290 ps
CPU time 0.85 seconds
Started Dec 24 12:24:45 PM PST 23
Finished Dec 24 12:24:47 PM PST 23
Peak memory 199064 kb
Host smart-373c11f1-c621-4b52-8d86-ce7c3c724e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630624770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.2630624770
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.1819339221
Short name T590
Test name
Test status
Simulation time 1755882413 ps
CPU time 6.88 seconds
Started Dec 24 12:26:06 PM PST 23
Finished Dec 24 12:26:16 PM PST 23
Peak memory 199288 kb
Host smart-b1cefff9-7a51-499a-9dab-b5631028f129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819339221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.1819339221
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.1705151309
Short name T282
Test name
Test status
Simulation time 173623695 ps
CPU time 1.09 seconds
Started Dec 24 12:28:00 PM PST 23
Finished Dec 24 12:28:22 PM PST 23
Peak memory 199260 kb
Host smart-2df9f080-ae90-4891-a56a-79c06bb4dcb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705151309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.1705151309
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.4048026648
Short name T599
Test name
Test status
Simulation time 209732776 ps
CPU time 1.43 seconds
Started Dec 24 12:28:49 PM PST 23
Finished Dec 24 12:29:01 PM PST 23
Peak memory 199372 kb
Host smart-1bb175bb-0deb-47e4-bc66-403315aa299e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048026648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.4048026648
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.2367651773
Short name T53
Test name
Test status
Simulation time 2707714119 ps
CPU time 11.76 seconds
Started Dec 24 12:25:58 PM PST 23
Finished Dec 24 12:26:14 PM PST 23
Peak memory 199456 kb
Host smart-6d69cc4d-d370-4b78-a2e9-6d00779f1268
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367651773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.2367651773
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.1034544922
Short name T133
Test name
Test status
Simulation time 443066562 ps
CPU time 2.62 seconds
Started Dec 24 12:26:38 PM PST 23
Finished Dec 24 12:26:43 PM PST 23
Peak memory 199308 kb
Host smart-a6fb59b7-251f-4766-a7e6-9de9ff5ebeee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034544922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.1034544922
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.2114222224
Short name T248
Test name
Test status
Simulation time 143063828 ps
CPU time 1 seconds
Started Dec 24 12:26:39 PM PST 23
Finished Dec 24 12:26:44 PM PST 23
Peak memory 198996 kb
Host smart-2086f282-30b2-448a-9bcb-51141e8cdde4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114222224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.2114222224
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.1554028872
Short name T489
Test name
Test status
Simulation time 74457064 ps
CPU time 0.76 seconds
Started Dec 24 12:31:12 PM PST 23
Finished Dec 24 12:31:35 PM PST 23
Peak memory 198708 kb
Host smart-d0163cdb-ce2e-43a6-bc06-88e873f07cfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554028872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.1554028872
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.3839960988
Short name T350
Test name
Test status
Simulation time 1229783261 ps
CPU time 5.71 seconds
Started Dec 24 12:25:35 PM PST 23
Finished Dec 24 12:25:42 PM PST 23
Peak memory 221336 kb
Host smart-33782026-8961-491f-ab11-969c44544252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839960988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.3839960988
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.2779332450
Short name T555
Test name
Test status
Simulation time 245034207 ps
CPU time 1 seconds
Started Dec 24 12:25:05 PM PST 23
Finished Dec 24 12:25:07 PM PST 23
Peak memory 216484 kb
Host smart-ec83a44b-5611-4a9c-8881-d5158be449ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779332450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.2779332450
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.402703659
Short name T547
Test name
Test status
Simulation time 84773200 ps
CPU time 0.84 seconds
Started Dec 24 12:26:38 PM PST 23
Finished Dec 24 12:26:42 PM PST 23
Peak memory 197640 kb
Host smart-4ec93b12-eb83-4b85-b42f-93559229c95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402703659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.402703659
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.3432314452
Short name T81
Test name
Test status
Simulation time 1002964035 ps
CPU time 4.46 seconds
Started Dec 24 12:26:38 PM PST 23
Finished Dec 24 12:26:46 PM PST 23
Peak memory 198180 kb
Host smart-99ef5d9d-fc89-47ca-81de-f896340d194c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432314452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.3432314452
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.955302989
Short name T79
Test name
Test status
Simulation time 106537065 ps
CPU time 0.98 seconds
Started Dec 24 12:26:23 PM PST 23
Finished Dec 24 12:26:26 PM PST 23
Peak memory 199296 kb
Host smart-eda89e80-0397-4cdc-96a4-92ca9a330fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955302989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.955302989
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.1463866731
Short name T22
Test name
Test status
Simulation time 111905167 ps
CPU time 1.19 seconds
Started Dec 24 12:25:59 PM PST 23
Finished Dec 24 12:26:05 PM PST 23
Peak memory 199388 kb
Host smart-5e74620b-8fdb-4433-863f-1a7da47fa549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463866731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.1463866731
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.2609515072
Short name T249
Test name
Test status
Simulation time 6329703308 ps
CPU time 22.04 seconds
Started Dec 24 12:26:09 PM PST 23
Finished Dec 24 12:26:33 PM PST 23
Peak memory 199484 kb
Host smart-f2a539e1-f8e2-4f62-b17d-04054efd2b63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609515072 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.2609515072
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.980123057
Short name T351
Test name
Test status
Simulation time 493124057 ps
CPU time 2.44 seconds
Started Dec 24 12:25:34 PM PST 23
Finished Dec 24 12:25:37 PM PST 23
Peak memory 199156 kb
Host smart-6ca127d4-ff65-47d4-9a78-2cf67630f0d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980123057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.980123057
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.1061586475
Short name T499
Test name
Test status
Simulation time 68911817 ps
CPU time 0.75 seconds
Started Dec 24 12:25:57 PM PST 23
Finished Dec 24 12:26:00 PM PST 23
Peak memory 199172 kb
Host smart-2a2130c9-527c-4e9f-b699-d64c557a5d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061586475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.1061586475
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.3776582317
Short name T284
Test name
Test status
Simulation time 68527906 ps
CPU time 0.76 seconds
Started Dec 24 12:26:14 PM PST 23
Finished Dec 24 12:26:17 PM PST 23
Peak memory 199088 kb
Host smart-fc718229-86fc-402b-b98c-5906ee4aea6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776582317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.3776582317
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.1779299912
Short name T512
Test name
Test status
Simulation time 1222911215 ps
CPU time 5.94 seconds
Started Dec 24 12:25:21 PM PST 23
Finished Dec 24 12:25:28 PM PST 23
Peak memory 216432 kb
Host smart-5d96ba08-7c7f-4e58-a987-0f77b1c34bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779299912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.1779299912
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.3343019558
Short name T542
Test name
Test status
Simulation time 245901278 ps
CPU time 1.01 seconds
Started Dec 24 12:26:35 PM PST 23
Finished Dec 24 12:26:38 PM PST 23
Peak memory 216268 kb
Host smart-ecd4ea3b-aa4b-4f7f-a98d-c59b5c44b890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343019558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.3343019558
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.3499290911
Short name T545
Test name
Test status
Simulation time 143778640 ps
CPU time 0.83 seconds
Started Dec 24 12:26:17 PM PST 23
Finished Dec 24 12:26:21 PM PST 23
Peak memory 199080 kb
Host smart-4b447732-3408-42db-962d-4dff4830bb55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499290911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.3499290911
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.3905195043
Short name T343
Test name
Test status
Simulation time 1287244135 ps
CPU time 5.11 seconds
Started Dec 24 12:26:15 PM PST 23
Finished Dec 24 12:26:22 PM PST 23
Peak memory 199368 kb
Host smart-a5dfd286-8667-4a6a-aad1-206a2c503b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905195043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.3905195043
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.1661356562
Short name T325
Test name
Test status
Simulation time 103489907 ps
CPU time 0.93 seconds
Started Dec 24 12:24:50 PM PST 23
Finished Dec 24 12:24:53 PM PST 23
Peak memory 199116 kb
Host smart-b3829072-af4a-447f-8e4e-03f422fc35ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661356562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.1661356562
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.2913548762
Short name T530
Test name
Test status
Simulation time 7076999281 ps
CPU time 24.75 seconds
Started Dec 24 12:25:34 PM PST 23
Finished Dec 24 12:26:00 PM PST 23
Peak memory 198608 kb
Host smart-32c2995e-e403-4d7a-ba2c-8593eda7d70b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913548762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.2913548762
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.1635268547
Short name T458
Test name
Test status
Simulation time 244279343 ps
CPU time 1.89 seconds
Started Dec 24 12:26:23 PM PST 23
Finished Dec 24 12:26:27 PM PST 23
Peak memory 199232 kb
Host smart-398acc09-6d08-44f4-9fc1-f8b513e562c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635268547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.1635268547
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.4136272363
Short name T83
Test name
Test status
Simulation time 188773983 ps
CPU time 1.17 seconds
Started Dec 24 12:26:31 PM PST 23
Finished Dec 24 12:26:34 PM PST 23
Peak memory 199272 kb
Host smart-859856c6-937e-45b5-8463-2af57cb31735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136272363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.4136272363
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.726335713
Short name T432
Test name
Test status
Simulation time 75066701 ps
CPU time 0.86 seconds
Started Dec 24 12:25:35 PM PST 23
Finished Dec 24 12:25:37 PM PST 23
Peak memory 198952 kb
Host smart-faac92c2-5148-4779-ba39-b96fd28afe7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726335713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.726335713
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.1050246392
Short name T34
Test name
Test status
Simulation time 2365008719 ps
CPU time 8.03 seconds
Started Dec 24 12:30:26 PM PST 23
Finished Dec 24 12:30:59 PM PST 23
Peak memory 216832 kb
Host smart-356d6e88-4ea3-4aef-860f-4ce515d8fd14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050246392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.1050246392
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.400706049
Short name T139
Test name
Test status
Simulation time 244996350 ps
CPU time 1.03 seconds
Started Dec 24 12:25:37 PM PST 23
Finished Dec 24 12:25:40 PM PST 23
Peak memory 216348 kb
Host smart-a33f39c3-9b0a-44e9-af03-3e641ee037bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400706049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.400706049
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.3367103726
Short name T18
Test name
Test status
Simulation time 141318841 ps
CPU time 0.75 seconds
Started Dec 24 12:30:52 PM PST 23
Finished Dec 24 12:31:16 PM PST 23
Peak memory 199104 kb
Host smart-ec655689-767d-46f5-93d8-e7f1ce411c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367103726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.3367103726
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.1980873073
Short name T153
Test name
Test status
Simulation time 980338849 ps
CPU time 4.28 seconds
Started Dec 24 12:32:45 PM PST 23
Finished Dec 24 12:33:17 PM PST 23
Peak memory 198004 kb
Host smart-8812b5a7-de2d-471b-b70a-318f2ce003f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980873073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.1980873073
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.82552651
Short name T77
Test name
Test status
Simulation time 16511209952 ps
CPU time 29.24 seconds
Started Dec 24 12:26:12 PM PST 23
Finished Dec 24 12:26:43 PM PST 23
Peak memory 217028 kb
Host smart-b7ca96e4-b887-4271-9c26-2aa001e1991a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82552651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.82552651
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.3602222255
Short name T276
Test name
Test status
Simulation time 108775157 ps
CPU time 1.03 seconds
Started Dec 24 12:25:47 PM PST 23
Finished Dec 24 12:25:51 PM PST 23
Peak memory 197644 kb
Host smart-0ca54284-248a-421a-a29c-58abe61d5638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602222255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.3602222255
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.1814235093
Short name T414
Test name
Test status
Simulation time 245207780 ps
CPU time 1.44 seconds
Started Dec 24 12:33:13 PM PST 23
Finished Dec 24 12:33:55 PM PST 23
Peak memory 199196 kb
Host smart-62caafc1-902f-4aad-b080-a51499d3ed86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814235093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.1814235093
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.589689550
Short name T151
Test name
Test status
Simulation time 4727868931 ps
CPU time 21.05 seconds
Started Dec 24 12:26:11 PM PST 23
Finished Dec 24 12:26:34 PM PST 23
Peak memory 199368 kb
Host smart-9a848244-328f-4c3a-9635-d131dc520bca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589689550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.589689550
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.4004570002
Short name T551
Test name
Test status
Simulation time 319583995 ps
CPU time 1.99 seconds
Started Dec 24 12:28:51 PM PST 23
Finished Dec 24 12:29:04 PM PST 23
Peak memory 199260 kb
Host smart-eda0872c-b2ab-43d9-8c29-a6f77880009d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004570002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.4004570002
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.2060905961
Short name T508
Test name
Test status
Simulation time 67284905 ps
CPU time 0.72 seconds
Started Dec 24 12:26:38 PM PST 23
Finished Dec 24 12:26:42 PM PST 23
Peak memory 198180 kb
Host smart-6f4efb0c-700f-45b3-a96a-a2c0257077a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060905961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.2060905961
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.4047825749
Short name T581
Test name
Test status
Simulation time 59411860 ps
CPU time 0.74 seconds
Started Dec 24 12:26:42 PM PST 23
Finished Dec 24 12:26:46 PM PST 23
Peak memory 199396 kb
Host smart-dca405ab-fcd8-4ea0-ae12-ffd6d54b9191
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047825749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.4047825749
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.422825227
Short name T344
Test name
Test status
Simulation time 1221047107 ps
CPU time 5.77 seconds
Started Dec 24 12:26:58 PM PST 23
Finished Dec 24 12:27:08 PM PST 23
Peak memory 221196 kb
Host smart-f8f07c5a-e1ea-482f-82c2-a22d5ce80575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422825227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.422825227
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.978336844
Short name T484
Test name
Test status
Simulation time 245118065 ps
CPU time 1.05 seconds
Started Dec 24 12:26:54 PM PST 23
Finished Dec 24 12:26:59 PM PST 23
Peak memory 216420 kb
Host smart-f4792c29-e61a-4e7b-88ca-6b930c534fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978336844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.978336844
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.3746076820
Short name T19
Test name
Test status
Simulation time 145905801 ps
CPU time 0.83 seconds
Started Dec 24 12:27:23 PM PST 23
Finished Dec 24 12:27:28 PM PST 23
Peak memory 199044 kb
Host smart-22bac7b3-3918-4d1f-b92d-e5635b826eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746076820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.3746076820
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.2157648193
Short name T329
Test name
Test status
Simulation time 1693258351 ps
CPU time 6.46 seconds
Started Dec 24 12:26:21 PM PST 23
Finished Dec 24 12:26:30 PM PST 23
Peak memory 199420 kb
Host smart-d5cd49c1-fd17-40fc-a2e2-1bd7c986c3c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157648193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.2157648193
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.2187480859
Short name T371
Test name
Test status
Simulation time 99034240 ps
CPU time 0.96 seconds
Started Dec 24 12:25:49 PM PST 23
Finished Dec 24 12:25:52 PM PST 23
Peak memory 198624 kb
Host smart-0b1509b3-a530-49a2-99f7-e4e96d781f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187480859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.2187480859
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.2649850592
Short name T56
Test name
Test status
Simulation time 193699885 ps
CPU time 1.3 seconds
Started Dec 24 12:26:57 PM PST 23
Finished Dec 24 12:27:01 PM PST 23
Peak memory 199272 kb
Host smart-6b2f00f2-403c-4d8c-95c8-e91cacf98a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649850592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.2649850592
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.3026643436
Short name T152
Test name
Test status
Simulation time 1133212832 ps
CPU time 5.19 seconds
Started Dec 24 12:26:39 PM PST 23
Finished Dec 24 12:26:48 PM PST 23
Peak memory 199408 kb
Host smart-f91a5590-49da-4630-bf08-dbeb3afc8caa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026643436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.3026643436
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.1760435430
Short name T566
Test name
Test status
Simulation time 376197330 ps
CPU time 2.46 seconds
Started Dec 24 12:26:32 PM PST 23
Finished Dec 24 12:26:36 PM PST 23
Peak memory 199192 kb
Host smart-d6f37db5-0700-4422-9511-14f34e775298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760435430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.1760435430
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.3734459147
Short name T89
Test name
Test status
Simulation time 144619910 ps
CPU time 1.13 seconds
Started Dec 24 12:25:14 PM PST 23
Finished Dec 24 12:25:16 PM PST 23
Peak memory 199084 kb
Host smart-e28efdc4-0b21-4149-82a3-fc997a2d6f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734459147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.3734459147
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.88657564
Short name T480
Test name
Test status
Simulation time 65290952 ps
CPU time 0.74 seconds
Started Dec 24 12:26:56 PM PST 23
Finished Dec 24 12:27:00 PM PST 23
Peak memory 198924 kb
Host smart-cc122adf-9dee-495b-a8a5-e6068c8d48c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88657564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.88657564
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.610663196
Short name T450
Test name
Test status
Simulation time 1897804064 ps
CPU time 7.78 seconds
Started Dec 24 12:27:04 PM PST 23
Finished Dec 24 12:27:17 PM PST 23
Peak memory 221256 kb
Host smart-74654968-085c-4f3c-8049-92eb09e7372a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610663196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.610663196
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.496967565
Short name T527
Test name
Test status
Simulation time 243496742 ps
CPU time 1.06 seconds
Started Dec 24 12:25:09 PM PST 23
Finished Dec 24 12:25:11 PM PST 23
Peak memory 216300 kb
Host smart-38d6f949-d7c1-443b-8ad7-f3e6d999dd78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496967565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.496967565
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.1618181028
Short name T321
Test name
Test status
Simulation time 225375133 ps
CPU time 0.93 seconds
Started Dec 24 12:26:22 PM PST 23
Finished Dec 24 12:26:25 PM PST 23
Peak memory 198968 kb
Host smart-bf3b28c8-2047-4d9a-ba2f-4aabbacca0be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618181028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.1618181028
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.3047438612
Short name T113
Test name
Test status
Simulation time 796154799 ps
CPU time 3.75 seconds
Started Dec 24 12:26:58 PM PST 23
Finished Dec 24 12:27:05 PM PST 23
Peak memory 199436 kb
Host smart-2b85c9ba-cdc9-48ef-ab0e-761125f19802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047438612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.3047438612
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.3558313976
Short name T324
Test name
Test status
Simulation time 101652230 ps
CPU time 0.96 seconds
Started Dec 24 12:28:46 PM PST 23
Finished Dec 24 12:28:55 PM PST 23
Peak memory 198960 kb
Host smart-31c6cba0-0c1c-4c9b-be8b-0c514cfc6a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558313976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.3558313976
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.1083262339
Short name T46
Test name
Test status
Simulation time 120193335 ps
CPU time 1.21 seconds
Started Dec 24 12:26:54 PM PST 23
Finished Dec 24 12:26:58 PM PST 23
Peak memory 199416 kb
Host smart-94bdffa1-edad-4f43-8573-902f674fa036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083262339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.1083262339
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.2848869564
Short name T250
Test name
Test status
Simulation time 4035642214 ps
CPU time 18.58 seconds
Started Dec 24 12:26:58 PM PST 23
Finished Dec 24 12:27:20 PM PST 23
Peak memory 199476 kb
Host smart-6aa50161-02cf-44ae-85f0-360ecd12d8ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848869564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.2848869564
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.2332469009
Short name T65
Test name
Test status
Simulation time 398744792 ps
CPU time 2.69 seconds
Started Dec 24 12:26:57 PM PST 23
Finished Dec 24 12:27:04 PM PST 23
Peak memory 199204 kb
Host smart-2a2f3dfa-5e7f-4daf-bf64-ea104c90febd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332469009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.2332469009
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.3913010239
Short name T357
Test name
Test status
Simulation time 102193274 ps
CPU time 0.96 seconds
Started Dec 24 12:27:02 PM PST 23
Finished Dec 24 12:27:08 PM PST 23
Peak memory 199200 kb
Host smart-cd51d4a5-cfd2-4138-ad27-c88ea5789406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913010239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.3913010239
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.3336550196
Short name T498
Test name
Test status
Simulation time 70622296 ps
CPU time 0.71 seconds
Started Dec 24 12:29:14 PM PST 23
Finished Dec 24 12:29:19 PM PST 23
Peak memory 198600 kb
Host smart-c14dde99-a315-4af5-a15f-281586d2649e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336550196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.3336550196
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.3218423484
Short name T32
Test name
Test status
Simulation time 1223883050 ps
CPU time 5.87 seconds
Started Dec 24 12:26:09 PM PST 23
Finished Dec 24 12:26:17 PM PST 23
Peak memory 217004 kb
Host smart-d5859979-8834-4dd4-a1a1-1a266c86a3e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218423484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.3218423484
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.84101038
Short name T307
Test name
Test status
Simulation time 244696354 ps
CPU time 1.09 seconds
Started Dec 24 12:28:18 PM PST 23
Finished Dec 24 12:28:35 PM PST 23
Peak memory 215964 kb
Host smart-740462fd-09c8-4f28-84b0-ef9506d4d348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84101038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.84101038
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.1198632325
Short name T408
Test name
Test status
Simulation time 242662710 ps
CPU time 0.98 seconds
Started Dec 24 12:27:20 PM PST 23
Finished Dec 24 12:27:25 PM PST 23
Peak memory 198968 kb
Host smart-c2169230-a519-4038-984c-506b27e3fb36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198632325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.1198632325
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.3187426424
Short name T601
Test name
Test status
Simulation time 1047912288 ps
CPU time 5.33 seconds
Started Dec 24 12:25:09 PM PST 23
Finished Dec 24 12:25:15 PM PST 23
Peak memory 199264 kb
Host smart-d716a9ca-db3d-4c52-a718-321ebe1740f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187426424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.3187426424
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.3793663418
Short name T461
Test name
Test status
Simulation time 98946615 ps
CPU time 0.91 seconds
Started Dec 24 12:28:01 PM PST 23
Finished Dec 24 12:28:15 PM PST 23
Peak memory 199132 kb
Host smart-1abfd19d-182d-4387-9812-123bea78d59d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793663418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.3793663418
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.1573517721
Short name T561
Test name
Test status
Simulation time 125158539 ps
CPU time 1.15 seconds
Started Dec 24 12:26:56 PM PST 23
Finished Dec 24 12:27:01 PM PST 23
Peak memory 199260 kb
Host smart-cf423254-db0a-4345-8003-ea258a62358f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573517721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.1573517721
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.220167861
Short name T475
Test name
Test status
Simulation time 3374222160 ps
CPU time 14.45 seconds
Started Dec 24 12:27:51 PM PST 23
Finished Dec 24 12:28:14 PM PST 23
Peak memory 199496 kb
Host smart-c780e544-c4ad-4e6b-aaf7-fd7ba7cf5341
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220167861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.220167861
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.556497199
Short name T382
Test name
Test status
Simulation time 468650262 ps
CPU time 2.62 seconds
Started Dec 24 12:25:25 PM PST 23
Finished Dec 24 12:25:29 PM PST 23
Peak memory 199540 kb
Host smart-6f531377-b843-479a-aa82-a8197cdd4587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556497199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.556497199
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.2274228553
Short name T505
Test name
Test status
Simulation time 74534513 ps
CPU time 0.83 seconds
Started Dec 24 12:25:10 PM PST 23
Finished Dec 24 12:25:12 PM PST 23
Peak memory 199204 kb
Host smart-37bc602b-2869-4303-b2b3-290de34cd28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274228553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.2274228553
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.3487664587
Short name T585
Test name
Test status
Simulation time 83069502 ps
CPU time 0.77 seconds
Started Dec 24 12:25:55 PM PST 23
Finished Dec 24 12:25:57 PM PST 23
Peak memory 198924 kb
Host smart-79de3da1-c58e-48b0-a6d1-28031b2eb9ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487664587 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.3487664587
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.3208205894
Short name T25
Test name
Test status
Simulation time 2353134729 ps
CPU time 9.31 seconds
Started Dec 24 12:26:46 PM PST 23
Finished Dec 24 12:26:57 PM PST 23
Peak memory 216432 kb
Host smart-912537c7-779a-4014-b2fc-08a353dceb46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208205894 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.3208205894
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.1127426609
Short name T165
Test name
Test status
Simulation time 243821382 ps
CPU time 1.08 seconds
Started Dec 24 12:25:25 PM PST 23
Finished Dec 24 12:25:27 PM PST 23
Peak memory 216492 kb
Host smart-5882bbab-da4c-40f4-b4ac-f5195c781fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127426609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.1127426609
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.1876736439
Short name T338
Test name
Test status
Simulation time 151487041 ps
CPU time 0.83 seconds
Started Dec 24 12:26:56 PM PST 23
Finished Dec 24 12:27:00 PM PST 23
Peak memory 198884 kb
Host smart-db635418-854e-4a8e-ab0a-10e9107169d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876736439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.1876736439
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.2763284264
Short name T406
Test name
Test status
Simulation time 1362337775 ps
CPU time 6.4 seconds
Started Dec 24 12:27:04 PM PST 23
Finished Dec 24 12:27:15 PM PST 23
Peak memory 199404 kb
Host smart-54fee271-7f39-4de6-bd44-096506a876cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763284264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.2763284264
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.3008797258
Short name T273
Test name
Test status
Simulation time 141077527 ps
CPU time 1.17 seconds
Started Dec 24 12:26:39 PM PST 23
Finished Dec 24 12:26:44 PM PST 23
Peak memory 199248 kb
Host smart-3810ea45-1e76-4bcc-8539-7d6a315a908a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008797258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.3008797258
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.3069859659
Short name T155
Test name
Test status
Simulation time 116488850 ps
CPU time 1.12 seconds
Started Dec 24 12:27:22 PM PST 23
Finished Dec 24 12:27:28 PM PST 23
Peak memory 199396 kb
Host smart-805257f9-e83e-4f68-9705-31488de95108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069859659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.3069859659
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.1811944803
Short name T380
Test name
Test status
Simulation time 2903802907 ps
CPU time 12.17 seconds
Started Dec 24 12:27:08 PM PST 23
Finished Dec 24 12:27:25 PM PST 23
Peak memory 199480 kb
Host smart-9cd9d7ff-5b3a-4aa4-ae84-214ba0bc8689
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811944803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.1811944803
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.1794619448
Short name T78
Test name
Test status
Simulation time 139193796 ps
CPU time 1.61 seconds
Started Dec 24 12:27:06 PM PST 23
Finished Dec 24 12:27:13 PM PST 23
Peak memory 199212 kb
Host smart-bd2bf1a1-daa9-4dab-834b-ea60dad5ce07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794619448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.1794619448
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.4065917145
Short name T322
Test name
Test status
Simulation time 146041008 ps
CPU time 1.17 seconds
Started Dec 24 12:27:16 PM PST 23
Finished Dec 24 12:27:21 PM PST 23
Peak memory 199272 kb
Host smart-4657acb7-c5ca-4526-8d79-18afd60c7bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065917145 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.4065917145
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.3980114967
Short name T496
Test name
Test status
Simulation time 67702120 ps
CPU time 0.77 seconds
Started Dec 24 12:26:57 PM PST 23
Finished Dec 24 12:27:00 PM PST 23
Peak memory 199060 kb
Host smart-8f8d71ba-ea88-44d5-8850-678008cc9595
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980114967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.3980114967
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.1512746533
Short name T27
Test name
Test status
Simulation time 1895218054 ps
CPU time 6.79 seconds
Started Dec 24 12:27:57 PM PST 23
Finished Dec 24 12:28:17 PM PST 23
Peak memory 215692 kb
Host smart-37193369-2a94-4eb3-8f64-69f470342328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512746533 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.1512746533
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.4044366603
Short name T456
Test name
Test status
Simulation time 243443364 ps
CPU time 1.17 seconds
Started Dec 24 12:26:22 PM PST 23
Finished Dec 24 12:26:26 PM PST 23
Peak memory 216668 kb
Host smart-c13e8dcc-3159-41ce-a4fa-114968cbe94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044366603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.4044366603
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.1103956911
Short name T16
Test name
Test status
Simulation time 181541739 ps
CPU time 0.81 seconds
Started Dec 24 12:28:03 PM PST 23
Finished Dec 24 12:28:16 PM PST 23
Peak memory 199140 kb
Host smart-e09f8d81-83ce-4388-be45-7d67dc9f702f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103956911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.1103956911
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.2289914573
Short name T331
Test name
Test status
Simulation time 942664828 ps
CPU time 4.8 seconds
Started Dec 24 12:28:15 PM PST 23
Finished Dec 24 12:28:32 PM PST 23
Peak memory 199296 kb
Host smart-cc88855c-7ef7-46f6-b687-68a847e73fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289914573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.2289914573
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.1284902876
Short name T520
Test name
Test status
Simulation time 157536452 ps
CPU time 1.03 seconds
Started Dec 24 12:27:57 PM PST 23
Finished Dec 24 12:28:11 PM PST 23
Peak memory 199200 kb
Host smart-b8f939a5-ebc3-49d8-bf6d-c9f9ab172177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284902876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.1284902876
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.2014794889
Short name T373
Test name
Test status
Simulation time 124650221 ps
CPU time 1.14 seconds
Started Dec 24 12:25:57 PM PST 23
Finished Dec 24 12:26:00 PM PST 23
Peak memory 199412 kb
Host smart-ea686df0-3b46-4aba-b02b-ea09df260a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014794889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.2014794889
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.2419047266
Short name T337
Test name
Test status
Simulation time 432368919 ps
CPU time 2.44 seconds
Started Dec 24 12:25:28 PM PST 23
Finished Dec 24 12:25:31 PM PST 23
Peak memory 199356 kb
Host smart-101f3a48-1929-490f-b1aa-f41b051b5418
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419047266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.2419047266
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.2840716419
Short name T560
Test name
Test status
Simulation time 118957070 ps
CPU time 1.55 seconds
Started Dec 24 12:25:28 PM PST 23
Finished Dec 24 12:25:30 PM PST 23
Peak memory 199260 kb
Host smart-5649a2cc-3cbb-4494-8cd9-128578e8c760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840716419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.2840716419
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.382927400
Short name T310
Test name
Test status
Simulation time 250278612 ps
CPU time 1.37 seconds
Started Dec 24 12:27:57 PM PST 23
Finished Dec 24 12:28:11 PM PST 23
Peak memory 199440 kb
Host smart-6d98e00b-549d-4b15-a724-6fb605c92177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382927400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.382927400
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.278408248
Short name T401
Test name
Test status
Simulation time 81447706 ps
CPU time 0.77 seconds
Started Dec 24 12:28:48 PM PST 23
Finished Dec 24 12:28:58 PM PST 23
Peak memory 199112 kb
Host smart-9b154e1b-82b0-4c2c-ae4a-90ff283b64a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278408248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.278408248
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.2731092687
Short name T312
Test name
Test status
Simulation time 1222410109 ps
CPU time 5.33 seconds
Started Dec 24 12:27:57 PM PST 23
Finished Dec 24 12:28:16 PM PST 23
Peak memory 220512 kb
Host smart-13201197-a41c-4894-89b8-6c8faffe5cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731092687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.2731092687
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.4094945389
Short name T557
Test name
Test status
Simulation time 244780333 ps
CPU time 1.12 seconds
Started Dec 24 12:28:03 PM PST 23
Finished Dec 24 12:28:17 PM PST 23
Peak memory 216232 kb
Host smart-85144ef1-a40b-4074-b915-67480ddefe07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094945389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.4094945389
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.1452883356
Short name T486
Test name
Test status
Simulation time 172024168 ps
CPU time 0.83 seconds
Started Dec 24 12:26:51 PM PST 23
Finished Dec 24 12:26:54 PM PST 23
Peak memory 198936 kb
Host smart-dbeda745-fef2-4eae-92e4-2293d27afbd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452883356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.1452883356
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.1513236183
Short name T59
Test name
Test status
Simulation time 1686659759 ps
CPU time 7.46 seconds
Started Dec 24 12:26:49 PM PST 23
Finished Dec 24 12:26:59 PM PST 23
Peak memory 199304 kb
Host smart-5cd5cf5b-35e9-43cb-882e-f672a2114493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513236183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.1513236183
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.984951902
Short name T374
Test name
Test status
Simulation time 97855012 ps
CPU time 0.96 seconds
Started Dec 24 12:25:41 PM PST 23
Finished Dec 24 12:25:44 PM PST 23
Peak memory 199252 kb
Host smart-767e2bf5-42c4-4806-96ea-566344b9e71c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984951902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.984951902
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.2578943303
Short name T470
Test name
Test status
Simulation time 122774613 ps
CPU time 1.15 seconds
Started Dec 24 12:28:05 PM PST 23
Finished Dec 24 12:28:18 PM PST 23
Peak memory 199408 kb
Host smart-53fc5303-f388-4406-814e-27f45db77bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578943303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.2578943303
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.1753528415
Short name T452
Test name
Test status
Simulation time 5963033841 ps
CPU time 25.26 seconds
Started Dec 24 12:27:17 PM PST 23
Finished Dec 24 12:27:46 PM PST 23
Peak memory 199372 kb
Host smart-0c8a8205-8678-49ff-8001-111b5e079c97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753528415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.1753528415
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.1355261604
Short name T619
Test name
Test status
Simulation time 117443828 ps
CPU time 1.36 seconds
Started Dec 24 12:25:58 PM PST 23
Finished Dec 24 12:26:03 PM PST 23
Peak memory 199088 kb
Host smart-f77fe9a8-1c7c-4d94-93d9-800ead77ca7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355261604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.1355261604
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.1653606550
Short name T514
Test name
Test status
Simulation time 153497088 ps
CPU time 1.26 seconds
Started Dec 24 12:25:57 PM PST 23
Finished Dec 24 12:26:01 PM PST 23
Peak memory 199268 kb
Host smart-e2f621cf-b136-4564-98b5-27845997c54a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653606550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.1653606550
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.3397312321
Short name T254
Test name
Test status
Simulation time 90399729 ps
CPU time 0.82 seconds
Started Dec 24 12:27:17 PM PST 23
Finished Dec 24 12:27:22 PM PST 23
Peak memory 198952 kb
Host smart-e568c131-a469-4945-821d-573b7eee3d29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397312321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.3397312321
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.2477566336
Short name T44
Test name
Test status
Simulation time 2180088746 ps
CPU time 8.79 seconds
Started Dec 24 12:29:51 PM PST 23
Finished Dec 24 12:30:25 PM PST 23
Peak memory 217124 kb
Host smart-8b71a895-1b0e-4267-b203-787b72d59f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477566336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.2477566336
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.1293056423
Short name T256
Test name
Test status
Simulation time 244693189 ps
CPU time 1.02 seconds
Started Dec 24 12:28:48 PM PST 23
Finished Dec 24 12:29:00 PM PST 23
Peak memory 216504 kb
Host smart-312810e0-2863-4547-89ba-5e8ef5e5eb2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293056423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.1293056423
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.2584641515
Short name T264
Test name
Test status
Simulation time 170534379 ps
CPU time 0.8 seconds
Started Dec 24 12:28:48 PM PST 23
Finished Dec 24 12:28:58 PM PST 23
Peak memory 199064 kb
Host smart-a9e86ec5-7dbc-45a3-bec3-e467d074dfa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584641515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.2584641515
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.1343471798
Short name T164
Test name
Test status
Simulation time 943086707 ps
CPU time 4.42 seconds
Started Dec 24 12:27:17 PM PST 23
Finished Dec 24 12:27:26 PM PST 23
Peak memory 199280 kb
Host smart-3e3c0ecc-b053-4748-b2e0-f8325091695a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343471798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.1343471798
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.1427961040
Short name T143
Test name
Test status
Simulation time 97985462 ps
CPU time 1.02 seconds
Started Dec 24 12:27:09 PM PST 23
Finished Dec 24 12:27:14 PM PST 23
Peak memory 199188 kb
Host smart-e2ae6617-c0b1-4da5-81c0-f7b1708cdb7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427961040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.1427961040
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.2362474203
Short name T94
Test name
Test status
Simulation time 247689875 ps
CPU time 1.54 seconds
Started Dec 24 12:26:08 PM PST 23
Finished Dec 24 12:26:12 PM PST 23
Peak memory 199352 kb
Host smart-0fed963c-8c25-4bf8-b3c1-c7f33b5526d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362474203 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.2362474203
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.742367910
Short name T246
Test name
Test status
Simulation time 2555967632 ps
CPU time 11.35 seconds
Started Dec 24 12:27:09 PM PST 23
Finished Dec 24 12:27:24 PM PST 23
Peak memory 199668 kb
Host smart-1c74ea67-f103-4a9c-b99b-b186634c84c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742367910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.742367910
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.2509102753
Short name T571
Test name
Test status
Simulation time 339167896 ps
CPU time 2.01 seconds
Started Dec 24 12:28:47 PM PST 23
Finished Dec 24 12:28:58 PM PST 23
Peak memory 199220 kb
Host smart-ef3e1bf0-dc19-4af8-9323-ca903df2eb34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509102753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.2509102753
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.1864278732
Short name T12
Test name
Test status
Simulation time 185914381 ps
CPU time 1.28 seconds
Started Dec 24 12:30:13 PM PST 23
Finished Dec 24 12:30:38 PM PST 23
Peak memory 199400 kb
Host smart-311ffd7c-0f1b-41bd-93f5-bde0f504e168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864278732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.1864278732
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.1965765842
Short name T541
Test name
Test status
Simulation time 70663358 ps
CPU time 0.71 seconds
Started Dec 24 12:28:48 PM PST 23
Finished Dec 24 12:28:58 PM PST 23
Peak memory 199088 kb
Host smart-570bc9cb-1691-4649-97ac-13103ba6f3a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965765842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.1965765842
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.2556594411
Short name T495
Test name
Test status
Simulation time 1216370012 ps
CPU time 5.66 seconds
Started Dec 24 12:27:18 PM PST 23
Finished Dec 24 12:27:27 PM PST 23
Peak memory 216976 kb
Host smart-3da71fd5-c83d-4b26-b11f-30d2fc150a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556594411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.2556594411
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.3372460537
Short name T361
Test name
Test status
Simulation time 244036455 ps
CPU time 1.02 seconds
Started Dec 24 12:27:52 PM PST 23
Finished Dec 24 12:28:00 PM PST 23
Peak memory 216464 kb
Host smart-0469e238-f8a7-436d-9c5e-2aeeb5fc43bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372460537 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.3372460537
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.1029562038
Short name T20
Test name
Test status
Simulation time 145363477 ps
CPU time 0.87 seconds
Started Dec 24 12:27:17 PM PST 23
Finished Dec 24 12:27:22 PM PST 23
Peak memory 198928 kb
Host smart-597617a5-3215-44f1-9456-48019c3dabb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029562038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.1029562038
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.3988780287
Short name T131
Test name
Test status
Simulation time 1699210913 ps
CPU time 5.67 seconds
Started Dec 24 12:30:00 PM PST 23
Finished Dec 24 12:30:32 PM PST 23
Peak memory 199468 kb
Host smart-63fc9038-eef3-446c-bcce-bbcf11f87c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988780287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.3988780287
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.2603235089
Short name T424
Test name
Test status
Simulation time 105540475 ps
CPU time 0.92 seconds
Started Dec 24 12:28:50 PM PST 23
Finished Dec 24 12:29:01 PM PST 23
Peak memory 199268 kb
Host smart-b5320487-08b6-4dc8-a1b5-1783fa013bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603235089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.2603235089
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.1601579875
Short name T468
Test name
Test status
Simulation time 122357634 ps
CPU time 1.12 seconds
Started Dec 24 12:25:35 PM PST 23
Finished Dec 24 12:25:38 PM PST 23
Peak memory 199304 kb
Host smart-24cc529b-2a26-438e-86ac-f3f8317f2afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601579875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.1601579875
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.2848992830
Short name T433
Test name
Test status
Simulation time 7731508941 ps
CPU time 32.88 seconds
Started Dec 24 12:27:10 PM PST 23
Finished Dec 24 12:27:47 PM PST 23
Peak memory 199436 kb
Host smart-e374bcc7-07e0-4139-b743-1ed016e1529b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848992830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.2848992830
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.2477920747
Short name T610
Test name
Test status
Simulation time 421613541 ps
CPU time 2.26 seconds
Started Dec 24 12:29:00 PM PST 23
Finished Dec 24 12:29:11 PM PST 23
Peak memory 199220 kb
Host smart-c79b0d04-404c-4632-a0ee-f8f6bc9a4765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477920747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.2477920747
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.2824565512
Short name T605
Test name
Test status
Simulation time 153156736 ps
CPU time 0.98 seconds
Started Dec 24 12:27:12 PM PST 23
Finished Dec 24 12:27:16 PM PST 23
Peak memory 199220 kb
Host smart-a21b5fc7-fd10-4253-a136-0f269cf86b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824565512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.2824565512
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.4046674067
Short name T466
Test name
Test status
Simulation time 57821870 ps
CPU time 0.71 seconds
Started Dec 24 12:25:34 PM PST 23
Finished Dec 24 12:25:36 PM PST 23
Peak memory 198948 kb
Host smart-a42525f3-02c0-4023-98c5-ae207f877eb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046674067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.4046674067
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.2720267040
Short name T314
Test name
Test status
Simulation time 1228835809 ps
CPU time 6 seconds
Started Dec 24 12:25:39 PM PST 23
Finished Dec 24 12:25:47 PM PST 23
Peak memory 220308 kb
Host smart-4ba2fdac-62c3-48ea-aaf9-d1d943715c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720267040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.2720267040
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.1659419515
Short name T158
Test name
Test status
Simulation time 244281551 ps
CPU time 1.1 seconds
Started Dec 24 12:28:09 PM PST 23
Finished Dec 24 12:28:25 PM PST 23
Peak memory 215616 kb
Host smart-af197903-ed7e-451a-b4c5-7ffe7389162e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659419515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.1659419515
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.4253461688
Short name T493
Test name
Test status
Simulation time 151906974 ps
CPU time 0.85 seconds
Started Dec 24 12:29:26 PM PST 23
Finished Dec 24 12:29:37 PM PST 23
Peak memory 198224 kb
Host smart-254db715-6d5c-46d8-9009-b8699af85fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253461688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.4253461688
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.2021291450
Short name T444
Test name
Test status
Simulation time 969570482 ps
CPU time 4.71 seconds
Started Dec 24 12:27:17 PM PST 23
Finished Dec 24 12:27:26 PM PST 23
Peak memory 199280 kb
Host smart-a5925af3-567e-4a98-9f70-4fe0c18126e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021291450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.2021291450
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.3920488339
Short name T596
Test name
Test status
Simulation time 173194076 ps
CPU time 1.17 seconds
Started Dec 24 12:27:57 PM PST 23
Finished Dec 24 12:28:11 PM PST 23
Peak memory 197824 kb
Host smart-262450a0-43ee-455a-8aac-147b4163a065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920488339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.3920488339
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.83964996
Short name T548
Test name
Test status
Simulation time 114412988 ps
CPU time 1.1 seconds
Started Dec 24 12:27:27 PM PST 23
Finished Dec 24 12:27:31 PM PST 23
Peak memory 199288 kb
Host smart-3de9d1cc-f78b-4771-932b-72f23388f543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83964996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.83964996
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.2406446929
Short name T339
Test name
Test status
Simulation time 1348997391 ps
CPU time 5.64 seconds
Started Dec 24 12:30:11 PM PST 23
Finished Dec 24 12:30:41 PM PST 23
Peak memory 199404 kb
Host smart-73af5591-0ddc-432d-97b5-11eaa823c244
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406446929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.2406446929
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.688466284
Short name T323
Test name
Test status
Simulation time 355027659 ps
CPU time 2 seconds
Started Dec 24 12:25:55 PM PST 23
Finished Dec 24 12:25:59 PM PST 23
Peak memory 199108 kb
Host smart-4565c4a0-4beb-446e-ae00-6d61009dcd23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688466284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.688466284
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.1463265625
Short name T565
Test name
Test status
Simulation time 126583265 ps
CPU time 0.89 seconds
Started Dec 24 12:28:06 PM PST 23
Finished Dec 24 12:28:20 PM PST 23
Peak memory 199008 kb
Host smart-d1bc7296-107b-42ef-a4fe-044e81309626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463265625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.1463265625
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.2590631227
Short name T582
Test name
Test status
Simulation time 59498532 ps
CPU time 0.7 seconds
Started Dec 24 12:26:27 PM PST 23
Finished Dec 24 12:26:29 PM PST 23
Peak memory 199008 kb
Host smart-2262278e-fe5f-47da-8d58-4f2fd0008c9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590631227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.2590631227
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.3603035391
Short name T518
Test name
Test status
Simulation time 2348879589 ps
CPU time 8.18 seconds
Started Dec 24 12:25:47 PM PST 23
Finished Dec 24 12:25:57 PM PST 23
Peak memory 217868 kb
Host smart-f8324714-3568-4188-924a-e46d6be3020f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603035391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.3603035391
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.2355529615
Short name T36
Test name
Test status
Simulation time 243909304 ps
CPU time 1.1 seconds
Started Dec 24 12:26:18 PM PST 23
Finished Dec 24 12:26:22 PM PST 23
Peak memory 216320 kb
Host smart-31d7bb52-2164-415b-a020-0d4d7d0e1172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355529615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.2355529615
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.3634256542
Short name T476
Test name
Test status
Simulation time 199196830 ps
CPU time 0.87 seconds
Started Dec 24 12:27:57 PM PST 23
Finished Dec 24 12:28:10 PM PST 23
Peak memory 197568 kb
Host smart-32d05569-2e8b-4154-beab-8f0d8475524c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634256542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.3634256542
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.1946071844
Short name T411
Test name
Test status
Simulation time 1967959473 ps
CPU time 7.66 seconds
Started Dec 24 12:28:07 PM PST 23
Finished Dec 24 12:28:34 PM PST 23
Peak memory 199152 kb
Host smart-6d678abf-f7ab-48c9-9821-0c1ca0a50b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946071844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.1946071844
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.2959086872
Short name T428
Test name
Test status
Simulation time 170029297 ps
CPU time 1.15 seconds
Started Dec 24 12:26:18 PM PST 23
Finished Dec 24 12:26:22 PM PST 23
Peak memory 199200 kb
Host smart-d6be86b8-8cca-4f00-b779-629d8059b4e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959086872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.2959086872
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.1899298948
Short name T303
Test name
Test status
Simulation time 258034810 ps
CPU time 1.77 seconds
Started Dec 24 12:28:01 PM PST 23
Finished Dec 24 12:28:24 PM PST 23
Peak memory 199184 kb
Host smart-5fc02fa5-ffd1-40c5-914a-29c16f7741ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899298948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.1899298948
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.1483147200
Short name T92
Test name
Test status
Simulation time 133028581 ps
CPU time 1.63 seconds
Started Dec 24 12:25:40 PM PST 23
Finished Dec 24 12:25:43 PM PST 23
Peak memory 199092 kb
Host smart-5d20cfac-7cd6-4ad8-868e-853dc77e7b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483147200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.1483147200
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.2488861498
Short name T362
Test name
Test status
Simulation time 233658853 ps
CPU time 1.44 seconds
Started Dec 24 12:25:39 PM PST 23
Finished Dec 24 12:25:43 PM PST 23
Peak memory 199280 kb
Host smart-569dea19-fc50-449c-bcc7-9298f4cb712c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488861498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.2488861498
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.1739407051
Short name T37
Test name
Test status
Simulation time 81654393 ps
CPU time 0.79 seconds
Started Dec 24 12:26:53 PM PST 23
Finished Dec 24 12:26:57 PM PST 23
Peak memory 198628 kb
Host smart-522a044f-68f1-463a-a119-277aee0513d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739407051 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.1739407051
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.834544492
Short name T469
Test name
Test status
Simulation time 2340473971 ps
CPU time 7.73 seconds
Started Dec 24 12:27:14 PM PST 23
Finished Dec 24 12:27:24 PM PST 23
Peak memory 218032 kb
Host smart-1b60e2f0-c3c2-4737-b3d9-2051f99773e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834544492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.834544492
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.3622416646
Short name T448
Test name
Test status
Simulation time 243526869 ps
CPU time 1.18 seconds
Started Dec 24 12:25:24 PM PST 23
Finished Dec 24 12:25:26 PM PST 23
Peak memory 215472 kb
Host smart-878788e0-0367-46dd-b9cb-f03639b3eaf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622416646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.3622416646
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.4118442524
Short name T612
Test name
Test status
Simulation time 125992275 ps
CPU time 0.81 seconds
Started Dec 24 12:25:35 PM PST 23
Finished Dec 24 12:25:37 PM PST 23
Peak memory 199004 kb
Host smart-0bd0d28b-f4cd-4502-84b5-814ceabedda3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118442524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.4118442524
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.579243250
Short name T70
Test name
Test status
Simulation time 8307179516 ps
CPU time 15.09 seconds
Started Dec 24 12:26:53 PM PST 23
Finished Dec 24 12:27:11 PM PST 23
Peak memory 215392 kb
Host smart-48b9e96b-1d50-48b5-979a-57ae1652ebda
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579243250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.579243250
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.2974770367
Short name T385
Test name
Test status
Simulation time 155984465 ps
CPU time 1.11 seconds
Started Dec 24 12:26:54 PM PST 23
Finished Dec 24 12:26:58 PM PST 23
Peak memory 199128 kb
Host smart-269fb4fb-a6e7-4f62-8c81-abe7b98609d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974770367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.2974770367
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.1430327062
Short name T289
Test name
Test status
Simulation time 198779322 ps
CPU time 1.36 seconds
Started Dec 24 12:26:12 PM PST 23
Finished Dec 24 12:26:15 PM PST 23
Peak memory 199100 kb
Host smart-67d1edb6-0498-4260-863a-7c34a0c536ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430327062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.1430327062
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.2324505868
Short name T490
Test name
Test status
Simulation time 5704488264 ps
CPU time 27.51 seconds
Started Dec 24 12:26:38 PM PST 23
Finished Dec 24 12:27:09 PM PST 23
Peak memory 199480 kb
Host smart-ef061616-8747-4045-84d2-24466d0ecaf9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324505868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.2324505868
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.343230569
Short name T245
Test name
Test status
Simulation time 435030724 ps
CPU time 2.25 seconds
Started Dec 24 12:27:23 PM PST 23
Finished Dec 24 12:27:29 PM PST 23
Peak memory 199108 kb
Host smart-ba005acd-09e1-4534-88a0-10c9bf1224d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343230569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.343230569
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.808884619
Short name T54
Test name
Test status
Simulation time 75744323 ps
CPU time 0.72 seconds
Started Dec 24 12:26:52 PM PST 23
Finished Dec 24 12:26:56 PM PST 23
Peak memory 199136 kb
Host smart-03fe5c3b-1e25-4e34-bd35-543106a6e7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808884619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.808884619
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.3799622630
Short name T313
Test name
Test status
Simulation time 59356149 ps
CPU time 0.73 seconds
Started Dec 24 12:26:19 PM PST 23
Finished Dec 24 12:26:21 PM PST 23
Peak memory 199080 kb
Host smart-920ec62e-10ee-4973-bfbc-e40f367a331c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799622630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.3799622630
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.3582446754
Short name T427
Test name
Test status
Simulation time 2175007355 ps
CPU time 7.42 seconds
Started Dec 24 12:27:56 PM PST 23
Finished Dec 24 12:28:17 PM PST 23
Peak memory 219236 kb
Host smart-a528d2c1-1a97-4563-9bde-c8720cfb2c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582446754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.3582446754
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.2195214279
Short name T394
Test name
Test status
Simulation time 243792636 ps
CPU time 1.1 seconds
Started Dec 24 12:28:46 PM PST 23
Finished Dec 24 12:28:56 PM PST 23
Peak memory 216052 kb
Host smart-f68279ff-7d16-4972-8e11-07a9bf9d27c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195214279 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.2195214279
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.950957203
Short name T485
Test name
Test status
Simulation time 166273082 ps
CPU time 0.82 seconds
Started Dec 24 12:25:38 PM PST 23
Finished Dec 24 12:25:42 PM PST 23
Peak memory 198964 kb
Host smart-0668cc86-7124-455d-970a-f371bb5152b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950957203 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.950957203
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.1908732881
Short name T438
Test name
Test status
Simulation time 962946513 ps
CPU time 4.62 seconds
Started Dec 24 12:27:01 PM PST 23
Finished Dec 24 12:27:11 PM PST 23
Peak memory 199300 kb
Host smart-0c11862a-7566-4382-a349-2311299b1bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908732881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.1908732881
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.2701277712
Short name T11
Test name
Test status
Simulation time 152033894 ps
CPU time 1.11 seconds
Started Dec 24 12:25:35 PM PST 23
Finished Dec 24 12:25:38 PM PST 23
Peak memory 199160 kb
Host smart-1904dba3-37be-4628-a993-2f8a30d93f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701277712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.2701277712
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.2681722451
Short name T521
Test name
Test status
Simulation time 241397747 ps
CPU time 1.55 seconds
Started Dec 24 12:26:18 PM PST 23
Finished Dec 24 12:26:22 PM PST 23
Peak memory 199232 kb
Host smart-6d1b51cf-f44d-420f-99ca-5b7b3542e186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681722451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.2681722451
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.3933013544
Short name T328
Test name
Test status
Simulation time 7333054379 ps
CPU time 24.06 seconds
Started Dec 24 12:28:46 PM PST 23
Finished Dec 24 12:29:18 PM PST 23
Peak memory 199228 kb
Host smart-fe4ea57b-2666-4e4b-a57d-667418d55006
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933013544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.3933013544
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.3525254333
Short name T546
Test name
Test status
Simulation time 131522610 ps
CPU time 1.72 seconds
Started Dec 24 12:26:15 PM PST 23
Finished Dec 24 12:26:18 PM PST 23
Peak memory 199232 kb
Host smart-8c5de5cc-5c26-4d14-8ba8-dc361e537a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525254333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.3525254333
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.783790076
Short name T471
Test name
Test status
Simulation time 163983184 ps
CPU time 1.06 seconds
Started Dec 24 12:26:24 PM PST 23
Finished Dec 24 12:26:29 PM PST 23
Peak memory 199172 kb
Host smart-211e1bc1-497c-4545-b3cb-d884a4a8d58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783790076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.783790076
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.2918590419
Short name T262
Test name
Test status
Simulation time 75030302 ps
CPU time 0.74 seconds
Started Dec 24 12:25:48 PM PST 23
Finished Dec 24 12:25:50 PM PST 23
Peak memory 199052 kb
Host smart-d5ca54c6-4e0d-455f-8294-49c8728443d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918590419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.2918590419
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.1877257774
Short name T510
Test name
Test status
Simulation time 1227049468 ps
CPU time 5.75 seconds
Started Dec 24 12:25:42 PM PST 23
Finished Dec 24 12:25:51 PM PST 23
Peak memory 221584 kb
Host smart-c20d6c7b-42d2-43d6-bb64-bd1433ff095a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877257774 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.1877257774
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.2056271592
Short name T306
Test name
Test status
Simulation time 243786772 ps
CPU time 1.06 seconds
Started Dec 24 12:29:28 PM PST 23
Finished Dec 24 12:29:40 PM PST 23
Peak memory 216212 kb
Host smart-ea93f32c-e779-4c5b-8723-52ebcf964bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056271592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.2056271592
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.4247184254
Short name T515
Test name
Test status
Simulation time 168151371 ps
CPU time 0.85 seconds
Started Dec 24 12:27:01 PM PST 23
Finished Dec 24 12:27:07 PM PST 23
Peak memory 199208 kb
Host smart-ef10e696-4d84-49f2-83ac-f497a05851a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247184254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.4247184254
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.1029802552
Short name T247
Test name
Test status
Simulation time 1186410268 ps
CPU time 5.98 seconds
Started Dec 24 12:26:49 PM PST 23
Finished Dec 24 12:26:57 PM PST 23
Peak memory 199272 kb
Host smart-9505c27e-658f-42f8-8ca8-a7b812201227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029802552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.1029802552
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.4189373064
Short name T140
Test name
Test status
Simulation time 99688379 ps
CPU time 0.91 seconds
Started Dec 24 12:29:30 PM PST 23
Finished Dec 24 12:29:42 PM PST 23
Peak memory 199260 kb
Host smart-56fcbc4a-302b-4c0c-ac4e-31ee6e959230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189373064 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.4189373064
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.2698711933
Short name T538
Test name
Test status
Simulation time 198024947 ps
CPU time 1.37 seconds
Started Dec 24 12:26:58 PM PST 23
Finished Dec 24 12:27:04 PM PST 23
Peak memory 199580 kb
Host smart-f9de9721-ff73-466d-8d54-441e21800c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698711933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.2698711933
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.216673322
Short name T304
Test name
Test status
Simulation time 159528001 ps
CPU time 1.21 seconds
Started Dec 24 12:25:55 PM PST 23
Finished Dec 24 12:25:57 PM PST 23
Peak memory 199248 kb
Host smart-2ed49353-94fe-451a-bf97-1d23e0c32777
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216673322 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.216673322
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.2425939505
Short name T274
Test name
Test status
Simulation time 114038399 ps
CPU time 1.33 seconds
Started Dec 24 12:25:40 PM PST 23
Finished Dec 24 12:25:43 PM PST 23
Peak memory 199256 kb
Host smart-fa527171-c536-4760-9fae-28c965c742b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425939505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.2425939505
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.2161161494
Short name T82
Test name
Test status
Simulation time 110942553 ps
CPU time 0.86 seconds
Started Dec 24 12:26:55 PM PST 23
Finished Dec 24 12:26:59 PM PST 23
Peak memory 199160 kb
Host smart-a71ecb05-d4f6-4f02-a30b-ffd24b373ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161161494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.2161161494
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.3188448240
Short name T400
Test name
Test status
Simulation time 55864380 ps
CPU time 0.66 seconds
Started Dec 24 12:25:46 PM PST 23
Finished Dec 24 12:25:49 PM PST 23
Peak memory 199060 kb
Host smart-0151db12-70b3-4117-8fa2-1a04c61f4cd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188448240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.3188448240
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.2326052553
Short name T595
Test name
Test status
Simulation time 1906746304 ps
CPU time 6.65 seconds
Started Dec 24 12:29:28 PM PST 23
Finished Dec 24 12:29:45 PM PST 23
Peak memory 217108 kb
Host smart-9d0c60d5-de54-44d3-8ed4-56eed4488b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326052553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.2326052553
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.3683781556
Short name T2
Test name
Test status
Simulation time 245788168 ps
CPU time 1.01 seconds
Started Dec 24 12:27:57 PM PST 23
Finished Dec 24 12:28:11 PM PST 23
Peak memory 216340 kb
Host smart-8cc47b8c-e34b-4886-9166-0441d8a4daff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683781556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.3683781556
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.297155630
Short name T430
Test name
Test status
Simulation time 79447250 ps
CPU time 0.7 seconds
Started Dec 24 12:25:48 PM PST 23
Finished Dec 24 12:25:51 PM PST 23
Peak memory 198968 kb
Host smart-dc5ca1dd-e19e-4208-93c7-8b914bf566b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297155630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.297155630
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.183673018
Short name T305
Test name
Test status
Simulation time 1613038968 ps
CPU time 6.1 seconds
Started Dec 24 12:26:45 PM PST 23
Finished Dec 24 12:26:53 PM PST 23
Peak memory 199304 kb
Host smart-96edff3d-5188-4c7f-a6b1-f59104c7acad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183673018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.183673018
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.3186063413
Short name T146
Test name
Test status
Simulation time 172815484 ps
CPU time 1.1 seconds
Started Dec 24 12:26:10 PM PST 23
Finished Dec 24 12:26:13 PM PST 23
Peak memory 199204 kb
Host smart-7b13c852-8d2b-4a9e-9612-2ae36ab74c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186063413 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.3186063413
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.2890342856
Short name T572
Test name
Test status
Simulation time 263662274 ps
CPU time 1.57 seconds
Started Dec 24 12:26:23 PM PST 23
Finished Dec 24 12:26:28 PM PST 23
Peak memory 199420 kb
Host smart-a83ec22d-75f2-47fe-b565-9fb77fc51d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890342856 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.2890342856
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.1212304930
Short name T287
Test name
Test status
Simulation time 1986206220 ps
CPU time 8.17 seconds
Started Dec 24 12:26:11 PM PST 23
Finished Dec 24 12:26:21 PM PST 23
Peak memory 198672 kb
Host smart-15ab05bf-3244-432a-b40d-3b95d19cc0d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212304930 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.1212304930
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.458194792
Short name T375
Test name
Test status
Simulation time 480901971 ps
CPU time 2.47 seconds
Started Dec 24 12:26:15 PM PST 23
Finished Dec 24 12:26:20 PM PST 23
Peak memory 199156 kb
Host smart-47f1a0db-a67d-4aa1-a7b1-d9947defe050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458194792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.458194792
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.4141862366
Short name T85
Test name
Test status
Simulation time 86444283 ps
CPU time 0.81 seconds
Started Dec 24 12:25:45 PM PST 23
Finished Dec 24 12:25:47 PM PST 23
Peak memory 199172 kb
Host smart-e0b4b8e4-9c11-44a9-9659-dbea04434026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141862366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.4141862366
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.3041719309
Short name T156
Test name
Test status
Simulation time 66694383 ps
CPU time 0.74 seconds
Started Dec 24 12:26:33 PM PST 23
Finished Dec 24 12:26:35 PM PST 23
Peak memory 199068 kb
Host smart-a11e39e5-7bb9-4d99-9ee6-8f0161204a20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041719309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.3041719309
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.2859149878
Short name T616
Test name
Test status
Simulation time 1225133658 ps
CPU time 5.21 seconds
Started Dec 24 12:29:33 PM PST 23
Finished Dec 24 12:29:51 PM PST 23
Peak memory 216084 kb
Host smart-690ac81a-2b2a-4942-95fa-365acfd5e9da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859149878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.2859149878
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.1763707763
Short name T259
Test name
Test status
Simulation time 243989691 ps
CPU time 1.18 seconds
Started Dec 24 12:26:28 PM PST 23
Finished Dec 24 12:26:31 PM PST 23
Peak memory 216244 kb
Host smart-d817efbd-b44c-44cf-922e-293181055161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763707763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.1763707763
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.258459825
Short name T285
Test name
Test status
Simulation time 123444378 ps
CPU time 0.8 seconds
Started Dec 24 12:25:46 PM PST 23
Finished Dec 24 12:25:49 PM PST 23
Peak memory 199036 kb
Host smart-0d3e1c1c-5eb1-4f94-bfc7-cc22f8f573fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258459825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.258459825
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.3971640964
Short name T49
Test name
Test status
Simulation time 936117354 ps
CPU time 5.12 seconds
Started Dec 24 12:25:45 PM PST 23
Finished Dec 24 12:25:52 PM PST 23
Peak memory 199352 kb
Host smart-bd5ed7da-8af7-4957-ad0f-4f208ef8f841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971640964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.3971640964
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.838915463
Short name T419
Test name
Test status
Simulation time 106580938 ps
CPU time 1 seconds
Started Dec 24 12:27:57 PM PST 23
Finished Dec 24 12:28:11 PM PST 23
Peak memory 199204 kb
Host smart-a3430640-2872-48d4-ab97-1417904e96b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838915463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.838915463
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.3387997396
Short name T309
Test name
Test status
Simulation time 199648596 ps
CPU time 1.4 seconds
Started Dec 24 12:26:22 PM PST 23
Finished Dec 24 12:26:26 PM PST 23
Peak memory 199320 kb
Host smart-c153f694-c247-45ba-87db-a894f9c6b808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387997396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.3387997396
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.2965547372
Short name T391
Test name
Test status
Simulation time 4796946107 ps
CPU time 21.54 seconds
Started Dec 24 12:28:01 PM PST 23
Finished Dec 24 12:28:36 PM PST 23
Peak memory 199528 kb
Host smart-1799699c-d784-46b5-9543-b7d988c55ba2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965547372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.2965547372
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.2289383793
Short name T507
Test name
Test status
Simulation time 325622347 ps
CPU time 1.96 seconds
Started Dec 24 12:28:49 PM PST 23
Finished Dec 24 12:29:02 PM PST 23
Peak memory 199220 kb
Host smart-737194c9-92b0-4b51-8643-7cfa6d6cda1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289383793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.2289383793
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.3523860737
Short name T91
Test name
Test status
Simulation time 63981682 ps
CPU time 0.74 seconds
Started Dec 24 12:25:41 PM PST 23
Finished Dec 24 12:25:43 PM PST 23
Peak memory 199268 kb
Host smart-9c963127-6231-4783-a165-593de990a639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523860737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.3523860737
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.2313850540
Short name T453
Test name
Test status
Simulation time 74244710 ps
CPU time 0.78 seconds
Started Dec 24 12:28:16 PM PST 23
Finished Dec 24 12:28:30 PM PST 23
Peak memory 197496 kb
Host smart-7842a7f8-84c0-4b6a-a832-a3a7f7694aed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313850540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.2313850540
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.1109638134
Short name T460
Test name
Test status
Simulation time 1218960159 ps
CPU time 6.1 seconds
Started Dec 24 12:27:34 PM PST 23
Finished Dec 24 12:27:42 PM PST 23
Peak memory 215376 kb
Host smart-41eec611-66fd-4f54-9d8f-4d319b37503f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109638134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.1109638134
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.849861434
Short name T41
Test name
Test status
Simulation time 243817164 ps
CPU time 1.18 seconds
Started Dec 24 12:27:26 PM PST 23
Finished Dec 24 12:27:31 PM PST 23
Peak memory 214880 kb
Host smart-92f7f5f7-aa98-4b14-bda7-809686c32319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849861434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.849861434
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.2137827307
Short name T417
Test name
Test status
Simulation time 181657669 ps
CPU time 0.84 seconds
Started Dec 24 12:26:38 PM PST 23
Finished Dec 24 12:26:43 PM PST 23
Peak memory 198880 kb
Host smart-59b1e635-a062-4805-8e32-fd984bf7be3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137827307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.2137827307
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.2227979711
Short name T431
Test name
Test status
Simulation time 723166461 ps
CPU time 3.6 seconds
Started Dec 24 12:27:59 PM PST 23
Finished Dec 24 12:28:16 PM PST 23
Peak memory 199352 kb
Host smart-d8f7eed3-a814-4f20-9afb-b11b3a0bd47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227979711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.2227979711
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.3480304056
Short name T142
Test name
Test status
Simulation time 177030201 ps
CPU time 1.1 seconds
Started Dec 24 12:28:50 PM PST 23
Finished Dec 24 12:29:02 PM PST 23
Peak memory 198708 kb
Host smart-fbf79e95-5c68-43ab-be21-fad3e941057c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480304056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.3480304056
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.2149316274
Short name T529
Test name
Test status
Simulation time 121531681 ps
CPU time 1.1 seconds
Started Dec 24 12:27:57 PM PST 23
Finished Dec 24 12:28:11 PM PST 23
Peak memory 199400 kb
Host smart-801b447a-3180-49f3-8743-34f6d0fe20e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149316274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.2149316274
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.1468618835
Short name T562
Test name
Test status
Simulation time 6806912207 ps
CPU time 29.68 seconds
Started Dec 24 12:26:32 PM PST 23
Finished Dec 24 12:27:03 PM PST 23
Peak memory 199380 kb
Host smart-8f6c9d25-18e8-456d-9f0c-383e5fcb428a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468618835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.1468618835
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.2574701212
Short name T532
Test name
Test status
Simulation time 405250096 ps
CPU time 2.17 seconds
Started Dec 24 12:26:45 PM PST 23
Finished Dec 24 12:26:49 PM PST 23
Peak memory 199216 kb
Host smart-428d2eab-7486-4b0f-916b-5648b75cef00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574701212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.2574701212
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.996845761
Short name T536
Test name
Test status
Simulation time 86074054 ps
CPU time 0.78 seconds
Started Dec 24 12:27:57 PM PST 23
Finished Dec 24 12:28:10 PM PST 23
Peak memory 199212 kb
Host smart-c1556e47-1f0b-41c6-8a92-421b6c3390e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996845761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.996845761
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.907222396
Short name T429
Test name
Test status
Simulation time 84124454 ps
CPU time 0.81 seconds
Started Dec 24 12:27:26 PM PST 23
Finished Dec 24 12:27:30 PM PST 23
Peak memory 197432 kb
Host smart-1d3a5b5f-ff78-47a1-9e71-97cbf51218f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907222396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.907222396
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.1703003902
Short name T29
Test name
Test status
Simulation time 2361706674 ps
CPU time 7.75 seconds
Started Dec 24 12:26:15 PM PST 23
Finished Dec 24 12:26:25 PM PST 23
Peak memory 229176 kb
Host smart-38a6eaf8-2352-4643-801b-67cd64225112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703003902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.1703003902
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.1551040383
Short name T410
Test name
Test status
Simulation time 244650399 ps
CPU time 1.13 seconds
Started Dec 24 12:27:57 PM PST 23
Finished Dec 24 12:28:12 PM PST 23
Peak memory 216120 kb
Host smart-2e263985-8349-4bed-96ac-e323f8d0a55c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551040383 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.1551040383
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.2060927900
Short name T421
Test name
Test status
Simulation time 182328550 ps
CPU time 0.88 seconds
Started Dec 24 12:27:02 PM PST 23
Finished Dec 24 12:27:07 PM PST 23
Peak memory 199012 kb
Host smart-f87e94ce-3909-4cde-8211-bffe2cc64c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060927900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.2060927900
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.1359798276
Short name T348
Test name
Test status
Simulation time 949615386 ps
CPU time 4.41 seconds
Started Dec 24 12:27:57 PM PST 23
Finished Dec 24 12:28:15 PM PST 23
Peak memory 199352 kb
Host smart-77e0f631-84b1-4c79-aa89-7f5340c97f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359798276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.1359798276
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.2009638639
Short name T251
Test name
Test status
Simulation time 107204284 ps
CPU time 1.1 seconds
Started Dec 24 12:26:39 PM PST 23
Finished Dec 24 12:26:44 PM PST 23
Peak memory 199296 kb
Host smart-63a967d2-a0f4-4b23-98d6-748e7e9fae42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009638639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.2009638639
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.1133399834
Short name T593
Test name
Test status
Simulation time 120615848 ps
CPU time 1.17 seconds
Started Dec 24 12:26:44 PM PST 23
Finished Dec 24 12:26:48 PM PST 23
Peak memory 199284 kb
Host smart-67f00cfd-f34d-4ac9-b757-f87b8ee328bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133399834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.1133399834
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.3156491069
Short name T58
Test name
Test status
Simulation time 5518749725 ps
CPU time 19.56 seconds
Started Dec 24 12:28:16 PM PST 23
Finished Dec 24 12:28:48 PM PST 23
Peak memory 197896 kb
Host smart-531d617e-261f-4b6d-8dab-29029dacfff6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156491069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.3156491069
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.4129589475
Short name T286
Test name
Test status
Simulation time 299819560 ps
CPU time 2.04 seconds
Started Dec 24 12:26:38 PM PST 23
Finished Dec 24 12:26:44 PM PST 23
Peak memory 199036 kb
Host smart-f23db886-fcf7-464e-ac24-4c4d731515c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129589475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.4129589475
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.305278753
Short name T272
Test name
Test status
Simulation time 271081471 ps
CPU time 1.41 seconds
Started Dec 24 12:27:57 PM PST 23
Finished Dec 24 12:28:12 PM PST 23
Peak memory 199044 kb
Host smart-7112372f-e94e-47b3-bd9a-33639c74b9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305278753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.305278753
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.3009900270
Short name T334
Test name
Test status
Simulation time 82869334 ps
CPU time 0.8 seconds
Started Dec 24 12:27:15 PM PST 23
Finished Dec 24 12:27:19 PM PST 23
Peak memory 199104 kb
Host smart-c2261815-7071-4d6e-9907-fd65d8917c84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009900270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.3009900270
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.756625571
Short name T43
Test name
Test status
Simulation time 1900085964 ps
CPU time 7.19 seconds
Started Dec 24 12:27:21 PM PST 23
Finished Dec 24 12:27:32 PM PST 23
Peak memory 221100 kb
Host smart-38abf68a-c1ea-4946-ae64-11c029027d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756625571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.756625571
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.1813351364
Short name T244
Test name
Test status
Simulation time 243819690 ps
CPU time 1.05 seconds
Started Dec 24 12:29:44 PM PST 23
Finished Dec 24 12:30:06 PM PST 23
Peak memory 216404 kb
Host smart-16eac839-b5a2-4025-a4b8-06cc34059b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813351364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.1813351364
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.3461940829
Short name T5
Test name
Test status
Simulation time 178109274 ps
CPU time 0.81 seconds
Started Dec 24 12:29:45 PM PST 23
Finished Dec 24 12:30:07 PM PST 23
Peak memory 199112 kb
Host smart-10d087ca-cb2d-413c-a51b-2a648a994c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461940829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.3461940829
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.693098246
Short name T109
Test name
Test status
Simulation time 1538467135 ps
CPU time 5.74 seconds
Started Dec 24 12:27:57 PM PST 23
Finished Dec 24 12:28:16 PM PST 23
Peak memory 199356 kb
Host smart-d1f94b83-5b05-4a86-8994-7ad82b494b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693098246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.693098246
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.2760027317
Short name T422
Test name
Test status
Simulation time 162154314 ps
CPU time 1.16 seconds
Started Dec 24 12:27:21 PM PST 23
Finished Dec 24 12:27:26 PM PST 23
Peak memory 199172 kb
Host smart-93ea8a65-22ac-400c-a25e-9b77421078eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760027317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.2760027317
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.1045080263
Short name T93
Test name
Test status
Simulation time 206488302 ps
CPU time 1.34 seconds
Started Dec 24 12:28:04 PM PST 23
Finished Dec 24 12:28:17 PM PST 23
Peak memory 199444 kb
Host smart-abbce3f7-961c-4e92-928e-374a2eda3f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045080263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.1045080263
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.1842278356
Short name T129
Test name
Test status
Simulation time 2704591106 ps
CPU time 9.86 seconds
Started Dec 24 12:27:32 PM PST 23
Finished Dec 24 12:27:43 PM PST 23
Peak memory 199464 kb
Host smart-8e45a49a-edef-4041-bbac-9fc3cc49ca42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842278356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.1842278356
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.4014832851
Short name T90
Test name
Test status
Simulation time 426871237 ps
CPU time 2.62 seconds
Started Dec 24 12:26:23 PM PST 23
Finished Dec 24 12:26:29 PM PST 23
Peak memory 199128 kb
Host smart-db495a8d-b825-43ba-bb50-749ba4217bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014832851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.4014832851
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.2243960265
Short name T316
Test name
Test status
Simulation time 108706936 ps
CPU time 0.87 seconds
Started Dec 24 12:28:17 PM PST 23
Finished Dec 24 12:28:30 PM PST 23
Peak memory 199208 kb
Host smart-fb4c604c-02a7-44ec-8a04-7ceb9fd98d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243960265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.2243960265
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.3493355553
Short name T567
Test name
Test status
Simulation time 77617473 ps
CPU time 0.79 seconds
Started Dec 24 12:26:08 PM PST 23
Finished Dec 24 12:26:11 PM PST 23
Peak memory 199036 kb
Host smart-26eb45c6-8d6b-495b-87ce-0cc9500e5132
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493355553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.3493355553
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.3571679979
Short name T487
Test name
Test status
Simulation time 1866830096 ps
CPU time 7.11 seconds
Started Dec 24 12:29:58 PM PST 23
Finished Dec 24 12:30:31 PM PST 23
Peak memory 217156 kb
Host smart-4986d55c-17b8-4feb-81d4-2056be30701d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571679979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.3571679979
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.1562414237
Short name T576
Test name
Test status
Simulation time 244653705 ps
CPU time 1.07 seconds
Started Dec 24 12:29:56 PM PST 23
Finished Dec 24 12:30:24 PM PST 23
Peak memory 216408 kb
Host smart-b90964cb-7d38-4a2f-a39d-74d97a506147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562414237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.1562414237
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.41130020
Short name T588
Test name
Test status
Simulation time 217499915 ps
CPU time 0.88 seconds
Started Dec 24 12:26:57 PM PST 23
Finished Dec 24 12:27:02 PM PST 23
Peak memory 198988 kb
Host smart-744b5022-f413-4bca-a371-cac66f9f60a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41130020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.41130020
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.451502428
Short name T130
Test name
Test status
Simulation time 1312496518 ps
CPU time 5.84 seconds
Started Dec 24 12:27:16 PM PST 23
Finished Dec 24 12:27:25 PM PST 23
Peak memory 199412 kb
Host smart-95b36288-aa9e-4fb6-888b-11e3123da2d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451502428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.451502428
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.3621699273
Short name T293
Test name
Test status
Simulation time 174565920 ps
CPU time 1.19 seconds
Started Dec 24 12:27:20 PM PST 23
Finished Dec 24 12:27:24 PM PST 23
Peak memory 199296 kb
Host smart-496beb2a-5384-4e3d-a7fa-9eb6ccdc0407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621699273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.3621699273
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.1774898036
Short name T294
Test name
Test status
Simulation time 260701952 ps
CPU time 1.55 seconds
Started Dec 24 12:28:05 PM PST 23
Finished Dec 24 12:28:19 PM PST 23
Peak memory 199380 kb
Host smart-8530fdd0-6b5f-4498-a8e5-a63c45f1f7db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774898036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.1774898036
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.4049302232
Short name T333
Test name
Test status
Simulation time 11620073139 ps
CPU time 46.59 seconds
Started Dec 24 12:27:27 PM PST 23
Finished Dec 24 12:28:16 PM PST 23
Peak memory 199484 kb
Host smart-adc05252-e562-4de5-bcd6-b0707c835754
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049302232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.4049302232
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.2862698263
Short name T292
Test name
Test status
Simulation time 291482979 ps
CPU time 1.84 seconds
Started Dec 24 12:26:28 PM PST 23
Finished Dec 24 12:26:33 PM PST 23
Peak memory 199308 kb
Host smart-fd9008a3-7c1e-4f55-908b-35fa98613e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862698263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.2862698263
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.4177669011
Short name T478
Test name
Test status
Simulation time 142078824 ps
CPU time 1.18 seconds
Started Dec 24 12:27:14 PM PST 23
Finished Dec 24 12:27:18 PM PST 23
Peak memory 199280 kb
Host smart-523316c4-6195-4d09-bc93-92054cdd3c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177669011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.4177669011
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.3142752154
Short name T519
Test name
Test status
Simulation time 66569456 ps
CPU time 0.7 seconds
Started Dec 24 12:28:03 PM PST 23
Finished Dec 24 12:28:16 PM PST 23
Peak memory 198948 kb
Host smart-bb57cb1d-a377-4253-8b86-2639c39f8840
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142752154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.3142752154
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.647224737
Short name T447
Test name
Test status
Simulation time 1223031879 ps
CPU time 5.71 seconds
Started Dec 24 12:27:38 PM PST 23
Finished Dec 24 12:27:45 PM PST 23
Peak memory 220160 kb
Host smart-5765c4c0-12d9-479b-81ed-a43ae3f5b7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647224737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.647224737
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.3388053253
Short name T157
Test name
Test status
Simulation time 245240027 ps
CPU time 1.02 seconds
Started Dec 24 12:28:03 PM PST 23
Finished Dec 24 12:28:17 PM PST 23
Peak memory 216656 kb
Host smart-9be59eb0-d552-4a79-8afb-8e6007bfbae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388053253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.3388053253
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.3628424208
Short name T449
Test name
Test status
Simulation time 132615401 ps
CPU time 0.74 seconds
Started Dec 24 12:26:15 PM PST 23
Finished Dec 24 12:26:18 PM PST 23
Peak memory 198996 kb
Host smart-8149bd24-9473-467c-9b03-bc67ebf3df05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628424208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.3628424208
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.3276219696
Short name T270
Test name
Test status
Simulation time 1605456424 ps
CPU time 5.75 seconds
Started Dec 24 12:27:25 PM PST 23
Finished Dec 24 12:27:34 PM PST 23
Peak memory 199464 kb
Host smart-25c21a7e-88d0-47ce-9715-b73ace782de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276219696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.3276219696
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.3720205282
Short name T376
Test name
Test status
Simulation time 110161949 ps
CPU time 1 seconds
Started Dec 24 12:25:58 PM PST 23
Finished Dec 24 12:26:02 PM PST 23
Peak memory 199300 kb
Host smart-2a92a935-91af-46d5-b137-bab6b2473ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720205282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.3720205282
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.967707148
Short name T473
Test name
Test status
Simulation time 118492372 ps
CPU time 1.21 seconds
Started Dec 24 12:25:43 PM PST 23
Finished Dec 24 12:25:47 PM PST 23
Peak memory 199344 kb
Host smart-0466cb67-4941-4248-9a2a-c916c891f352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967707148 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.967707148
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.3945680531
Short name T114
Test name
Test status
Simulation time 1685759481 ps
CPU time 8.59 seconds
Started Dec 24 12:25:55 PM PST 23
Finished Dec 24 12:26:05 PM PST 23
Peak memory 199404 kb
Host smart-5b8abd97-aa0c-4aa9-b7ff-16bd9f8edb4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945680531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.3945680531
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.4213546294
Short name T397
Test name
Test status
Simulation time 146663946 ps
CPU time 1.82 seconds
Started Dec 24 12:25:48 PM PST 23
Finished Dec 24 12:25:51 PM PST 23
Peak memory 199164 kb
Host smart-d671da49-2ce6-4064-8e73-facd91e90b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213546294 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.4213546294
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.1632544673
Short name T8
Test name
Test status
Simulation time 221778003 ps
CPU time 1.3 seconds
Started Dec 24 12:25:54 PM PST 23
Finished Dec 24 12:25:56 PM PST 23
Peak memory 199168 kb
Host smart-899a6e5e-99b7-410c-b2fd-bfd67fdbf42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632544673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.1632544673
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.2431133808
Short name T540
Test name
Test status
Simulation time 61783817 ps
CPU time 0.69 seconds
Started Dec 24 12:28:46 PM PST 23
Finished Dec 24 12:28:55 PM PST 23
Peak memory 198740 kb
Host smart-98e90366-f4fc-46c2-9668-c2a6fd7fa6f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431133808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.2431133808
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.1798852242
Short name T368
Test name
Test status
Simulation time 2350380563 ps
CPU time 7.8 seconds
Started Dec 24 12:28:07 PM PST 23
Finished Dec 24 12:28:28 PM PST 23
Peak memory 216744 kb
Host smart-7df900ef-74f2-4416-9c2b-4fed45e58f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798852242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.1798852242
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.1218649021
Short name T147
Test name
Test status
Simulation time 243455287 ps
CPU time 1.13 seconds
Started Dec 24 12:28:06 PM PST 23
Finished Dec 24 12:28:19 PM PST 23
Peak memory 216400 kb
Host smart-3fb1a71f-1b4d-4bbc-ba12-9fde325d973a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218649021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.1218649021
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.490856621
Short name T13
Test name
Test status
Simulation time 99283584 ps
CPU time 0.9 seconds
Started Dec 24 12:27:04 PM PST 23
Finished Dec 24 12:27:09 PM PST 23
Peak memory 199076 kb
Host smart-4f34b355-ad78-4be2-b5d8-1798d5f8ae52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490856621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.490856621
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.310406724
Short name T416
Test name
Test status
Simulation time 1386664526 ps
CPU time 5.26 seconds
Started Dec 24 12:28:03 PM PST 23
Finished Dec 24 12:28:27 PM PST 23
Peak memory 199368 kb
Host smart-40bac1e8-f702-4765-ab8e-ae6e05401649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310406724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.310406724
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.1613122678
Short name T326
Test name
Test status
Simulation time 171572039 ps
CPU time 1.17 seconds
Started Dec 24 12:27:02 PM PST 23
Finished Dec 24 12:27:08 PM PST 23
Peak memory 199256 kb
Host smart-7499adf6-e486-4bd3-b799-793816c7b831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613122678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.1613122678
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.908925326
Short name T442
Test name
Test status
Simulation time 114405851 ps
CPU time 1.1 seconds
Started Dec 24 12:28:03 PM PST 23
Finished Dec 24 12:28:17 PM PST 23
Peak memory 199280 kb
Host smart-f808f3a6-33be-4cb0-9794-aea14ad9e0f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908925326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.908925326
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.1434424836
Short name T311
Test name
Test status
Simulation time 4967075481 ps
CPU time 21.06 seconds
Started Dec 24 12:26:54 PM PST 23
Finished Dec 24 12:27:19 PM PST 23
Peak memory 199440 kb
Host smart-03af651b-bc9e-4a4c-98b9-becd68a4146c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434424836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.1434424836
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.740597087
Short name T48
Test name
Test status
Simulation time 328247198 ps
CPU time 2.22 seconds
Started Dec 24 12:25:56 PM PST 23
Finished Dec 24 12:26:01 PM PST 23
Peak memory 199208 kb
Host smart-7db0bec8-d496-408a-b814-d3ca45b01f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740597087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.740597087
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.2009325367
Short name T332
Test name
Test status
Simulation time 100364647 ps
CPU time 0.82 seconds
Started Dec 24 12:28:03 PM PST 23
Finished Dec 24 12:28:17 PM PST 23
Peak memory 198956 kb
Host smart-1ca12cd7-ebb4-4e68-8212-b28fd3c8837d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009325367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.2009325367
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.2470371329
Short name T253
Test name
Test status
Simulation time 66830470 ps
CPU time 0.79 seconds
Started Dec 24 12:26:28 PM PST 23
Finished Dec 24 12:26:30 PM PST 23
Peak memory 198060 kb
Host smart-8636b2c1-8625-44b3-aa63-39c7a26240fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470371329 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.2470371329
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.3123425929
Short name T586
Test name
Test status
Simulation time 1220659769 ps
CPU time 5.73 seconds
Started Dec 24 12:26:53 PM PST 23
Finished Dec 24 12:27:02 PM PST 23
Peak memory 215112 kb
Host smart-ec78f244-06ef-45fe-9ab1-2c2f16b3bfe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123425929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.3123425929
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.675072571
Short name T335
Test name
Test status
Simulation time 245023781 ps
CPU time 1.15 seconds
Started Dec 24 12:26:52 PM PST 23
Finished Dec 24 12:26:57 PM PST 23
Peak memory 214640 kb
Host smart-6e039873-5baf-4319-b132-1c53c05e42ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675072571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.675072571
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.612652430
Short name T291
Test name
Test status
Simulation time 112496855 ps
CPU time 0.77 seconds
Started Dec 24 12:27:15 PM PST 23
Finished Dec 24 12:27:18 PM PST 23
Peak memory 199016 kb
Host smart-dbd228e9-0b76-4e24-8afe-4482939f617c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612652430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.612652430
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.4262189414
Short name T608
Test name
Test status
Simulation time 1404044855 ps
CPU time 5.22 seconds
Started Dec 24 12:25:44 PM PST 23
Finished Dec 24 12:25:51 PM PST 23
Peak memory 199416 kb
Host smart-e2b2b1b2-dba1-4cf6-9a85-8039401a75d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262189414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.4262189414
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.3926885681
Short name T418
Test name
Test status
Simulation time 176574974 ps
CPU time 1.11 seconds
Started Dec 24 12:27:15 PM PST 23
Finished Dec 24 12:27:18 PM PST 23
Peak memory 199216 kb
Host smart-5ee1dd3f-67ab-42a8-a5d9-baac68b7faeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926885681 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.3926885681
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.1658355724
Short name T396
Test name
Test status
Simulation time 121535980 ps
CPU time 1.16 seconds
Started Dec 24 12:23:35 PM PST 23
Finished Dec 24 12:23:36 PM PST 23
Peak memory 199728 kb
Host smart-d0e902d9-fa64-4d72-b52e-9aee54af1c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658355724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.1658355724
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.2792850398
Short name T412
Test name
Test status
Simulation time 1753126677 ps
CPU time 7.37 seconds
Started Dec 24 12:27:23 PM PST 23
Finished Dec 24 12:27:35 PM PST 23
Peak memory 199300 kb
Host smart-78cfcd9f-442b-4172-a7c0-3e8a5c8fea77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792850398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.2792850398
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.541593681
Short name T457
Test name
Test status
Simulation time 395708701 ps
CPU time 2.21 seconds
Started Dec 24 12:27:23 PM PST 23
Finished Dec 24 12:27:30 PM PST 23
Peak memory 199160 kb
Host smart-03c7419d-0905-4369-88be-5d36614ba7ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541593681 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.541593681
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.158454256
Short name T575
Test name
Test status
Simulation time 61872854 ps
CPU time 0.82 seconds
Started Dec 24 12:26:52 PM PST 23
Finished Dec 24 12:26:57 PM PST 23
Peak memory 197480 kb
Host smart-910ac967-e501-43af-a482-197b6b1d8e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158454256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.158454256
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.3282007163
Short name T252
Test name
Test status
Simulation time 52776347 ps
CPU time 0.71 seconds
Started Dec 24 12:26:53 PM PST 23
Finished Dec 24 12:26:56 PM PST 23
Peak memory 198952 kb
Host smart-8821052c-d57c-475a-9f86-872e8993a1d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282007163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.3282007163
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.234605514
Short name T51
Test name
Test status
Simulation time 1885415141 ps
CPU time 7.37 seconds
Started Dec 24 12:27:23 PM PST 23
Finished Dec 24 12:27:35 PM PST 23
Peak memory 216540 kb
Host smart-408137ec-eff9-415a-84d2-de9b0d0d2802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234605514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.234605514
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.3590167527
Short name T288
Test name
Test status
Simulation time 243708723 ps
CPU time 1.07 seconds
Started Dec 24 12:26:54 PM PST 23
Finished Dec 24 12:26:58 PM PST 23
Peak memory 216368 kb
Host smart-96e8cbc5-432a-4f1f-8c91-84577f64a4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590167527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.3590167527
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.1394194285
Short name T15
Test name
Test status
Simulation time 77570621 ps
CPU time 0.69 seconds
Started Dec 24 12:27:23 PM PST 23
Finished Dec 24 12:27:28 PM PST 23
Peak memory 198952 kb
Host smart-1537e487-e06d-45aa-8ae8-2f2325a4b01e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394194285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.1394194285
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.4187510679
Short name T149
Test name
Test status
Simulation time 1340748191 ps
CPU time 5.4 seconds
Started Dec 24 12:25:18 PM PST 23
Finished Dec 24 12:25:25 PM PST 23
Peak memory 199352 kb
Host smart-5a925af0-953c-44e9-8b8c-db3b63fde5a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187510679 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.4187510679
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.11757877
Short name T434
Test name
Test status
Simulation time 155039912 ps
CPU time 1.12 seconds
Started Dec 24 12:26:57 PM PST 23
Finished Dec 24 12:27:02 PM PST 23
Peak memory 198000 kb
Host smart-f99316c2-0461-4dfb-a699-c42478820fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11757877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.11757877
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.4017313613
Short name T377
Test name
Test status
Simulation time 260707929 ps
CPU time 1.42 seconds
Started Dec 24 12:29:24 PM PST 23
Finished Dec 24 12:29:33 PM PST 23
Peak memory 199404 kb
Host smart-561a4e92-0046-4925-acd6-7ff299dec3bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017313613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.4017313613
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.1747640390
Short name T607
Test name
Test status
Simulation time 11761949627 ps
CPU time 39.97 seconds
Started Dec 24 12:27:23 PM PST 23
Finished Dec 24 12:28:07 PM PST 23
Peak memory 199360 kb
Host smart-8fb2e751-cfe5-4c4b-a131-dd15716b6f94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747640390 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.1747640390
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.940076397
Short name T10
Test name
Test status
Simulation time 372948566 ps
CPU time 2.38 seconds
Started Dec 24 12:25:44 PM PST 23
Finished Dec 24 12:25:49 PM PST 23
Peak memory 199224 kb
Host smart-700cd65c-180c-4ff0-962f-78ef0164eff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940076397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.940076397
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.4125693932
Short name T330
Test name
Test status
Simulation time 134654728 ps
CPU time 1.1 seconds
Started Dec 24 12:27:23 PM PST 23
Finished Dec 24 12:27:29 PM PST 23
Peak memory 199156 kb
Host smart-b19282e4-2ace-4b86-b112-1a059a7dc910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125693932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.4125693932
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.3022078924
Short name T553
Test name
Test status
Simulation time 70784954 ps
CPU time 0.77 seconds
Started Dec 24 12:26:16 PM PST 23
Finished Dec 24 12:26:20 PM PST 23
Peak memory 198932 kb
Host smart-77708a65-73ff-49f4-b1a0-41f937ca8b04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022078924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.3022078924
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.982353310
Short name T533
Test name
Test status
Simulation time 1227378098 ps
CPU time 5.51 seconds
Started Dec 24 12:28:57 PM PST 23
Finished Dec 24 12:29:13 PM PST 23
Peak memory 219376 kb
Host smart-488ea98b-1740-4089-9878-7815435b9855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982353310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.982353310
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.2414767730
Short name T150
Test name
Test status
Simulation time 244372910 ps
CPU time 1.07 seconds
Started Dec 24 12:25:49 PM PST 23
Finished Dec 24 12:25:52 PM PST 23
Peak memory 216332 kb
Host smart-f4dc2aad-2ce8-4719-9e5e-c1f6c2f1d41c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414767730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.2414767730
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.1950970500
Short name T336
Test name
Test status
Simulation time 160731564 ps
CPU time 0.9 seconds
Started Dec 24 12:26:57 PM PST 23
Finished Dec 24 12:27:01 PM PST 23
Peak memory 197644 kb
Host smart-dd35fa02-a289-46f0-be0c-7c50e582af0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950970500 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.1950970500
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.420760043
Short name T589
Test name
Test status
Simulation time 848531173 ps
CPU time 4.09 seconds
Started Dec 24 12:26:54 PM PST 23
Finished Dec 24 12:27:01 PM PST 23
Peak memory 199276 kb
Host smart-3c3a8c91-28ad-47e2-884a-6d1726fc253b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420760043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.420760043
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.2278264314
Short name T57
Test name
Test status
Simulation time 149448532 ps
CPU time 1.13 seconds
Started Dec 24 12:27:28 PM PST 23
Finished Dec 24 12:27:31 PM PST 23
Peak memory 199156 kb
Host smart-85578084-3f5a-4028-a4e7-f30688e9e0fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278264314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.2278264314
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.2697986517
Short name T525
Test name
Test status
Simulation time 110329201 ps
CPU time 1.11 seconds
Started Dec 24 12:25:42 PM PST 23
Finished Dec 24 12:25:45 PM PST 23
Peak memory 199288 kb
Host smart-2d264644-8c78-4180-91c2-1eb16bbafe0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697986517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.2697986517
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.2696960821
Short name T614
Test name
Test status
Simulation time 121147523 ps
CPU time 0.96 seconds
Started Dec 24 12:26:00 PM PST 23
Finished Dec 24 12:26:08 PM PST 23
Peak memory 199080 kb
Host smart-f3e8dfc0-f73f-4c75-bf47-ccea6d3a67f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696960821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.2696960821
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.2014278648
Short name T358
Test name
Test status
Simulation time 132916354 ps
CPU time 1.63 seconds
Started Dec 24 12:25:47 PM PST 23
Finished Dec 24 12:25:50 PM PST 23
Peak memory 199168 kb
Host smart-e8c37bef-8908-4e61-a0e0-2606963af5a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014278648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.2014278648
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.4051804523
Short name T383
Test name
Test status
Simulation time 189749254 ps
CPU time 1.41 seconds
Started Dec 24 12:26:04 PM PST 23
Finished Dec 24 12:26:10 PM PST 23
Peak memory 199252 kb
Host smart-46b012bf-d68e-4170-9fa0-a5023e91773f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051804523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.4051804523
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.3763178773
Short name T50
Test name
Test status
Simulation time 63197988 ps
CPU time 0.81 seconds
Started Dec 24 12:26:50 PM PST 23
Finished Dec 24 12:26:52 PM PST 23
Peak memory 198760 kb
Host smart-053b13fe-6ea5-49b1-9b28-e57857af2aa7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763178773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.3763178773
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.583827177
Short name T295
Test name
Test status
Simulation time 1895378359 ps
CPU time 8.04 seconds
Started Dec 24 12:25:17 PM PST 23
Finished Dec 24 12:25:26 PM PST 23
Peak memory 216768 kb
Host smart-48cd84d7-b714-4980-b4c2-9a742ccb2dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583827177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.583827177
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.1540503993
Short name T86
Test name
Test status
Simulation time 243985277 ps
CPU time 1.17 seconds
Started Dec 24 12:26:15 PM PST 23
Finished Dec 24 12:26:19 PM PST 23
Peak memory 216484 kb
Host smart-9cfa5c34-0bda-477c-8c50-d10f901ca48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540503993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.1540503993
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.2290203102
Short name T364
Test name
Test status
Simulation time 82951850 ps
CPU time 0.71 seconds
Started Dec 24 12:26:33 PM PST 23
Finished Dec 24 12:26:35 PM PST 23
Peak memory 198704 kb
Host smart-8a863f1f-8674-47cf-92dc-b8b2fbc024d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290203102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.2290203102
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.2334664276
Short name T606
Test name
Test status
Simulation time 1219072300 ps
CPU time 5.03 seconds
Started Dec 24 12:26:25 PM PST 23
Finished Dec 24 12:26:33 PM PST 23
Peak memory 199304 kb
Host smart-88ebeeb4-7564-4c40-876c-387a1efbd3cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334664276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.2334664276
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.2957446228
Short name T597
Test name
Test status
Simulation time 152190717 ps
CPU time 1.11 seconds
Started Dec 24 12:25:20 PM PST 23
Finished Dec 24 12:25:22 PM PST 23
Peak memory 199136 kb
Host smart-22821a08-f60b-45a1-8be6-641db2ee18b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957446228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.2957446228
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.3116884342
Short name T283
Test name
Test status
Simulation time 196870585 ps
CPU time 1.41 seconds
Started Dec 24 12:26:23 PM PST 23
Finished Dec 24 12:26:27 PM PST 23
Peak memory 199284 kb
Host smart-9384bf9d-3870-4bf9-81cd-801577438e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116884342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.3116884342
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.261165129
Short name T535
Test name
Test status
Simulation time 12093742817 ps
CPU time 47.79 seconds
Started Dec 24 12:26:40 PM PST 23
Finished Dec 24 12:27:32 PM PST 23
Peak memory 199500 kb
Host smart-12261d64-05b8-445f-ade0-8deeaa9afb8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261165129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.261165129
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.607880327
Short name T573
Test name
Test status
Simulation time 505293879 ps
CPU time 2.71 seconds
Started Dec 24 12:27:22 PM PST 23
Finished Dec 24 12:27:29 PM PST 23
Peak memory 199204 kb
Host smart-b0ae4e5b-2682-423c-a69b-d60dd3044530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607880327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.607880327
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.2149841456
Short name T451
Test name
Test status
Simulation time 129401435 ps
CPU time 0.96 seconds
Started Dec 24 12:26:27 PM PST 23
Finished Dec 24 12:26:29 PM PST 23
Peak memory 199240 kb
Host smart-432f968c-b24a-4aba-9778-3a6d67a49324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149841456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.2149841456
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.2273526651
Short name T263
Test name
Test status
Simulation time 78036692 ps
CPU time 0.78 seconds
Started Dec 24 12:29:36 PM PST 23
Finished Dec 24 12:29:51 PM PST 23
Peak memory 199096 kb
Host smart-6af86aae-0354-4728-a9ca-f1f0fc849eca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273526651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.2273526651
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.1624626272
Short name T467
Test name
Test status
Simulation time 2164423243 ps
CPU time 8.04 seconds
Started Dec 24 12:27:28 PM PST 23
Finished Dec 24 12:27:39 PM PST 23
Peak memory 217264 kb
Host smart-40ef990d-efc3-408a-9e56-2e7a8040863c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624626272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.1624626272
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.19693609
Short name T320
Test name
Test status
Simulation time 244743435 ps
CPU time 1.15 seconds
Started Dec 24 12:26:23 PM PST 23
Finished Dec 24 12:26:27 PM PST 23
Peak memory 216316 kb
Host smart-bc3f034e-f11a-4865-9c30-af1f27a063a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19693609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.19693609
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.4037700562
Short name T445
Test name
Test status
Simulation time 108028257 ps
CPU time 0.82 seconds
Started Dec 24 12:23:50 PM PST 23
Finished Dec 24 12:23:51 PM PST 23
Peak memory 199404 kb
Host smart-84c76f0c-7796-498e-949f-f87b8c6dbe8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037700562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.4037700562
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.1067331582
Short name T115
Test name
Test status
Simulation time 943450527 ps
CPU time 4.67 seconds
Started Dec 24 12:25:47 PM PST 23
Finished Dec 24 12:25:53 PM PST 23
Peak memory 199312 kb
Host smart-c7c6f526-4121-41c7-81f2-ef3ab0a35c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067331582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.1067331582
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.3194351756
Short name T278
Test name
Test status
Simulation time 172688897 ps
CPU time 1.1 seconds
Started Dec 24 12:26:48 PM PST 23
Finished Dec 24 12:26:51 PM PST 23
Peak memory 198844 kb
Host smart-a83d7820-9ecb-408c-b9ce-f8fdbaae1f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194351756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.3194351756
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.3735500662
Short name T402
Test name
Test status
Simulation time 195496451 ps
CPU time 1.3 seconds
Started Dec 24 12:26:33 PM PST 23
Finished Dec 24 12:26:36 PM PST 23
Peak memory 199072 kb
Host smart-b001815a-cd13-4052-aca1-e0fbf39120e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735500662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.3735500662
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.2377554383
Short name T327
Test name
Test status
Simulation time 10381451994 ps
CPU time 40.97 seconds
Started Dec 24 12:29:50 PM PST 23
Finished Dec 24 12:30:55 PM PST 23
Peak memory 199540 kb
Host smart-7cae266e-4e73-4bac-8c02-d13347be2fdf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377554383 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.2377554383
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.4113611170
Short name T440
Test name
Test status
Simulation time 238906526 ps
CPU time 1.65 seconds
Started Dec 24 12:28:09 PM PST 23
Finished Dec 24 12:28:26 PM PST 23
Peak memory 199256 kb
Host smart-32fc06d9-5627-4214-b8e8-5933c391db09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113611170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.4113611170
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.674162691
Short name T511
Test name
Test status
Simulation time 72860470 ps
CPU time 0.82 seconds
Started Dec 24 12:25:42 PM PST 23
Finished Dec 24 12:25:45 PM PST 23
Peak memory 199588 kb
Host smart-0f56189e-d5a3-4304-8316-6606bf4f2804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674162691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.674162691
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%