Summary for Variable enable
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1600 |
1 |
|
|
T10 |
32 |
|
T12 |
32 |
|
T49 |
32 |
auto[1] |
4932 |
1 |
|
|
T1 |
28 |
|
T5 |
3 |
|
T10 |
5 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1600 |
1 |
|
|
T10 |
32 |
|
T12 |
32 |
|
T49 |
32 |
auto[1] |
4932 |
1 |
|
|
T1 |
28 |
|
T5 |
3 |
|
T10 |
5 |
Summary for Variable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1875 |
1 |
|
|
T1 |
6 |
|
T10 |
10 |
|
T12 |
15 |
auto[1] |
4657 |
1 |
|
|
T1 |
22 |
|
T5 |
3 |
|
T10 |
27 |
Summary for Variable rst_n_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1875 |
1 |
|
|
T1 |
6 |
|
T10 |
10 |
|
T12 |
15 |
auto[1] |
4657 |
1 |
|
|
T1 |
22 |
|
T5 |
3 |
|
T10 |
27 |
Summary for Cross sw_rst_cross
Samples crossed: enable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for sw_rst_cross
Bins
enable | rst_n | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
400 |
1 |
|
|
T10 |
8 |
|
T12 |
8 |
|
T49 |
8 |
auto[0] |
auto[1] |
1200 |
1 |
|
|
T10 |
24 |
|
T12 |
24 |
|
T49 |
24 |
auto[1] |
auto[0] |
1475 |
1 |
|
|
T1 |
6 |
|
T10 |
2 |
|
T12 |
7 |
auto[1] |
auto[1] |
3457 |
1 |
|
|
T1 |
22 |
|
T5 |
3 |
|
T10 |
3 |
Summary for Variable enable
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1460 |
1 |
|
|
T5 |
3 |
|
T10 |
28 |
|
T12 |
28 |
auto[1] |
4837 |
1 |
|
|
T1 |
28 |
|
T10 |
9 |
|
T12 |
26 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1460 |
1 |
|
|
T5 |
3 |
|
T10 |
28 |
|
T12 |
28 |
auto[1] |
4837 |
1 |
|
|
T1 |
28 |
|
T10 |
9 |
|
T12 |
26 |
Summary for Variable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1856 |
1 |
|
|
T1 |
11 |
|
T5 |
2 |
|
T10 |
11 |
auto[1] |
4441 |
1 |
|
|
T1 |
17 |
|
T5 |
1 |
|
T10 |
26 |
Summary for Variable rst_n_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1856 |
1 |
|
|
T1 |
11 |
|
T5 |
2 |
|
T10 |
11 |
auto[1] |
4441 |
1 |
|
|
T1 |
17 |
|
T5 |
1 |
|
T10 |
26 |
Summary for Cross sw_rst_cross
Samples crossed: enable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for sw_rst_cross
Bins
enable | rst_n | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
383 |
1 |
|
|
T5 |
2 |
|
T10 |
7 |
|
T12 |
7 |
auto[0] |
auto[1] |
1077 |
1 |
|
|
T5 |
1 |
|
T10 |
21 |
|
T12 |
21 |
auto[1] |
auto[0] |
1473 |
1 |
|
|
T1 |
11 |
|
T10 |
4 |
|
T12 |
6 |
auto[1] |
auto[1] |
3364 |
1 |
|
|
T1 |
17 |
|
T10 |
5 |
|
T12 |
20 |
Summary for Variable enable
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1275 |
1 |
|
|
T5 |
3 |
|
T10 |
24 |
|
T12 |
24 |
auto[1] |
4897 |
1 |
|
|
T1 |
28 |
|
T10 |
13 |
|
T12 |
30 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1275 |
1 |
|
|
T5 |
3 |
|
T10 |
24 |
|
T12 |
24 |
auto[1] |
4897 |
1 |
|
|
T1 |
28 |
|
T10 |
13 |
|
T12 |
30 |
Summary for Variable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1774 |
1 |
|
|
T1 |
10 |
|
T5 |
2 |
|
T10 |
11 |
auto[1] |
4398 |
1 |
|
|
T1 |
18 |
|
T5 |
1 |
|
T10 |
26 |
Summary for Variable rst_n_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1774 |
1 |
|
|
T1 |
10 |
|
T5 |
2 |
|
T10 |
11 |
auto[1] |
4398 |
1 |
|
|
T1 |
18 |
|
T5 |
1 |
|
T10 |
26 |
Summary for Cross sw_rst_cross
Samples crossed: enable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for sw_rst_cross
Bins
enable | rst_n | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
337 |
1 |
|
|
T5 |
2 |
|
T10 |
6 |
|
T12 |
6 |
auto[0] |
auto[1] |
938 |
1 |
|
|
T5 |
1 |
|
T10 |
18 |
|
T12 |
18 |
auto[1] |
auto[0] |
1437 |
1 |
|
|
T1 |
10 |
|
T10 |
5 |
|
T12 |
11 |
auto[1] |
auto[1] |
3460 |
1 |
|
|
T1 |
18 |
|
T10 |
8 |
|
T12 |
19 |
Summary for Variable enable
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1087 |
1 |
|
|
T5 |
3 |
|
T10 |
20 |
|
T12 |
20 |
auto[1] |
5070 |
1 |
|
|
T1 |
28 |
|
T10 |
17 |
|
T12 |
34 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1087 |
1 |
|
|
T5 |
3 |
|
T10 |
20 |
|
T12 |
20 |
auto[1] |
5070 |
1 |
|
|
T1 |
28 |
|
T10 |
17 |
|
T12 |
34 |
Summary for Variable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1751 |
1 |
|
|
T1 |
6 |
|
T5 |
1 |
|
T10 |
11 |
auto[1] |
4406 |
1 |
|
|
T1 |
22 |
|
T5 |
2 |
|
T10 |
26 |
Summary for Variable rst_n_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1751 |
1 |
|
|
T1 |
6 |
|
T5 |
1 |
|
T10 |
11 |
auto[1] |
4406 |
1 |
|
|
T1 |
22 |
|
T5 |
2 |
|
T10 |
26 |
Summary for Cross sw_rst_cross
Samples crossed: enable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for sw_rst_cross
Bins
enable | rst_n | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
296 |
1 |
|
|
T5 |
1 |
|
T10 |
5 |
|
T12 |
5 |
auto[0] |
auto[1] |
791 |
1 |
|
|
T5 |
2 |
|
T10 |
15 |
|
T12 |
15 |
auto[1] |
auto[0] |
1455 |
1 |
|
|
T1 |
6 |
|
T10 |
6 |
|
T12 |
10 |
auto[1] |
auto[1] |
3615 |
1 |
|
|
T1 |
22 |
|
T10 |
11 |
|
T12 |
24 |
Summary for Variable enable
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
878 |
1 |
|
|
T5 |
3 |
|
T10 |
16 |
|
T12 |
16 |
auto[1] |
5279 |
1 |
|
|
T1 |
28 |
|
T10 |
21 |
|
T12 |
38 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
878 |
1 |
|
|
T5 |
3 |
|
T10 |
16 |
|
T12 |
16 |
auto[1] |
5279 |
1 |
|
|
T1 |
28 |
|
T10 |
21 |
|
T12 |
38 |
Summary for Variable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1763 |
1 |
|
|
T1 |
12 |
|
T5 |
1 |
|
T10 |
9 |
auto[1] |
4394 |
1 |
|
|
T1 |
16 |
|
T5 |
2 |
|
T10 |
28 |
Summary for Variable rst_n_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1763 |
1 |
|
|
T1 |
12 |
|
T5 |
1 |
|
T10 |
9 |
auto[1] |
4394 |
1 |
|
|
T1 |
16 |
|
T5 |
2 |
|
T10 |
28 |
Summary for Cross sw_rst_cross
Samples crossed: enable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for sw_rst_cross
Bins
enable | rst_n | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
238 |
1 |
|
|
T5 |
1 |
|
T10 |
4 |
|
T12 |
4 |
auto[0] |
auto[1] |
640 |
1 |
|
|
T5 |
2 |
|
T10 |
12 |
|
T12 |
12 |
auto[1] |
auto[0] |
1525 |
1 |
|
|
T1 |
12 |
|
T10 |
5 |
|
T12 |
13 |
auto[1] |
auto[1] |
3754 |
1 |
|
|
T1 |
16 |
|
T10 |
16 |
|
T12 |
25 |
Summary for Variable enable
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
666 |
1 |
|
|
T5 |
3 |
|
T10 |
12 |
|
T12 |
12 |
auto[1] |
5491 |
1 |
|
|
T1 |
28 |
|
T10 |
25 |
|
T12 |
42 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
666 |
1 |
|
|
T5 |
3 |
|
T10 |
12 |
|
T12 |
12 |
auto[1] |
5491 |
1 |
|
|
T1 |
28 |
|
T10 |
25 |
|
T12 |
42 |
Summary for Variable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1761 |
1 |
|
|
T1 |
9 |
|
T5 |
1 |
|
T10 |
10 |
auto[1] |
4396 |
1 |
|
|
T1 |
19 |
|
T5 |
2 |
|
T10 |
27 |
Summary for Variable rst_n_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1761 |
1 |
|
|
T1 |
9 |
|
T5 |
1 |
|
T10 |
10 |
auto[1] |
4396 |
1 |
|
|
T1 |
19 |
|
T5 |
2 |
|
T10 |
27 |
Summary for Cross sw_rst_cross
Samples crossed: enable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for sw_rst_cross
Bins
enable | rst_n | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
183 |
1 |
|
|
T5 |
1 |
|
T10 |
3 |
|
T12 |
3 |
auto[0] |
auto[1] |
483 |
1 |
|
|
T5 |
2 |
|
T10 |
9 |
|
T12 |
9 |
auto[1] |
auto[0] |
1578 |
1 |
|
|
T1 |
9 |
|
T10 |
7 |
|
T12 |
13 |
auto[1] |
auto[1] |
3913 |
1 |
|
|
T1 |
19 |
|
T10 |
18 |
|
T12 |
29 |
Summary for Variable enable
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
490 |
1 |
|
|
T10 |
8 |
|
T12 |
8 |
|
T49 |
8 |
auto[1] |
5667 |
1 |
|
|
T1 |
28 |
|
T5 |
3 |
|
T10 |
29 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
490 |
1 |
|
|
T10 |
8 |
|
T12 |
8 |
|
T49 |
8 |
auto[1] |
5667 |
1 |
|
|
T1 |
28 |
|
T5 |
3 |
|
T10 |
29 |
Summary for Variable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1714 |
1 |
|
|
T1 |
8 |
|
T10 |
10 |
|
T12 |
14 |
auto[1] |
4443 |
1 |
|
|
T1 |
20 |
|
T5 |
3 |
|
T10 |
27 |
Summary for Variable rst_n_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1714 |
1 |
|
|
T1 |
8 |
|
T10 |
10 |
|
T12 |
14 |
auto[1] |
4443 |
1 |
|
|
T1 |
20 |
|
T5 |
3 |
|
T10 |
27 |
Summary for Cross sw_rst_cross
Samples crossed: enable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for sw_rst_cross
Bins
enable | rst_n | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
144 |
1 |
|
|
T10 |
2 |
|
T12 |
2 |
|
T49 |
2 |
auto[0] |
auto[1] |
346 |
1 |
|
|
T10 |
6 |
|
T12 |
6 |
|
T49 |
6 |
auto[1] |
auto[0] |
1570 |
1 |
|
|
T1 |
8 |
|
T10 |
8 |
|
T12 |
12 |
auto[1] |
auto[1] |
4097 |
1 |
|
|
T1 |
20 |
|
T5 |
3 |
|
T10 |
21 |
Summary for Variable enable
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
269 |
1 |
|
|
T5 |
3 |
|
T10 |
4 |
|
T12 |
4 |
auto[1] |
5888 |
1 |
|
|
T1 |
28 |
|
T10 |
33 |
|
T12 |
50 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
269 |
1 |
|
|
T5 |
3 |
|
T10 |
4 |
|
T12 |
4 |
auto[1] |
5888 |
1 |
|
|
T1 |
28 |
|
T10 |
33 |
|
T12 |
50 |
Summary for Variable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1779 |
1 |
|
|
T1 |
10 |
|
T5 |
1 |
|
T10 |
9 |
auto[1] |
4378 |
1 |
|
|
T1 |
18 |
|
T5 |
2 |
|
T10 |
28 |
Summary for Variable rst_n_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1779 |
1 |
|
|
T1 |
10 |
|
T5 |
1 |
|
T10 |
9 |
auto[1] |
4378 |
1 |
|
|
T1 |
18 |
|
T5 |
2 |
|
T10 |
28 |
Summary for Cross sw_rst_cross
Samples crossed: enable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for sw_rst_cross
Bins
enable | rst_n | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
84 |
1 |
|
|
T5 |
1 |
|
T10 |
1 |
|
T12 |
1 |
auto[0] |
auto[1] |
185 |
1 |
|
|
T5 |
2 |
|
T10 |
3 |
|
T12 |
3 |
auto[1] |
auto[0] |
1695 |
1 |
|
|
T1 |
10 |
|
T10 |
8 |
|
T12 |
13 |
auto[1] |
auto[1] |
4193 |
1 |
|
|
T1 |
18 |
|
T10 |
25 |
|
T12 |
37 |