Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	589939	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

355634

1

T1

185

T2

999

T3

77

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	502936	1			T1	224		T2	1482		T3	99
values[0x0]	220995	1			T1	104		T2	569		T3	56
values[0x1]	221642	1			T1	122		T2	582		T3	57

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	495218	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

450355

1

T1

216

T2

1256

T3

98

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3612	1			T2	13		T12	1		T22	1
valid_sources[0x01]	3791	1			T2	7		T12	2		T49	4
valid_sources[0x02]	2678	1			T1	2		T2	10		T12	6
valid_sources[0x03]	3145	1			T2	17		T12	5		T14	3
valid_sources[0x04]	3626	1			T2	11		T12	4		T14	1
valid_sources[0x05]	3009	1			T2	5		T12	11		T14	1
valid_sources[0x06]	4276	1			T1	4		T2	8		T12	1
valid_sources[0x07]	2979	1			T1	2		T2	9		T12	5
valid_sources[0x08]	3622	1			T1	3		T2	4		T12	5
valid_sources[0x09]	3930	1			T1	2		T2	6		T12	1
valid_sources[0x0a]	6005	1			T1	2		T2	8		T12	3
valid_sources[0x0b]	3158	1			T1	2		T2	12		T12	1
valid_sources[0x0c]	2994	1			T2	6		T49	19		T24	8
valid_sources[0x0d]	3299	1			T2	10		T12	8		T22	1
valid_sources[0x0e]	3859	1			T2	7		T12	1		T14	2
valid_sources[0x0f]	3796	1			T1	1		T2	10		T12	7
valid_sources[0x10]	3466	1			T1	3		T2	4		T12	5
valid_sources[0x11]	4227	1			T1	1		T2	7		T12	1
valid_sources[0x12]	3890	1			T1	3		T2	7		T12	2
valid_sources[0x13]	3592	1			T1	2		T2	15		T12	1
valid_sources[0x14]	3088	1			T1	3		T2	14		T12	1
valid_sources[0x15]	3887	1			T1	2		T2	5		T7	33
valid_sources[0x16]	3120	1			T1	1		T2	8		T24	6
valid_sources[0x17]	3017	1			T1	5		T2	11		T12	1
valid_sources[0x18]	3064	1			T2	13		T12	3		T14	1
valid_sources[0x19]	3804	1			T1	3		T2	19		T12	9
valid_sources[0x1a]	2966	1			T1	1		T2	8		T12	11
valid_sources[0x1b]	3102	1			T1	4		T2	5		T12	6
valid_sources[0x1c]	3531	1			T1	1		T2	9		T12	3
valid_sources[0x1d]	6481	1			T1	1		T2	9		T12	5
valid_sources[0x1e]	3403	1			T1	1		T2	8		T12	2
valid_sources[0x1f]	3113	1			T1	1		T2	6		T12	3
valid_sources[0x20]	4835	1			T2	13		T12	1		T24	3
valid_sources[0x21]	2831	1			T1	3		T2	8		T12	8
valid_sources[0x22]	3152	1			T1	10		T2	13		T12	5
valid_sources[0x23]	3311	1			T1	5		T2	6		T12	1
valid_sources[0x24]	3192	1			T1	1		T2	6		T12	5
valid_sources[0x25]	3221	1			T1	1		T2	8		T14	1
valid_sources[0x26]	3089	1			T1	2		T2	5		T12	6
valid_sources[0x27]	3720	1			T1	2		T2	7		T12	8
valid_sources[0x28]	3769	1			T1	1		T2	16		T12	4
valid_sources[0x29]	3744	1			T1	7		T2	15		T12	1
valid_sources[0x2a]	2910	1			T1	1		T2	9		T12	4
valid_sources[0x2b]	2933	1			T1	3		T2	10		T12	8
valid_sources[0x2c]	3122	1			T1	1		T2	11		T12	6
valid_sources[0x2d]	3896	1			T1	3		T2	14		T24	9
valid_sources[0x2e]	6503	1			T1	1		T2	9		T12	2
valid_sources[0x2f]	3453	1			T1	2		T2	15		T12	3
valid_sources[0x30]	3369	1			T2	10		T12	6		T24	3
valid_sources[0x31]	3327	1			T2	9		T12	1		T49	2
valid_sources[0x32]	4057	1			T1	1		T2	19		T12	6
valid_sources[0x33]	3495	1			T1	4		T2	6		T14	4
valid_sources[0x34]	4071	1			T1	1		T2	8		T12	3
valid_sources[0x35]	3716	1			T1	1		T2	14		T12	1
valid_sources[0x36]	3347	1			T1	1		T2	6		T12	4
valid_sources[0x37]	2802	1			T1	4		T2	6		T12	2
valid_sources[0x38]	4197	1			T1	2		T2	8		T12	1
valid_sources[0x39]	3041	1			T2	11		T4	1		T12	3
valid_sources[0x3a]	3125	1			T1	1		T2	13		T24	10
valid_sources[0x3b]	3403	1			T1	4		T2	10		T12	5
valid_sources[0x3c]	2899	1			T1	3		T2	13		T12	7
valid_sources[0x3d]	2738	1			T1	1		T2	9		T12	1
valid_sources[0x3e]	3809	1			T1	3		T2	15		T14	1
valid_sources[0x3f]	4183	1			T1	2		T2	13		T12	9
valid_sources[0x40]	2841	1			T1	1		T2	2		T12	1
valid_sources[0x41]	3983	1			T1	3		T2	12		T12	2
valid_sources[0x42]	3562	1			T1	3		T2	11		T12	2
valid_sources[0x43]	3626	1			T2	4		T12	2		T24	16
valid_sources[0x44]	5927	1			T1	1		T2	5		T12	2
valid_sources[0x45]	3670	1			T1	2		T2	17		T12	1
valid_sources[0x46]	3116	1			T1	2		T2	14		T12	7
valid_sources[0x47]	3046	1			T1	1		T2	14		T12	6
valid_sources[0x48]	3253	1			T1	1		T2	4		T12	3
valid_sources[0x49]	3314	1			T1	2		T2	7		T12	6
valid_sources[0x4a]	4757	1			T1	1		T2	14		T14	1
valid_sources[0x4b]	3307	1			T1	3		T2	5		T12	2
valid_sources[0x4c]	2866	1			T1	1		T2	11		T12	8
valid_sources[0x4d]	3396	1			T1	3		T2	11		T6	212
valid_sources[0x4e]	4047	1			T1	1		T2	14		T12	6
valid_sources[0x4f]	3364	1			T2	10		T12	7		T24	8
valid_sources[0x50]	2954	1			T2	11		T12	5		T49	9
valid_sources[0x51]	3427	1			T1	3		T2	12		T12	6
valid_sources[0x52]	2778	1			T2	8		T12	2		T49	4
valid_sources[0x53]	3306	1			T2	6		T12	2		T14	1
valid_sources[0x54]	4739	1			T2	11		T12	1		T49	3
valid_sources[0x55]	4431	1			T1	1		T2	23		T12	4
valid_sources[0x56]	2718	1			T1	4		T2	15		T12	8
valid_sources[0x57]	3581	1			T1	1		T2	11		T12	2
valid_sources[0x58]	3019	1			T1	2		T2	15		T12	18
valid_sources[0x59]	3303	1			T1	4		T2	15		T12	8
valid_sources[0x5a]	4277	1			T1	3		T2	9		T12	1
valid_sources[0x5b]	3095	1			T1	5		T2	12		T12	1
valid_sources[0x5c]	4093	1			T1	2		T2	7		T49	1
valid_sources[0x5d]	6234	1			T1	2		T2	7		T12	1
valid_sources[0x5e]	4001	1			T1	4		T2	7		T12	5
valid_sources[0x5f]	3263	1			T1	1		T2	5		T12	1
valid_sources[0x60]	3243	1			T1	3		T2	20		T12	8
valid_sources[0x61]	3334	1			T1	3		T2	19		T12	5
valid_sources[0x62]	3609	1			T1	4		T2	9		T12	3
valid_sources[0x63]	4503	1			T1	2		T2	10		T12	4
valid_sources[0x64]	3447	1			T1	2		T2	11		T12	9
valid_sources[0x65]	3452	1			T1	1		T2	7		T12	6
valid_sources[0x66]	2827	1			T1	2		T2	8		T12	2
valid_sources[0x67]	4094	1			T1	1		T2	8		T12	7
valid_sources[0x68]	5528	1			T2	8		T10	712		T12	5
valid_sources[0x69]	3007	1			T1	2		T2	16		T12	2
valid_sources[0x6a]	3296	1			T1	2		T2	5		T12	3
valid_sources[0x6b]	3643	1			T1	2		T2	8		T12	8
valid_sources[0x6c]	3888	1			T2	13		T9	13		T12	3
valid_sources[0x6d]	3699	1			T1	2		T2	13		T12	3
valid_sources[0x6e]	3011	1			T1	2		T2	10		T12	2
valid_sources[0x6f]	3382	1			T2	19		T12	7		T49	17
valid_sources[0x70]	7024	1			T1	1		T2	9		T12	7
valid_sources[0x71]	4775	1			T1	2		T2	10		T12	3
valid_sources[0x72]	3101	1			T2	5		T12	7		T49	8
valid_sources[0x73]	3052	1			T1	3		T2	8		T12	1
valid_sources[0x74]	3631	1			T1	3		T2	8		T12	9
valid_sources[0x75]	3273	1			T1	2		T2	17		T12	5
valid_sources[0x76]	3208	1			T2	16		T12	9		T22	8
valid_sources[0x77]	3279	1			T1	1		T2	17		T12	2
valid_sources[0x78]	3400	1			T1	4		T2	16		T12	1
valid_sources[0x79]	4006	1			T1	2		T2	11		T49	4
valid_sources[0x7a]	3353	1			T1	2		T2	13		T12	3
valid_sources[0x7b]	3758	1			T2	17		T12	6		T24	4
valid_sources[0x7c]	3751	1			T1	1		T2	17		T12	4
valid_sources[0x7d]	2481	1			T1	1		T2	12		T12	4
valid_sources[0x7e]	4151	1			T2	10		T14	2		T49	4
valid_sources[0x7f]	6168	1			T2	8		T9	1		T49	2
valid_sources[0x80]	2931	1			T2	12		T12	2		T14	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

236652

1

T1

123

T2

698

T3

48

values[0x0]

all_enables

biggest_size

77381

1

T1

41

T2

192

T3

19

values[0x1]

all_enables

biggest_size

41601

1

T1

21

T2

109

T3

10