SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.55 | 100.00 | 98.21 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_por |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_por_io |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_por_io_div2 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_por_io_div4 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_por_usb |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_lc |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc_shadowed |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_lc_shadowed |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc_aon |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc_io |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_lc_io |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc_io_div2 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_lc_io_div2 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_daon_lc_io_div4 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_d0_lc_io_div4 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_daon_lc_io_div4_shadowed |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_d0_lc_io_div4_shadowed |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc_usb |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_lc_usb |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_sys |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_sys_io_div4 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_spi_device |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_spi_host0 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_spi_host1 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_usb |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | u_d0_usb_aon |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_i2c0 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_i2c1 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_i2c2 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.55 | 100.00 | 98.21 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.55 | 100.00 | 98.21 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 16665 | 16665 | 0 | 0 |
OutputsKnown_A | 361399762 | 205172235 | 0 | 0 |
gen_no_flops.OutputDelay_A | 361399762 | 205172235 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 16665 | 16665 | 0 | 0 |
T1 | 33 | 33 | 0 | 0 |
T2 | 33 | 33 | 0 | 0 |
T3 | 33 | 33 | 0 | 0 |
T4 | 33 | 33 | 0 | 0 |
T5 | 33 | 33 | 0 | 0 |
T6 | 33 | 33 | 0 | 0 |
T7 | 33 | 33 | 0 | 0 |
T8 | 33 | 33 | 0 | 0 |
T9 | 33 | 33 | 0 | 0 |
T10 | 33 | 33 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 361399762 | 205172235 | 0 | 0 |
T1 | 173044 | 153898 | 0 | 0 |
T2 | 526740 | 241125 | 0 | 0 |
T3 | 69475 | 37293 | 0 | 0 |
T4 | 88611 | 29282 | 0 | 0 |
T5 | 185025 | 152977 | 0 | 0 |
T6 | 127655 | 94797 | 0 | 0 |
T7 | 65669 | 46021 | 0 | 0 |
T8 | 94884 | 21159 | 0 | 0 |
T9 | 65067 | 46021 | 0 | 0 |
T10 | 205632 | 185248 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 361399762 | 205172235 | 0 | 0 |
T1 | 173044 | 153898 | 0 | 0 |
T2 | 526740 | 241125 | 0 | 0 |
T3 | 69475 | 37293 | 0 | 0 |
T4 | 88611 | 29282 | 0 | 0 |
T5 | 185025 | 152977 | 0 | 0 |
T6 | 127655 | 94797 | 0 | 0 |
T7 | 65669 | 46021 | 0 | 0 |
T8 | 94884 | 21159 | 0 | 0 |
T9 | 65067 | 46021 | 0 | 0 |
T10 | 205632 | 185248 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 12348402 | 7254667 | 0 | 0 |
gen_no_flops.OutputDelay_A | 12348402 | 7254667 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12348402 | 7254667 | 0 | 0 |
T1 | 5332 | 4682 | 0 | 0 |
T2 | 20532 | 10533 | 0 | 0 |
T3 | 2339 | 1325 | 0 | 0 |
T4 | 2819 | 994 | 0 | 0 |
T5 | 5793 | 4785 | 0 | 0 |
T6 | 4103 | 3117 | 0 | 0 |
T7 | 2053 | 1413 | 0 | 0 |
T8 | 2916 | 871 | 0 | 0 |
T9 | 2059 | 1413 | 0 | 0 |
T10 | 6272 | 5632 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12348402 | 7254667 | 0 | 0 |
T1 | 5332 | 4682 | 0 | 0 |
T2 | 20532 | 10533 | 0 | 0 |
T3 | 2339 | 1325 | 0 | 0 |
T4 | 2819 | 994 | 0 | 0 |
T5 | 5793 | 4785 | 0 | 0 |
T6 | 4103 | 3117 | 0 | 0 |
T7 | 2053 | 1413 | 0 | 0 |
T8 | 2916 | 871 | 0 | 0 |
T9 | 2059 | 1413 | 0 | 0 |
T10 | 6272 | 5632 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 10907855 | 6184924 | 0 | 0 |
gen_no_flops.OutputDelay_A | 10907855 | 6184924 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10907855 | 6184924 | 0 | 0 |
T1 | 5241 | 4663 | 0 | 0 |
T2 | 15819 | 7206 | 0 | 0 |
T3 | 2098 | 1124 | 0 | 0 |
T4 | 2681 | 884 | 0 | 0 |
T5 | 5601 | 4631 | 0 | 0 |
T6 | 3861 | 2865 | 0 | 0 |
T7 | 1988 | 1394 | 0 | 0 |
T8 | 2874 | 634 | 0 | 0 |
T9 | 1969 | 1394 | 0 | 0 |
T10 | 6230 | 5613 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10907855 | 6184924 | 0 | 0 |
T1 | 5241 | 4663 | 0 | 0 |
T2 | 15819 | 7206 | 0 | 0 |
T3 | 2098 | 1124 | 0 | 0 |
T4 | 2681 | 884 | 0 | 0 |
T5 | 5601 | 4631 | 0 | 0 |
T6 | 3861 | 2865 | 0 | 0 |
T7 | 1988 | 1394 | 0 | 0 |
T8 | 2874 | 634 | 0 | 0 |
T9 | 1969 | 1394 | 0 | 0 |
T10 | 6230 | 5613 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 10907855 | 6184924 | 0 | 0 |
gen_no_flops.OutputDelay_A | 10907855 | 6184924 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10907855 | 6184924 | 0 | 0 |
T1 | 5241 | 4663 | 0 | 0 |
T2 | 15819 | 7206 | 0 | 0 |
T3 | 2098 | 1124 | 0 | 0 |
T4 | 2681 | 884 | 0 | 0 |
T5 | 5601 | 4631 | 0 | 0 |
T6 | 3861 | 2865 | 0 | 0 |
T7 | 1988 | 1394 | 0 | 0 |
T8 | 2874 | 634 | 0 | 0 |
T9 | 1969 | 1394 | 0 | 0 |
T10 | 6230 | 5613 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10907855 | 6184924 | 0 | 0 |
T1 | 5241 | 4663 | 0 | 0 |
T2 | 15819 | 7206 | 0 | 0 |
T3 | 2098 | 1124 | 0 | 0 |
T4 | 2681 | 884 | 0 | 0 |
T5 | 5601 | 4631 | 0 | 0 |
T6 | 3861 | 2865 | 0 | 0 |
T7 | 1988 | 1394 | 0 | 0 |
T8 | 2874 | 634 | 0 | 0 |
T9 | 1969 | 1394 | 0 | 0 |
T10 | 6230 | 5613 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 10907855 | 6184924 | 0 | 0 |
gen_no_flops.OutputDelay_A | 10907855 | 6184924 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10907855 | 6184924 | 0 | 0 |
T1 | 5241 | 4663 | 0 | 0 |
T2 | 15819 | 7206 | 0 | 0 |
T3 | 2098 | 1124 | 0 | 0 |
T4 | 2681 | 884 | 0 | 0 |
T5 | 5601 | 4631 | 0 | 0 |
T6 | 3861 | 2865 | 0 | 0 |
T7 | 1988 | 1394 | 0 | 0 |
T8 | 2874 | 634 | 0 | 0 |
T9 | 1969 | 1394 | 0 | 0 |
T10 | 6230 | 5613 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10907855 | 6184924 | 0 | 0 |
T1 | 5241 | 4663 | 0 | 0 |
T2 | 15819 | 7206 | 0 | 0 |
T3 | 2098 | 1124 | 0 | 0 |
T4 | 2681 | 884 | 0 | 0 |
T5 | 5601 | 4631 | 0 | 0 |
T6 | 3861 | 2865 | 0 | 0 |
T7 | 1988 | 1394 | 0 | 0 |
T8 | 2874 | 634 | 0 | 0 |
T9 | 1969 | 1394 | 0 | 0 |
T10 | 6230 | 5613 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 10907855 | 6184924 | 0 | 0 |
gen_no_flops.OutputDelay_A | 10907855 | 6184924 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10907855 | 6184924 | 0 | 0 |
T1 | 5241 | 4663 | 0 | 0 |
T2 | 15819 | 7206 | 0 | 0 |
T3 | 2098 | 1124 | 0 | 0 |
T4 | 2681 | 884 | 0 | 0 |
T5 | 5601 | 4631 | 0 | 0 |
T6 | 3861 | 2865 | 0 | 0 |
T7 | 1988 | 1394 | 0 | 0 |
T8 | 2874 | 634 | 0 | 0 |
T9 | 1969 | 1394 | 0 | 0 |
T10 | 6230 | 5613 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10907855 | 6184924 | 0 | 0 |
T1 | 5241 | 4663 | 0 | 0 |
T2 | 15819 | 7206 | 0 | 0 |
T3 | 2098 | 1124 | 0 | 0 |
T4 | 2681 | 884 | 0 | 0 |
T5 | 5601 | 4631 | 0 | 0 |
T6 | 3861 | 2865 | 0 | 0 |
T7 | 1988 | 1394 | 0 | 0 |
T8 | 2874 | 634 | 0 | 0 |
T9 | 1969 | 1394 | 0 | 0 |
T10 | 6230 | 5613 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 10907855 | 6184924 | 0 | 0 |
gen_no_flops.OutputDelay_A | 10907855 | 6184924 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10907855 | 6184924 | 0 | 0 |
T1 | 5241 | 4663 | 0 | 0 |
T2 | 15819 | 7206 | 0 | 0 |
T3 | 2098 | 1124 | 0 | 0 |
T4 | 2681 | 884 | 0 | 0 |
T5 | 5601 | 4631 | 0 | 0 |
T6 | 3861 | 2865 | 0 | 0 |
T7 | 1988 | 1394 | 0 | 0 |
T8 | 2874 | 634 | 0 | 0 |
T9 | 1969 | 1394 | 0 | 0 |
T10 | 6230 | 5613 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10907855 | 6184924 | 0 | 0 |
T1 | 5241 | 4663 | 0 | 0 |
T2 | 15819 | 7206 | 0 | 0 |
T3 | 2098 | 1124 | 0 | 0 |
T4 | 2681 | 884 | 0 | 0 |
T5 | 5601 | 4631 | 0 | 0 |
T6 | 3861 | 2865 | 0 | 0 |
T7 | 1988 | 1394 | 0 | 0 |
T8 | 2874 | 634 | 0 | 0 |
T9 | 1969 | 1394 | 0 | 0 |
T10 | 6230 | 5613 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 10907855 | 6184924 | 0 | 0 |
gen_no_flops.OutputDelay_A | 10907855 | 6184924 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10907855 | 6184924 | 0 | 0 |
T1 | 5241 | 4663 | 0 | 0 |
T2 | 15819 | 7206 | 0 | 0 |
T3 | 2098 | 1124 | 0 | 0 |
T4 | 2681 | 884 | 0 | 0 |
T5 | 5601 | 4631 | 0 | 0 |
T6 | 3861 | 2865 | 0 | 0 |
T7 | 1988 | 1394 | 0 | 0 |
T8 | 2874 | 634 | 0 | 0 |
T9 | 1969 | 1394 | 0 | 0 |
T10 | 6230 | 5613 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10907855 | 6184924 | 0 | 0 |
T1 | 5241 | 4663 | 0 | 0 |
T2 | 15819 | 7206 | 0 | 0 |
T3 | 2098 | 1124 | 0 | 0 |
T4 | 2681 | 884 | 0 | 0 |
T5 | 5601 | 4631 | 0 | 0 |
T6 | 3861 | 2865 | 0 | 0 |
T7 | 1988 | 1394 | 0 | 0 |
T8 | 2874 | 634 | 0 | 0 |
T9 | 1969 | 1394 | 0 | 0 |
T10 | 6230 | 5613 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 10907855 | 6184924 | 0 | 0 |
gen_no_flops.OutputDelay_A | 10907855 | 6184924 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10907855 | 6184924 | 0 | 0 |
T1 | 5241 | 4663 | 0 | 0 |
T2 | 15819 | 7206 | 0 | 0 |
T3 | 2098 | 1124 | 0 | 0 |
T4 | 2681 | 884 | 0 | 0 |
T5 | 5601 | 4631 | 0 | 0 |
T6 | 3861 | 2865 | 0 | 0 |
T7 | 1988 | 1394 | 0 | 0 |
T8 | 2874 | 634 | 0 | 0 |
T9 | 1969 | 1394 | 0 | 0 |
T10 | 6230 | 5613 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10907855 | 6184924 | 0 | 0 |
T1 | 5241 | 4663 | 0 | 0 |
T2 | 15819 | 7206 | 0 | 0 |
T3 | 2098 | 1124 | 0 | 0 |
T4 | 2681 | 884 | 0 | 0 |
T5 | 5601 | 4631 | 0 | 0 |
T6 | 3861 | 2865 | 0 | 0 |
T7 | 1988 | 1394 | 0 | 0 |
T8 | 2874 | 634 | 0 | 0 |
T9 | 1969 | 1394 | 0 | 0 |
T10 | 6230 | 5613 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 10907855 | 6184924 | 0 | 0 |
gen_no_flops.OutputDelay_A | 10907855 | 6184924 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10907855 | 6184924 | 0 | 0 |
T1 | 5241 | 4663 | 0 | 0 |
T2 | 15819 | 7206 | 0 | 0 |
T3 | 2098 | 1124 | 0 | 0 |
T4 | 2681 | 884 | 0 | 0 |
T5 | 5601 | 4631 | 0 | 0 |
T6 | 3861 | 2865 | 0 | 0 |
T7 | 1988 | 1394 | 0 | 0 |
T8 | 2874 | 634 | 0 | 0 |
T9 | 1969 | 1394 | 0 | 0 |
T10 | 6230 | 5613 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10907855 | 6184924 | 0 | 0 |
T1 | 5241 | 4663 | 0 | 0 |
T2 | 15819 | 7206 | 0 | 0 |
T3 | 2098 | 1124 | 0 | 0 |
T4 | 2681 | 884 | 0 | 0 |
T5 | 5601 | 4631 | 0 | 0 |
T6 | 3861 | 2865 | 0 | 0 |
T7 | 1988 | 1394 | 0 | 0 |
T8 | 2874 | 634 | 0 | 0 |
T9 | 1969 | 1394 | 0 | 0 |
T10 | 6230 | 5613 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 10907855 | 6184924 | 0 | 0 |
gen_no_flops.OutputDelay_A | 10907855 | 6184924 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10907855 | 6184924 | 0 | 0 |
T1 | 5241 | 4663 | 0 | 0 |
T2 | 15819 | 7206 | 0 | 0 |
T3 | 2098 | 1124 | 0 | 0 |
T4 | 2681 | 884 | 0 | 0 |
T5 | 5601 | 4631 | 0 | 0 |
T6 | 3861 | 2865 | 0 | 0 |
T7 | 1988 | 1394 | 0 | 0 |
T8 | 2874 | 634 | 0 | 0 |
T9 | 1969 | 1394 | 0 | 0 |
T10 | 6230 | 5613 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10907855 | 6184924 | 0 | 0 |
T1 | 5241 | 4663 | 0 | 0 |
T2 | 15819 | 7206 | 0 | 0 |
T3 | 2098 | 1124 | 0 | 0 |
T4 | 2681 | 884 | 0 | 0 |
T5 | 5601 | 4631 | 0 | 0 |
T6 | 3861 | 2865 | 0 | 0 |
T7 | 1988 | 1394 | 0 | 0 |
T8 | 2874 | 634 | 0 | 0 |
T9 | 1969 | 1394 | 0 | 0 |
T10 | 6230 | 5613 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 10907855 | 6184924 | 0 | 0 |
gen_no_flops.OutputDelay_A | 10907855 | 6184924 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10907855 | 6184924 | 0 | 0 |
T1 | 5241 | 4663 | 0 | 0 |
T2 | 15819 | 7206 | 0 | 0 |
T3 | 2098 | 1124 | 0 | 0 |
T4 | 2681 | 884 | 0 | 0 |
T5 | 5601 | 4631 | 0 | 0 |
T6 | 3861 | 2865 | 0 | 0 |
T7 | 1988 | 1394 | 0 | 0 |
T8 | 2874 | 634 | 0 | 0 |
T9 | 1969 | 1394 | 0 | 0 |
T10 | 6230 | 5613 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10907855 | 6184924 | 0 | 0 |
T1 | 5241 | 4663 | 0 | 0 |
T2 | 15819 | 7206 | 0 | 0 |
T3 | 2098 | 1124 | 0 | 0 |
T4 | 2681 | 884 | 0 | 0 |
T5 | 5601 | 4631 | 0 | 0 |
T6 | 3861 | 2865 | 0 | 0 |
T7 | 1988 | 1394 | 0 | 0 |
T8 | 2874 | 634 | 0 | 0 |
T9 | 1969 | 1394 | 0 | 0 |
T10 | 6230 | 5613 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 10907855 | 6184924 | 0 | 0 |
gen_no_flops.OutputDelay_A | 10907855 | 6184924 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10907855 | 6184924 | 0 | 0 |
T1 | 5241 | 4663 | 0 | 0 |
T2 | 15819 | 7206 | 0 | 0 |
T3 | 2098 | 1124 | 0 | 0 |
T4 | 2681 | 884 | 0 | 0 |
T5 | 5601 | 4631 | 0 | 0 |
T6 | 3861 | 2865 | 0 | 0 |
T7 | 1988 | 1394 | 0 | 0 |
T8 | 2874 | 634 | 0 | 0 |
T9 | 1969 | 1394 | 0 | 0 |
T10 | 6230 | 5613 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10907855 | 6184924 | 0 | 0 |
T1 | 5241 | 4663 | 0 | 0 |
T2 | 15819 | 7206 | 0 | 0 |
T3 | 2098 | 1124 | 0 | 0 |
T4 | 2681 | 884 | 0 | 0 |
T5 | 5601 | 4631 | 0 | 0 |
T6 | 3861 | 2865 | 0 | 0 |
T7 | 1988 | 1394 | 0 | 0 |
T8 | 2874 | 634 | 0 | 0 |
T9 | 1969 | 1394 | 0 | 0 |
T10 | 6230 | 5613 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 10907855 | 6184924 | 0 | 0 |
gen_no_flops.OutputDelay_A | 10907855 | 6184924 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10907855 | 6184924 | 0 | 0 |
T1 | 5241 | 4663 | 0 | 0 |
T2 | 15819 | 7206 | 0 | 0 |
T3 | 2098 | 1124 | 0 | 0 |
T4 | 2681 | 884 | 0 | 0 |
T5 | 5601 | 4631 | 0 | 0 |
T6 | 3861 | 2865 | 0 | 0 |
T7 | 1988 | 1394 | 0 | 0 |
T8 | 2874 | 634 | 0 | 0 |
T9 | 1969 | 1394 | 0 | 0 |
T10 | 6230 | 5613 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10907855 | 6184924 | 0 | 0 |
T1 | 5241 | 4663 | 0 | 0 |
T2 | 15819 | 7206 | 0 | 0 |
T3 | 2098 | 1124 | 0 | 0 |
T4 | 2681 | 884 | 0 | 0 |
T5 | 5601 | 4631 | 0 | 0 |
T6 | 3861 | 2865 | 0 | 0 |
T7 | 1988 | 1394 | 0 | 0 |
T8 | 2874 | 634 | 0 | 0 |
T9 | 1969 | 1394 | 0 | 0 |
T10 | 6230 | 5613 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 10907855 | 6184924 | 0 | 0 |
gen_no_flops.OutputDelay_A | 10907855 | 6184924 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10907855 | 6184924 | 0 | 0 |
T1 | 5241 | 4663 | 0 | 0 |
T2 | 15819 | 7206 | 0 | 0 |
T3 | 2098 | 1124 | 0 | 0 |
T4 | 2681 | 884 | 0 | 0 |
T5 | 5601 | 4631 | 0 | 0 |
T6 | 3861 | 2865 | 0 | 0 |
T7 | 1988 | 1394 | 0 | 0 |
T8 | 2874 | 634 | 0 | 0 |
T9 | 1969 | 1394 | 0 | 0 |
T10 | 6230 | 5613 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10907855 | 6184924 | 0 | 0 |
T1 | 5241 | 4663 | 0 | 0 |
T2 | 15819 | 7206 | 0 | 0 |
T3 | 2098 | 1124 | 0 | 0 |
T4 | 2681 | 884 | 0 | 0 |
T5 | 5601 | 4631 | 0 | 0 |
T6 | 3861 | 2865 | 0 | 0 |
T7 | 1988 | 1394 | 0 | 0 |
T8 | 2874 | 634 | 0 | 0 |
T9 | 1969 | 1394 | 0 | 0 |
T10 | 6230 | 5613 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 10907855 | 6184924 | 0 | 0 |
gen_no_flops.OutputDelay_A | 10907855 | 6184924 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10907855 | 6184924 | 0 | 0 |
T1 | 5241 | 4663 | 0 | 0 |
T2 | 15819 | 7206 | 0 | 0 |
T3 | 2098 | 1124 | 0 | 0 |
T4 | 2681 | 884 | 0 | 0 |
T5 | 5601 | 4631 | 0 | 0 |
T6 | 3861 | 2865 | 0 | 0 |
T7 | 1988 | 1394 | 0 | 0 |
T8 | 2874 | 634 | 0 | 0 |
T9 | 1969 | 1394 | 0 | 0 |
T10 | 6230 | 5613 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10907855 | 6184924 | 0 | 0 |
T1 | 5241 | 4663 | 0 | 0 |
T2 | 15819 | 7206 | 0 | 0 |
T3 | 2098 | 1124 | 0 | 0 |
T4 | 2681 | 884 | 0 | 0 |
T5 | 5601 | 4631 | 0 | 0 |
T6 | 3861 | 2865 | 0 | 0 |
T7 | 1988 | 1394 | 0 | 0 |
T8 | 2874 | 634 | 0 | 0 |
T9 | 1969 | 1394 | 0 | 0 |
T10 | 6230 | 5613 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 10907855 | 6184924 | 0 | 0 |
gen_no_flops.OutputDelay_A | 10907855 | 6184924 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10907855 | 6184924 | 0 | 0 |
T1 | 5241 | 4663 | 0 | 0 |
T2 | 15819 | 7206 | 0 | 0 |
T3 | 2098 | 1124 | 0 | 0 |
T4 | 2681 | 884 | 0 | 0 |
T5 | 5601 | 4631 | 0 | 0 |
T6 | 3861 | 2865 | 0 | 0 |
T7 | 1988 | 1394 | 0 | 0 |
T8 | 2874 | 634 | 0 | 0 |
T9 | 1969 | 1394 | 0 | 0 |
T10 | 6230 | 5613 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10907855 | 6184924 | 0 | 0 |
T1 | 5241 | 4663 | 0 | 0 |
T2 | 15819 | 7206 | 0 | 0 |
T3 | 2098 | 1124 | 0 | 0 |
T4 | 2681 | 884 | 0 | 0 |
T5 | 5601 | 4631 | 0 | 0 |
T6 | 3861 | 2865 | 0 | 0 |
T7 | 1988 | 1394 | 0 | 0 |
T8 | 2874 | 634 | 0 | 0 |
T9 | 1969 | 1394 | 0 | 0 |
T10 | 6230 | 5613 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 10907855 | 6184924 | 0 | 0 |
gen_no_flops.OutputDelay_A | 10907855 | 6184924 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10907855 | 6184924 | 0 | 0 |
T1 | 5241 | 4663 | 0 | 0 |
T2 | 15819 | 7206 | 0 | 0 |
T3 | 2098 | 1124 | 0 | 0 |
T4 | 2681 | 884 | 0 | 0 |
T5 | 5601 | 4631 | 0 | 0 |
T6 | 3861 | 2865 | 0 | 0 |
T7 | 1988 | 1394 | 0 | 0 |
T8 | 2874 | 634 | 0 | 0 |
T9 | 1969 | 1394 | 0 | 0 |
T10 | 6230 | 5613 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10907855 | 6184924 | 0 | 0 |
T1 | 5241 | 4663 | 0 | 0 |
T2 | 15819 | 7206 | 0 | 0 |
T3 | 2098 | 1124 | 0 | 0 |
T4 | 2681 | 884 | 0 | 0 |
T5 | 5601 | 4631 | 0 | 0 |
T6 | 3861 | 2865 | 0 | 0 |
T7 | 1988 | 1394 | 0 | 0 |
T8 | 2874 | 634 | 0 | 0 |
T9 | 1969 | 1394 | 0 | 0 |
T10 | 6230 | 5613 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 10907855 | 6184924 | 0 | 0 |
gen_no_flops.OutputDelay_A | 10907855 | 6184924 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10907855 | 6184924 | 0 | 0 |
T1 | 5241 | 4663 | 0 | 0 |
T2 | 15819 | 7206 | 0 | 0 |
T3 | 2098 | 1124 | 0 | 0 |
T4 | 2681 | 884 | 0 | 0 |
T5 | 5601 | 4631 | 0 | 0 |
T6 | 3861 | 2865 | 0 | 0 |
T7 | 1988 | 1394 | 0 | 0 |
T8 | 2874 | 634 | 0 | 0 |
T9 | 1969 | 1394 | 0 | 0 |
T10 | 6230 | 5613 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10907855 | 6184924 | 0 | 0 |
T1 | 5241 | 4663 | 0 | 0 |
T2 | 15819 | 7206 | 0 | 0 |
T3 | 2098 | 1124 | 0 | 0 |
T4 | 2681 | 884 | 0 | 0 |
T5 | 5601 | 4631 | 0 | 0 |
T6 | 3861 | 2865 | 0 | 0 |
T7 | 1988 | 1394 | 0 | 0 |
T8 | 2874 | 634 | 0 | 0 |
T9 | 1969 | 1394 | 0 | 0 |
T10 | 6230 | 5613 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 10907855 | 6184924 | 0 | 0 |
gen_no_flops.OutputDelay_A | 10907855 | 6184924 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10907855 | 6184924 | 0 | 0 |
T1 | 5241 | 4663 | 0 | 0 |
T2 | 15819 | 7206 | 0 | 0 |
T3 | 2098 | 1124 | 0 | 0 |
T4 | 2681 | 884 | 0 | 0 |
T5 | 5601 | 4631 | 0 | 0 |
T6 | 3861 | 2865 | 0 | 0 |
T7 | 1988 | 1394 | 0 | 0 |
T8 | 2874 | 634 | 0 | 0 |
T9 | 1969 | 1394 | 0 | 0 |
T10 | 6230 | 5613 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10907855 | 6184924 | 0 | 0 |
T1 | 5241 | 4663 | 0 | 0 |
T2 | 15819 | 7206 | 0 | 0 |
T3 | 2098 | 1124 | 0 | 0 |
T4 | 2681 | 884 | 0 | 0 |
T5 | 5601 | 4631 | 0 | 0 |
T6 | 3861 | 2865 | 0 | 0 |
T7 | 1988 | 1394 | 0 | 0 |
T8 | 2874 | 634 | 0 | 0 |
T9 | 1969 | 1394 | 0 | 0 |
T10 | 6230 | 5613 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 10907855 | 6184924 | 0 | 0 |
gen_no_flops.OutputDelay_A | 10907855 | 6184924 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10907855 | 6184924 | 0 | 0 |
T1 | 5241 | 4663 | 0 | 0 |
T2 | 15819 | 7206 | 0 | 0 |
T3 | 2098 | 1124 | 0 | 0 |
T4 | 2681 | 884 | 0 | 0 |
T5 | 5601 | 4631 | 0 | 0 |
T6 | 3861 | 2865 | 0 | 0 |
T7 | 1988 | 1394 | 0 | 0 |
T8 | 2874 | 634 | 0 | 0 |
T9 | 1969 | 1394 | 0 | 0 |
T10 | 6230 | 5613 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10907855 | 6184924 | 0 | 0 |
T1 | 5241 | 4663 | 0 | 0 |
T2 | 15819 | 7206 | 0 | 0 |
T3 | 2098 | 1124 | 0 | 0 |
T4 | 2681 | 884 | 0 | 0 |
T5 | 5601 | 4631 | 0 | 0 |
T6 | 3861 | 2865 | 0 | 0 |
T7 | 1988 | 1394 | 0 | 0 |
T8 | 2874 | 634 | 0 | 0 |
T9 | 1969 | 1394 | 0 | 0 |
T10 | 6230 | 5613 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 10907855 | 6184924 | 0 | 0 |
gen_no_flops.OutputDelay_A | 10907855 | 6184924 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10907855 | 6184924 | 0 | 0 |
T1 | 5241 | 4663 | 0 | 0 |
T2 | 15819 | 7206 | 0 | 0 |
T3 | 2098 | 1124 | 0 | 0 |
T4 | 2681 | 884 | 0 | 0 |
T5 | 5601 | 4631 | 0 | 0 |
T6 | 3861 | 2865 | 0 | 0 |
T7 | 1988 | 1394 | 0 | 0 |
T8 | 2874 | 634 | 0 | 0 |
T9 | 1969 | 1394 | 0 | 0 |
T10 | 6230 | 5613 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10907855 | 6184924 | 0 | 0 |
T1 | 5241 | 4663 | 0 | 0 |
T2 | 15819 | 7206 | 0 | 0 |
T3 | 2098 | 1124 | 0 | 0 |
T4 | 2681 | 884 | 0 | 0 |
T5 | 5601 | 4631 | 0 | 0 |
T6 | 3861 | 2865 | 0 | 0 |
T7 | 1988 | 1394 | 0 | 0 |
T8 | 2874 | 634 | 0 | 0 |
T9 | 1969 | 1394 | 0 | 0 |
T10 | 6230 | 5613 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 10907855 | 6184924 | 0 | 0 |
gen_no_flops.OutputDelay_A | 10907855 | 6184924 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10907855 | 6184924 | 0 | 0 |
T1 | 5241 | 4663 | 0 | 0 |
T2 | 15819 | 7206 | 0 | 0 |
T3 | 2098 | 1124 | 0 | 0 |
T4 | 2681 | 884 | 0 | 0 |
T5 | 5601 | 4631 | 0 | 0 |
T6 | 3861 | 2865 | 0 | 0 |
T7 | 1988 | 1394 | 0 | 0 |
T8 | 2874 | 634 | 0 | 0 |
T9 | 1969 | 1394 | 0 | 0 |
T10 | 6230 | 5613 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10907855 | 6184924 | 0 | 0 |
T1 | 5241 | 4663 | 0 | 0 |
T2 | 15819 | 7206 | 0 | 0 |
T3 | 2098 | 1124 | 0 | 0 |
T4 | 2681 | 884 | 0 | 0 |
T5 | 5601 | 4631 | 0 | 0 |
T6 | 3861 | 2865 | 0 | 0 |
T7 | 1988 | 1394 | 0 | 0 |
T8 | 2874 | 634 | 0 | 0 |
T9 | 1969 | 1394 | 0 | 0 |
T10 | 6230 | 5613 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 10907855 | 6184924 | 0 | 0 |
gen_no_flops.OutputDelay_A | 10907855 | 6184924 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10907855 | 6184924 | 0 | 0 |
T1 | 5241 | 4663 | 0 | 0 |
T2 | 15819 | 7206 | 0 | 0 |
T3 | 2098 | 1124 | 0 | 0 |
T4 | 2681 | 884 | 0 | 0 |
T5 | 5601 | 4631 | 0 | 0 |
T6 | 3861 | 2865 | 0 | 0 |
T7 | 1988 | 1394 | 0 | 0 |
T8 | 2874 | 634 | 0 | 0 |
T9 | 1969 | 1394 | 0 | 0 |
T10 | 6230 | 5613 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10907855 | 6184924 | 0 | 0 |
T1 | 5241 | 4663 | 0 | 0 |
T2 | 15819 | 7206 | 0 | 0 |
T3 | 2098 | 1124 | 0 | 0 |
T4 | 2681 | 884 | 0 | 0 |
T5 | 5601 | 4631 | 0 | 0 |
T6 | 3861 | 2865 | 0 | 0 |
T7 | 1988 | 1394 | 0 | 0 |
T8 | 2874 | 634 | 0 | 0 |
T9 | 1969 | 1394 | 0 | 0 |
T10 | 6230 | 5613 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 10907855 | 6184924 | 0 | 0 |
gen_no_flops.OutputDelay_A | 10907855 | 6184924 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10907855 | 6184924 | 0 | 0 |
T1 | 5241 | 4663 | 0 | 0 |
T2 | 15819 | 7206 | 0 | 0 |
T3 | 2098 | 1124 | 0 | 0 |
T4 | 2681 | 884 | 0 | 0 |
T5 | 5601 | 4631 | 0 | 0 |
T6 | 3861 | 2865 | 0 | 0 |
T7 | 1988 | 1394 | 0 | 0 |
T8 | 2874 | 634 | 0 | 0 |
T9 | 1969 | 1394 | 0 | 0 |
T10 | 6230 | 5613 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10907855 | 6184924 | 0 | 0 |
T1 | 5241 | 4663 | 0 | 0 |
T2 | 15819 | 7206 | 0 | 0 |
T3 | 2098 | 1124 | 0 | 0 |
T4 | 2681 | 884 | 0 | 0 |
T5 | 5601 | 4631 | 0 | 0 |
T6 | 3861 | 2865 | 0 | 0 |
T7 | 1988 | 1394 | 0 | 0 |
T8 | 2874 | 634 | 0 | 0 |
T9 | 1969 | 1394 | 0 | 0 |
T10 | 6230 | 5613 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 10907855 | 6184924 | 0 | 0 |
gen_no_flops.OutputDelay_A | 10907855 | 6184924 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10907855 | 6184924 | 0 | 0 |
T1 | 5241 | 4663 | 0 | 0 |
T2 | 15819 | 7206 | 0 | 0 |
T3 | 2098 | 1124 | 0 | 0 |
T4 | 2681 | 884 | 0 | 0 |
T5 | 5601 | 4631 | 0 | 0 |
T6 | 3861 | 2865 | 0 | 0 |
T7 | 1988 | 1394 | 0 | 0 |
T8 | 2874 | 634 | 0 | 0 |
T9 | 1969 | 1394 | 0 | 0 |
T10 | 6230 | 5613 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10907855 | 6184924 | 0 | 0 |
T1 | 5241 | 4663 | 0 | 0 |
T2 | 15819 | 7206 | 0 | 0 |
T3 | 2098 | 1124 | 0 | 0 |
T4 | 2681 | 884 | 0 | 0 |
T5 | 5601 | 4631 | 0 | 0 |
T6 | 3861 | 2865 | 0 | 0 |
T7 | 1988 | 1394 | 0 | 0 |
T8 | 2874 | 634 | 0 | 0 |
T9 | 1969 | 1394 | 0 | 0 |
T10 | 6230 | 5613 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 10907855 | 6184924 | 0 | 0 |
gen_no_flops.OutputDelay_A | 10907855 | 6184924 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10907855 | 6184924 | 0 | 0 |
T1 | 5241 | 4663 | 0 | 0 |
T2 | 15819 | 7206 | 0 | 0 |
T3 | 2098 | 1124 | 0 | 0 |
T4 | 2681 | 884 | 0 | 0 |
T5 | 5601 | 4631 | 0 | 0 |
T6 | 3861 | 2865 | 0 | 0 |
T7 | 1988 | 1394 | 0 | 0 |
T8 | 2874 | 634 | 0 | 0 |
T9 | 1969 | 1394 | 0 | 0 |
T10 | 6230 | 5613 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10907855 | 6184924 | 0 | 0 |
T1 | 5241 | 4663 | 0 | 0 |
T2 | 15819 | 7206 | 0 | 0 |
T3 | 2098 | 1124 | 0 | 0 |
T4 | 2681 | 884 | 0 | 0 |
T5 | 5601 | 4631 | 0 | 0 |
T6 | 3861 | 2865 | 0 | 0 |
T7 | 1988 | 1394 | 0 | 0 |
T8 | 2874 | 634 | 0 | 0 |
T9 | 1969 | 1394 | 0 | 0 |
T10 | 6230 | 5613 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 10907855 | 6184924 | 0 | 0 |
gen_no_flops.OutputDelay_A | 10907855 | 6184924 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10907855 | 6184924 | 0 | 0 |
T1 | 5241 | 4663 | 0 | 0 |
T2 | 15819 | 7206 | 0 | 0 |
T3 | 2098 | 1124 | 0 | 0 |
T4 | 2681 | 884 | 0 | 0 |
T5 | 5601 | 4631 | 0 | 0 |
T6 | 3861 | 2865 | 0 | 0 |
T7 | 1988 | 1394 | 0 | 0 |
T8 | 2874 | 634 | 0 | 0 |
T9 | 1969 | 1394 | 0 | 0 |
T10 | 6230 | 5613 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10907855 | 6184924 | 0 | 0 |
T1 | 5241 | 4663 | 0 | 0 |
T2 | 15819 | 7206 | 0 | 0 |
T3 | 2098 | 1124 | 0 | 0 |
T4 | 2681 | 884 | 0 | 0 |
T5 | 5601 | 4631 | 0 | 0 |
T6 | 3861 | 2865 | 0 | 0 |
T7 | 1988 | 1394 | 0 | 0 |
T8 | 2874 | 634 | 0 | 0 |
T9 | 1969 | 1394 | 0 | 0 |
T10 | 6230 | 5613 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 10907855 | 6184924 | 0 | 0 |
gen_no_flops.OutputDelay_A | 10907855 | 6184924 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10907855 | 6184924 | 0 | 0 |
T1 | 5241 | 4663 | 0 | 0 |
T2 | 15819 | 7206 | 0 | 0 |
T3 | 2098 | 1124 | 0 | 0 |
T4 | 2681 | 884 | 0 | 0 |
T5 | 5601 | 4631 | 0 | 0 |
T6 | 3861 | 2865 | 0 | 0 |
T7 | 1988 | 1394 | 0 | 0 |
T8 | 2874 | 634 | 0 | 0 |
T9 | 1969 | 1394 | 0 | 0 |
T10 | 6230 | 5613 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10907855 | 6184924 | 0 | 0 |
T1 | 5241 | 4663 | 0 | 0 |
T2 | 15819 | 7206 | 0 | 0 |
T3 | 2098 | 1124 | 0 | 0 |
T4 | 2681 | 884 | 0 | 0 |
T5 | 5601 | 4631 | 0 | 0 |
T6 | 3861 | 2865 | 0 | 0 |
T7 | 1988 | 1394 | 0 | 0 |
T8 | 2874 | 634 | 0 | 0 |
T9 | 1969 | 1394 | 0 | 0 |
T10 | 6230 | 5613 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 10907855 | 6184924 | 0 | 0 |
gen_no_flops.OutputDelay_A | 10907855 | 6184924 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10907855 | 6184924 | 0 | 0 |
T1 | 5241 | 4663 | 0 | 0 |
T2 | 15819 | 7206 | 0 | 0 |
T3 | 2098 | 1124 | 0 | 0 |
T4 | 2681 | 884 | 0 | 0 |
T5 | 5601 | 4631 | 0 | 0 |
T6 | 3861 | 2865 | 0 | 0 |
T7 | 1988 | 1394 | 0 | 0 |
T8 | 2874 | 634 | 0 | 0 |
T9 | 1969 | 1394 | 0 | 0 |
T10 | 6230 | 5613 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10907855 | 6184924 | 0 | 0 |
T1 | 5241 | 4663 | 0 | 0 |
T2 | 15819 | 7206 | 0 | 0 |
T3 | 2098 | 1124 | 0 | 0 |
T4 | 2681 | 884 | 0 | 0 |
T5 | 5601 | 4631 | 0 | 0 |
T6 | 3861 | 2865 | 0 | 0 |
T7 | 1988 | 1394 | 0 | 0 |
T8 | 2874 | 634 | 0 | 0 |
T9 | 1969 | 1394 | 0 | 0 |
T10 | 6230 | 5613 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 10907855 | 6184924 | 0 | 0 |
gen_no_flops.OutputDelay_A | 10907855 | 6184924 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10907855 | 6184924 | 0 | 0 |
T1 | 5241 | 4663 | 0 | 0 |
T2 | 15819 | 7206 | 0 | 0 |
T3 | 2098 | 1124 | 0 | 0 |
T4 | 2681 | 884 | 0 | 0 |
T5 | 5601 | 4631 | 0 | 0 |
T6 | 3861 | 2865 | 0 | 0 |
T7 | 1988 | 1394 | 0 | 0 |
T8 | 2874 | 634 | 0 | 0 |
T9 | 1969 | 1394 | 0 | 0 |
T10 | 6230 | 5613 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10907855 | 6184924 | 0 | 0 |
T1 | 5241 | 4663 | 0 | 0 |
T2 | 15819 | 7206 | 0 | 0 |
T3 | 2098 | 1124 | 0 | 0 |
T4 | 2681 | 884 | 0 | 0 |
T5 | 5601 | 4631 | 0 | 0 |
T6 | 3861 | 2865 | 0 | 0 |
T7 | 1988 | 1394 | 0 | 0 |
T8 | 2874 | 634 | 0 | 0 |
T9 | 1969 | 1394 | 0 | 0 |
T10 | 6230 | 5613 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 10907855 | 6184924 | 0 | 0 |
gen_no_flops.OutputDelay_A | 10907855 | 6184924 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10907855 | 6184924 | 0 | 0 |
T1 | 5241 | 4663 | 0 | 0 |
T2 | 15819 | 7206 | 0 | 0 |
T3 | 2098 | 1124 | 0 | 0 |
T4 | 2681 | 884 | 0 | 0 |
T5 | 5601 | 4631 | 0 | 0 |
T6 | 3861 | 2865 | 0 | 0 |
T7 | 1988 | 1394 | 0 | 0 |
T8 | 2874 | 634 | 0 | 0 |
T9 | 1969 | 1394 | 0 | 0 |
T10 | 6230 | 5613 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10907855 | 6184924 | 0 | 0 |
T1 | 5241 | 4663 | 0 | 0 |
T2 | 15819 | 7206 | 0 | 0 |
T3 | 2098 | 1124 | 0 | 0 |
T4 | 2681 | 884 | 0 | 0 |
T5 | 5601 | 4631 | 0 | 0 |
T6 | 3861 | 2865 | 0 | 0 |
T7 | 1988 | 1394 | 0 | 0 |
T8 | 2874 | 634 | 0 | 0 |
T9 | 1969 | 1394 | 0 | 0 |
T10 | 6230 | 5613 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 10907855 | 6184924 | 0 | 0 |
gen_no_flops.OutputDelay_A | 10907855 | 6184924 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10907855 | 6184924 | 0 | 0 |
T1 | 5241 | 4663 | 0 | 0 |
T2 | 15819 | 7206 | 0 | 0 |
T3 | 2098 | 1124 | 0 | 0 |
T4 | 2681 | 884 | 0 | 0 |
T5 | 5601 | 4631 | 0 | 0 |
T6 | 3861 | 2865 | 0 | 0 |
T7 | 1988 | 1394 | 0 | 0 |
T8 | 2874 | 634 | 0 | 0 |
T9 | 1969 | 1394 | 0 | 0 |
T10 | 6230 | 5613 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10907855 | 6184924 | 0 | 0 |
T1 | 5241 | 4663 | 0 | 0 |
T2 | 15819 | 7206 | 0 | 0 |
T3 | 2098 | 1124 | 0 | 0 |
T4 | 2681 | 884 | 0 | 0 |
T5 | 5601 | 4631 | 0 | 0 |
T6 | 3861 | 2865 | 0 | 0 |
T7 | 1988 | 1394 | 0 | 0 |
T8 | 2874 | 634 | 0 | 0 |
T9 | 1969 | 1394 | 0 | 0 |
T10 | 6230 | 5613 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 10907855 | 6184924 | 0 | 0 |
gen_no_flops.OutputDelay_A | 10907855 | 6184924 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10907855 | 6184924 | 0 | 0 |
T1 | 5241 | 4663 | 0 | 0 |
T2 | 15819 | 7206 | 0 | 0 |
T3 | 2098 | 1124 | 0 | 0 |
T4 | 2681 | 884 | 0 | 0 |
T5 | 5601 | 4631 | 0 | 0 |
T6 | 3861 | 2865 | 0 | 0 |
T7 | 1988 | 1394 | 0 | 0 |
T8 | 2874 | 634 | 0 | 0 |
T9 | 1969 | 1394 | 0 | 0 |
T10 | 6230 | 5613 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10907855 | 6184924 | 0 | 0 |
T1 | 5241 | 4663 | 0 | 0 |
T2 | 15819 | 7206 | 0 | 0 |
T3 | 2098 | 1124 | 0 | 0 |
T4 | 2681 | 884 | 0 | 0 |
T5 | 5601 | 4631 | 0 | 0 |
T6 | 3861 | 2865 | 0 | 0 |
T7 | 1988 | 1394 | 0 | 0 |
T8 | 2874 | 634 | 0 | 0 |
T9 | 1969 | 1394 | 0 | 0 |
T10 | 6230 | 5613 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |