SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.gen_alert_tx[0].u_prim_alert_sender | 100.00 | 100.00 | |||||
tb.dut.gen_alert_tx[1].u_prim_alert_sender | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.55 | 100.00 | 98.21 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.55 | 100.00 | 98.21 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Total | Covered | Percent | |
---|---|---|---|
Totals | 10 | 10 | 100.00 |
Total Bits | 20 | 20 | 100.00 |
Total Bits 0->1 | 10 | 10 | 100.00 |
Total Bits 1->0 | 10 | 10 | 100.00 |
Ports | 10 | 10 | 100.00 |
Port Bits | 20 | 20 | 100.00 |
Port Bits 0->1 | 10 | 10 | 100.00 |
Port Bits 1->0 | 10 | 10 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T3,T4 | Yes | T1,T2,T3 | INPUT |
alert_test_i | Yes | Yes | T7,T9,T53 | Yes | T7,T9,T53 | INPUT |
alert_req_i | Yes | Yes | T21,T80,T54 | Yes | T21,T80,T54 | INPUT |
alert_ack_o | Yes | Yes | T21,T80,T61 | Yes | T21,T80,T61 | OUTPUT |
alert_state_o | Yes | Yes | T21,T80,T54 | Yes | T21,T80,T54 | OUTPUT |
alert_rx_i.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_rx_i.ack_p | Yes | Yes | T7,T9,T21 | Yes | T7,T9,T21 | INPUT |
alert_rx_i.ping_n | Unreachable | Unreachable | Unreachable | INPUT | ||
alert_rx_i.ping_p | Unreachable | Unreachable | Unreachable | INPUT | ||
alert_tx_o.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_tx_o.alert_p | Yes | Yes | T7,T9,T21 | Yes | T7,T9,T21 | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 10 | 10 | 100.00 |
Total Bits | 20 | 20 | 100.00 |
Total Bits 0->1 | 10 | 10 | 100.00 |
Total Bits 1->0 | 10 | 10 | 100.00 |
Ports | 10 | 10 | 100.00 |
Port Bits | 20 | 20 | 100.00 |
Port Bits 0->1 | 10 | 10 | 100.00 |
Port Bits 1->0 | 10 | 10 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T3,T4 | Yes | T1,T2,T3 | INPUT |
alert_test_i | Yes | Yes | T7,T9,T53 | Yes | T7,T9,T53 | INPUT |
alert_req_i | Yes | Yes | T61,T83,T84 | Yes | T61,T83,T84 | INPUT |
alert_ack_o | Yes | Yes | T61,T83,T84 | Yes | T61,T83,T84 | OUTPUT |
alert_state_o | Yes | Yes | T61,T83,T84 | Yes | T61,T83,T84 | OUTPUT |
alert_rx_i.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_rx_i.ack_p | Yes | Yes | T7,T9,T53 | Yes | T7,T9,T53 | INPUT |
alert_rx_i.ping_n | Unreachable | Unreachable | Unreachable | INPUT | ||
alert_rx_i.ping_p | Unreachable | Unreachable | Unreachable | INPUT | ||
alert_tx_o.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_tx_o.alert_p | Yes | Yes | T7,T9,T53 | Yes | T7,T9,T53 | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 10 | 10 | 100.00 |
Total Bits | 20 | 20 | 100.00 |
Total Bits 0->1 | 10 | 10 | 100.00 |
Total Bits 1->0 | 10 | 10 | 100.00 |
Ports | 10 | 10 | 100.00 |
Port Bits | 20 | 20 | 100.00 |
Port Bits 0->1 | 10 | 10 | 100.00 |
Port Bits 1->0 | 10 | 10 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T2,T3,T4 | Yes | T1,T2,T3 | INPUT |
alert_test_i | Yes | Yes | T7,T9,T53 | Yes | T7,T9,T53 | INPUT |
alert_req_i | Yes | Yes | T21,T80,T54 | Yes | T21,T80,T54 | INPUT |
alert_ack_o | Yes | Yes | T21,T80,T95 | Yes | T21,T80,T95 | OUTPUT |
alert_state_o | Yes | Yes | T21,T80,T54 | Yes | T21,T80,T54 | OUTPUT |
alert_rx_i.ack_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
alert_rx_i.ack_p | Yes | Yes | T7,T9,T21 | Yes | T7,T9,T21 | INPUT |
alert_rx_i.ping_n | Unreachable | Unreachable | Unreachable | INPUT | ||
alert_rx_i.ping_p | Unreachable | Unreachable | Unreachable | INPUT | ||
alert_tx_o.alert_n | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
alert_tx_o.alert_p | Yes | Yes | T7,T9,T21 | Yes | T7,T9,T21 | OUTPUT |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |