Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T10,T12
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T10,T12
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T10,T12
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T10,T12
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T10,T12
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T10,T12
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T10,T12
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T10,T12
1	0	Covered	T2,T3,T4

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	12348402	13457	0	0
gen_assertions[0].RstEnOn_A	12348402	1140	0	0
gen_assertions[0].RstNOff_A	12348402	13457	0	0
gen_assertions[0].RstNOn_A	12348402	1140	0	0
gen_assertions[1].RstEnOff_A	49394234	12251	0	0
gen_assertions[1].RstEnOn_A	49394234	1131	0	0
gen_assertions[1].RstNOff_A	49394234	12251	0	0
gen_assertions[1].RstNOn_A	49394234	1131	0	0
gen_assertions[2].RstEnOff_A	24697834	12300	0	0
gen_assertions[2].RstEnOn_A	24697834	1110	0	0
gen_assertions[2].RstNOff_A	24697834	12300	0	0
gen_assertions[2].RstNOn_A	24697834	1110	0	0
gen_assertions[3].RstEnOff_A	24697893	12352	0	0
gen_assertions[3].RstEnOn_A	24697893	1162	0	0
gen_assertions[3].RstNOff_A	24697893	12352	0	0
gen_assertions[3].RstNOn_A	24697893	1162	0	0
gen_assertions[4].RstEnOff_A	1558611	21032	0	0
gen_assertions[4].RstEnOn_A	1558611	1214	0	0
gen_assertions[4].RstNOff_A	1558611	21032	0	0
gen_assertions[4].RstNOn_A	1558611	1214	0	0
gen_assertions[5].RstEnOff_A	12348402	13721	0	0
gen_assertions[5].RstEnOn_A	12348402	1258	0	0
gen_assertions[5].RstNOff_A	12348402	13721	0	0
gen_assertions[5].RstNOn_A	12348402	1258	0	0
gen_assertions[6].RstEnOff_A	12348402	13739	0	0
gen_assertions[6].RstEnOn_A	12348402	1277	0	0
gen_assertions[6].RstNOff_A	12348402	13739	0	0
gen_assertions[6].RstNOn_A	12348402	1277	0	0
gen_assertions[7].RstEnOff_A	12348402	13842	0	0
gen_assertions[7].RstEnOn_A	12348402	1378	0	0
gen_assertions[7].RstNOff_A	12348402	13842	0	0
gen_assertions[7].RstNOn_A	12348402	1378	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12348402	13457	0	0
T1	5332	5	0	0
T2	20532	34	0	0
T3	2339	4	0	0
T4	2819	0	0	0
T5	5793	4	0	0
T6	4103	4	0	0
T7	2053	0	0	0
T8	2916	0	0	0
T9	2059	0	0	0
T10	6272	2	0	0
T12	0	6	0	0
T14	0	5	0	0
T21	0	75	0	0
T49	0	4	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12348402	1140	0	0
T1	5332	6	0	0
T2	20532	0	0	0
T3	2339	0	0	0
T4	2819	0	0	0
T5	5793	0	0	0
T6	4103	0	0	0
T7	2053	0	0	0
T8	2916	0	0	0
T9	2059	0	0	0
T10	6272	2	0	0
T12	0	6	0	0
T14	0	1	0	0
T49	0	4	0	0
T50	0	1	0	0
T52	0	8	0	0
T96	0	3	0	0
T97	0	1	0	0
T98	0	1	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12348402	13457	0	0
T1	5332	5	0	0
T2	20532	34	0	0
T3	2339	4	0	0
T4	2819	0	0	0
T5	5793	4	0	0
T6	4103	4	0	0
T7	2053	0	0	0
T8	2916	0	0	0
T9	2059	0	0	0
T10	6272	2	0	0
T12	0	6	0	0
T14	0	5	0	0
T21	0	75	0	0
T49	0	4	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12348402	1140	0	0
T1	5332	6	0	0
T2	20532	0	0	0
T3	2339	0	0	0
T4	2819	0	0	0
T5	5793	0	0	0
T6	4103	0	0	0
T7	2053	0	0	0
T8	2916	0	0	0
T9	2059	0	0	0
T10	6272	2	0	0
T12	0	6	0	0
T14	0	1	0	0
T49	0	4	0	0
T50	0	1	0	0
T52	0	8	0	0
T96	0	3	0	0
T97	0	1	0	0
T98	0	1	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49394234	12251	0	0
T1	21328	8	0	0
T2	82133	30	0	0
T3	9357	4	0	0
T4	11280	0	0	0
T5	23180	4	0	0
T6	16421	4	0	0
T7	8221	0	0	0
T8	11669	0	0	0
T9	8242	0	0	0
T10	25094	3	0	0
T12	0	6	0	0
T14	0	4	0	0
T21	0	65	0	0
T49	0	5	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49394234	1131	0	0
T1	21328	9	0	0
T2	82133	0	0	0
T3	9357	0	0	0
T4	11280	0	0	0
T5	23180	0	0	0
T6	16421	0	0	0
T7	8221	0	0	0
T8	11669	0	0	0
T9	8242	0	0	0
T10	25094	3	0	0
T12	0	6	0	0
T14	0	2	0	0
T49	0	5	0	0
T50	0	3	0	0
T52	0	6	0	0
T96	0	6	0	0
T97	0	1	0	0
T99	0	2	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49394234	12251	0	0
T1	21328	8	0	0
T2	82133	30	0	0
T3	9357	4	0	0
T4	11280	0	0	0
T5	23180	4	0	0
T6	16421	4	0	0
T7	8221	0	0	0
T8	11669	0	0	0
T9	8242	0	0	0
T10	25094	3	0	0
T12	0	6	0	0
T14	0	4	0	0
T21	0	65	0	0
T49	0	5	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49394234	1131	0	0
T1	21328	9	0	0
T2	82133	0	0	0
T3	9357	0	0	0
T4	11280	0	0	0
T5	23180	0	0	0
T6	16421	0	0	0
T7	8221	0	0	0
T8	11669	0	0	0
T9	8242	0	0	0
T10	25094	3	0	0
T12	0	6	0	0
T14	0	2	0	0
T49	0	5	0	0
T50	0	3	0	0
T52	0	6	0	0
T96	0	6	0	0
T97	0	1	0	0
T99	0	2	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24697834	12300	0	0
T1	10664	7	0	0
T2	41063	30	0	0
T3	4679	4	0	0
T4	5640	0	0	0
T5	11587	4	0	0
T6	8208	4	0	0
T7	4109	0	0	0
T8	5834	0	0	0
T9	4120	0	0	0
T10	12546	4	0	0
T12	0	8	0	0
T14	0	4	0	0
T21	0	65	0	0
T49	0	6	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24697834	1110	0	0
T1	10664	7	0	0
T2	41063	0	0	0
T3	4679	0	0	0
T4	5640	0	0	0
T5	11587	0	0	0
T6	8208	0	0	0
T7	4109	0	0	0
T8	5834	0	0	0
T9	4120	0	0	0
T10	12546	4	0	0
T12	0	8	0	0
T49	0	6	0	0
T50	0	4	0	0
T52	0	8	0	0
T93	0	1	0	0
T96	0	7	0	0
T97	0	4	0	0
T99	0	3	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24697834	12300	0	0
T1	10664	7	0	0
T2	41063	30	0	0
T3	4679	4	0	0
T4	5640	0	0	0
T5	11587	4	0	0
T6	8208	4	0	0
T7	4109	0	0	0
T8	5834	0	0	0
T9	4120	0	0	0
T10	12546	4	0	0
T12	0	8	0	0
T14	0	4	0	0
T21	0	65	0	0
T49	0	6	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24697834	1110	0	0
T1	10664	7	0	0
T2	41063	0	0	0
T3	4679	0	0	0
T4	5640	0	0	0
T5	11587	0	0	0
T6	8208	0	0	0
T7	4109	0	0	0
T8	5834	0	0	0
T9	4120	0	0	0
T10	12546	4	0	0
T12	0	8	0	0
T49	0	6	0	0
T50	0	4	0	0
T52	0	8	0	0
T93	0	1	0	0
T96	0	7	0	0
T97	0	4	0	0
T99	0	3	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24697893	12352	0	0
T1	10663	6	0	0
T2	41068	30	0	0
T3	4683	4	0	0
T4	5640	0	0	0
T5	11588	4	0	0
T6	8209	4	0	0
T7	4109	0	0	0
T8	5834	0	0	0
T9	4120	0	0	0
T10	12547	5	0	0
T12	0	9	0	0
T14	0	4	0	0
T21	0	65	0	0
T49	0	7	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24697893	1162	0	0
T1	10663	6	0	0
T2	41068	0	0	0
T3	4683	0	0	0
T4	5640	0	0	0
T5	11588	0	0	0
T6	8209	0	0	0
T7	4109	0	0	0
T8	5834	0	0	0
T9	4120	0	0	0
T10	12547	5	0	0
T12	0	9	0	0
T49	0	7	0	0
T50	0	5	0	0
T52	0	7	0	0
T96	0	5	0	0
T97	0	5	0	0
T99	0	4	0	0
T100	0	11	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24697893	12352	0	0
T1	10663	6	0	0
T2	41068	30	0	0
T3	4683	4	0	0
T4	5640	0	0	0
T5	11588	4	0	0
T6	8209	4	0	0
T7	4109	0	0	0
T8	5834	0	0	0
T9	4120	0	0	0
T10	12547	5	0	0
T12	0	9	0	0
T14	0	4	0	0
T21	0	65	0	0
T49	0	7	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24697893	1162	0	0
T1	10663	6	0	0
T2	41068	0	0	0
T3	4683	0	0	0
T4	5640	0	0	0
T5	11588	0	0	0
T6	8209	0	0	0
T7	4109	0	0	0
T8	5834	0	0	0
T9	4120	0	0	0
T10	12547	5	0	0
T12	0	9	0	0
T49	0	7	0	0
T50	0	5	0	0
T52	0	7	0	0
T96	0	5	0	0
T97	0	5	0	0
T99	0	4	0	0
T100	0	11	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1558611	21032	0	0
T1	665	9	0	0
T2	2655	52	0	0
T3	290	6	0	0
T4	352	2	0	0
T5	724	6	0	0
T6	511	6	0	0
T7	256	1	0	0
T8	363	2	0	0
T9	256	1	0	0
T10	784	6	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1558611	1214	0	0
T1	665	9	0	0
T2	2655	0	0	0
T3	290	0	0	0
T4	352	0	0	0
T5	724	0	0	0
T6	511	0	0	0
T7	256	0	0	0
T8	363	0	0	0
T9	256	0	0	0
T10	784	5	0	0
T12	0	10	0	0
T23	0	1	0	0
T49	0	8	0	0
T50	0	6	0	0
T52	0	7	0	0
T96	0	6	0	0
T97	0	6	0	0
T99	0	5	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1558611	21032	0	0
T1	665	9	0	0
T2	2655	52	0	0
T3	290	6	0	0
T4	352	2	0	0
T5	724	6	0	0
T6	511	6	0	0
T7	256	1	0	0
T8	363	2	0	0
T9	256	1	0	0
T10	784	6	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1558611	1214	0	0
T1	665	9	0	0
T2	2655	0	0	0
T3	290	0	0	0
T4	352	0	0	0
T5	724	0	0	0
T6	511	0	0	0
T7	256	0	0	0
T8	363	0	0	0
T9	256	0	0	0
T10	784	5	0	0
T12	0	10	0	0
T23	0	1	0	0
T49	0	8	0	0
T50	0	6	0	0
T52	0	7	0	0
T96	0	6	0	0
T97	0	6	0	0
T99	0	5	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12348402	13721	0	0
T1	5332	8	0	0
T2	20532	34	0	0
T3	2339	4	0	0
T4	2819	0	0	0
T5	5793	4	0	0
T6	4103	4	0	0
T7	2053	0	0	0
T8	2916	0	0	0
T9	2059	0	0	0
T10	6272	7	0	0
T12	0	12	0	0
T14	0	5	0	0
T21	0	75	0	0
T49	0	8	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12348402	1258	0	0
T1	5332	8	0	0
T2	20532	0	0	0
T3	2339	0	0	0
T4	2819	0	0	0
T5	5793	0	0	0
T6	4103	0	0	0
T7	2053	0	0	0
T8	2916	0	0	0
T9	2059	0	0	0
T10	6272	7	0	0
T12	0	12	0	0
T49	0	8	0	0
T50	0	7	0	0
T52	0	7	0	0
T96	0	7	0	0
T97	0	7	0	0
T99	0	7	0	0
T100	0	13	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12348402	13721	0	0
T1	5332	8	0	0
T2	20532	34	0	0
T3	2339	4	0	0
T4	2819	0	0	0
T5	5793	4	0	0
T6	4103	4	0	0
T7	2053	0	0	0
T8	2916	0	0	0
T9	2059	0	0	0
T10	6272	7	0	0
T12	0	12	0	0
T14	0	5	0	0
T21	0	75	0	0
T49	0	8	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12348402	1258	0	0
T1	5332	8	0	0
T2	20532	0	0	0
T3	2339	0	0	0
T4	2819	0	0	0
T5	5793	0	0	0
T6	4103	0	0	0
T7	2053	0	0	0
T8	2916	0	0	0
T9	2059	0	0	0
T10	6272	7	0	0
T12	0	12	0	0
T49	0	8	0	0
T50	0	7	0	0
T52	0	7	0	0
T96	0	7	0	0
T97	0	7	0	0
T99	0	7	0	0
T100	0	13	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12348402	13739	0	0
T1	5332	8	0	0
T2	20532	34	0	0
T3	2339	4	0	0
T4	2819	0	0	0
T5	5793	4	0	0
T6	4103	4	0	0
T7	2053	0	0	0
T8	2916	0	0	0
T9	2059	0	0	0
T10	6272	8	0	0
T12	0	11	0	0
T14	0	5	0	0
T21	0	75	0	0
T49	0	12	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12348402	1277	0	0
T1	5332	8	0	0
T2	20532	0	0	0
T3	2339	0	0	0
T4	2819	0	0	0
T5	5793	0	0	0
T6	4103	0	0	0
T7	2053	0	0	0
T8	2916	0	0	0
T9	2059	0	0	0
T10	6272	8	0	0
T12	0	11	0	0
T49	0	12	0	0
T50	0	8	0	0
T52	0	8	0	0
T96	0	8	0	0
T97	0	8	0	0
T99	0	7	0	0
T100	0	12	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12348402	13739	0	0
T1	5332	8	0	0
T2	20532	34	0	0
T3	2339	4	0	0
T4	2819	0	0	0
T5	5793	4	0	0
T6	4103	4	0	0
T7	2053	0	0	0
T8	2916	0	0	0
T9	2059	0	0	0
T10	6272	8	0	0
T12	0	11	0	0
T14	0	5	0	0
T21	0	75	0	0
T49	0	12	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12348402	1277	0	0
T1	5332	8	0	0
T2	20532	0	0	0
T3	2339	0	0	0
T4	2819	0	0	0
T5	5793	0	0	0
T6	4103	0	0	0
T7	2053	0	0	0
T8	2916	0	0	0
T9	2059	0	0	0
T10	6272	8	0	0
T12	0	11	0	0
T49	0	12	0	0
T50	0	8	0	0
T52	0	8	0	0
T96	0	8	0	0
T97	0	8	0	0
T99	0	7	0	0
T100	0	12	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12348402	13842	0	0
T1	5332	7	0	0
T2	20532	34	0	0
T3	2339	4	0	0
T4	2819	0	0	0
T5	5793	4	0	0
T6	4103	4	0	0
T7	2053	0	0	0
T8	2916	0	0	0
T9	2059	0	0	0
T10	6272	8	0	0
T12	0	12	0	0
T14	0	5	0	0
T21	0	75	0	0
T49	0	11	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12348402	1378	0	0
T1	5332	7	0	0
T2	20532	0	0	0
T3	2339	0	0	0
T4	2819	0	0	0
T5	5793	0	0	0
T6	4103	0	0	0
T7	2053	0	0	0
T8	2916	0	0	0
T9	2059	0	0	0
T10	6272	8	0	0
T12	0	12	0	0
T49	0	11	0	0
T50	0	9	0	0
T93	0	1	0	0
T96	0	9	0	0
T97	0	8	0	0
T98	0	1	0	0
T99	0	7	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12348402	13842	0	0
T1	5332	7	0	0
T2	20532	34	0	0
T3	2339	4	0	0
T4	2819	0	0	0
T5	5793	4	0	0
T6	4103	4	0	0
T7	2053	0	0	0
T8	2916	0	0	0
T9	2059	0	0	0
T10	6272	8	0	0
T12	0	12	0	0
T14	0	5	0	0
T21	0	75	0	0
T49	0	11	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12348402	1378	0	0
T1	5332	7	0	0
T2	20532	0	0	0
T3	2339	0	0	0
T4	2819	0	0	0
T5	5793	0	0	0
T6	4103	0	0	0
T7	2053	0	0	0
T8	2916	0	0	0
T9	2059	0	0	0
T10	6272	8	0	0
T12	0	12	0	0
T49	0	11	0	0
T50	0	9	0	0
T93	0	1	0	0
T96	0	9	0	0
T97	0	8	0	0
T98	0	1	0	0
T99	0	7	0	0