Unified Coverage Report :: Module :: rstmgr_reg_top

Module : rstmgr_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_systems_rstmgr_reg_0.1/rtl/autogen/rstmgr_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.65	98.40	99.85	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_info	100.00	100.00
u_alert_info_attr	33.33	33.33
u_alert_info_ctrl_en	100.00	100.00	100.00			100.00
u_alert_info_ctrl_index	100.00	100.00	100.00			100.00
u_alert_regwen	100.00	100.00	100.00			100.00
u_alert_test_fatal_cnsty_fault	100.00	100.00
u_alert_test_fatal_fault	100.00	100.00
u_chk	100.00	100.00		100.00			100.00
u_cpu_info	100.00	100.00
u_cpu_info_attr	33.33	33.33
u_cpu_info_ctrl_en	100.00	100.00	100.00			100.00
u_cpu_info_ctrl_index	100.00	100.00	100.00			100.00
u_cpu_regwen	100.00	100.00	100.00			100.00
u_err_code_fsm_err	96.30	88.89	100.00			100.00
u_err_code_reg_intg_err	96.30	88.89	100.00			100.00
u_err_code_reset_consistency_err	96.30	88.89	100.00			100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_reg_if	98.97	97.14	98.75			100.00	100.00
u_reset_info_hw_req	100.00	100.00	100.00			100.00
u_reset_info_low_power_exit	100.00	100.00	100.00			100.00
u_reset_info_por	100.00	100.00	100.00			100.00
u_reset_info_sw_reset	100.00	100.00	100.00			100.00
u_reset_req	100.00	100.00	100.00			100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_sw_rst_ctrl_n_0	100.00	100.00	100.00			100.00
u_sw_rst_ctrl_n_1	100.00	100.00	100.00			100.00
u_sw_rst_ctrl_n_2	100.00	100.00	100.00			100.00
u_sw_rst_ctrl_n_3	100.00	100.00	100.00			100.00
u_sw_rst_ctrl_n_4	100.00	100.00	100.00			100.00
u_sw_rst_ctrl_n_5	100.00	100.00	100.00			100.00
u_sw_rst_ctrl_n_6	100.00	100.00	100.00			100.00
u_sw_rst_ctrl_n_7	100.00	100.00	100.00			100.00
u_sw_rst_regwen_0	100.00	100.00	100.00			100.00
u_sw_rst_regwen_1	100.00	100.00	100.00			100.00
u_sw_rst_regwen_2	100.00	100.00	100.00			100.00
u_sw_rst_regwen_3	100.00	100.00	100.00			100.00
u_sw_rst_regwen_4	100.00	100.00	100.00			100.00
u_sw_rst_regwen_5	100.00	100.00	100.00			100.00
u_sw_rst_regwen_6	100.00	100.00	100.00			100.00
u_sw_rst_regwen_7	100.00	100.00	100.00			100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_reg_top

	Line No.	Total	Covered	Percent
TOTAL		178	178	100.00
ALWAYS	73	4	4	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	226	1	1	100.00
CONT_ASSIGN	241	1	1	100.00
CONT_ASSIGN	257	1	1	100.00
CONT_ASSIGN	433	1	1	100.00
CONT_ASSIGN	554	1	1	100.00
CONT_ASSIGN	880	1	1	100.00
CONT_ASSIGN	912	1	1	100.00
CONT_ASSIGN	944	1	1	100.00
CONT_ASSIGN	976	1	1	100.00
CONT_ASSIGN	1008	1	1	100.00
CONT_ASSIGN	1040	1	1	100.00
CONT_ASSIGN	1072	1	1	100.00
CONT_ASSIGN	1104	1	1	100.00
ALWAYS	1218	29	29	100.00
CONT_ASSIGN	1249	1	1	100.00
ALWAYS	1253	1	1	100.00
CONT_ASSIGN	1285	1	1	100.00
CONT_ASSIGN	1287	1	1	100.00
CONT_ASSIGN	1289	1	1	100.00
CONT_ASSIGN	1290	1	1	100.00
CONT_ASSIGN	1292	1	1	100.00
CONT_ASSIGN	1293	1	1	100.00
CONT_ASSIGN	1295	1	1	100.00
CONT_ASSIGN	1297	1	1	100.00
CONT_ASSIGN	1299	1	1	100.00
CONT_ASSIGN	1301	1	1	100.00
CONT_ASSIGN	1302	1	1	100.00
CONT_ASSIGN	1304	1	1	100.00
CONT_ASSIGN	1305	1	1	100.00
CONT_ASSIGN	1307	1	1	100.00
CONT_ASSIGN	1309	1	1	100.00
CONT_ASSIGN	1310	1	1	100.00
CONT_ASSIGN	1311	1	1	100.00
CONT_ASSIGN	1312	1	1	100.00
CONT_ASSIGN	1314	1	1	100.00
CONT_ASSIGN	1315	1	1	100.00
CONT_ASSIGN	1317	1	1	100.00
CONT_ASSIGN	1319	1	1	100.00
CONT_ASSIGN	1320	1	1	100.00
CONT_ASSIGN	1321	1	1	100.00
CONT_ASSIGN	1322	1	1	100.00
CONT_ASSIGN	1324	1	1	100.00
CONT_ASSIGN	1325	1	1	100.00
CONT_ASSIGN	1327	1	1	100.00
CONT_ASSIGN	1328	1	1	100.00
CONT_ASSIGN	1330	1	1	100.00
CONT_ASSIGN	1331	1	1	100.00
CONT_ASSIGN	1333	1	1	100.00
CONT_ASSIGN	1334	1	1	100.00
CONT_ASSIGN	1336	1	1	100.00
CONT_ASSIGN	1337	1	1	100.00
CONT_ASSIGN	1339	1	1	100.00
CONT_ASSIGN	1340	1	1	100.00
CONT_ASSIGN	1342	1	1	100.00
CONT_ASSIGN	1343	1	1	100.00
CONT_ASSIGN	1345	1	1	100.00
CONT_ASSIGN	1346	1	1	100.00
CONT_ASSIGN	1348	1	1	100.00
CONT_ASSIGN	1349	1	1	100.00
CONT_ASSIGN	1351	1	1	100.00
CONT_ASSIGN	1352	1	1	100.00
CONT_ASSIGN	1354	1	1	100.00
CONT_ASSIGN	1355	1	1	100.00
CONT_ASSIGN	1357	1	1	100.00
CONT_ASSIGN	1358	1	1	100.00
CONT_ASSIGN	1360	1	1	100.00
CONT_ASSIGN	1361	1	1	100.00
CONT_ASSIGN	1363	1	1	100.00
CONT_ASSIGN	1364	1	1	100.00
CONT_ASSIGN	1366	1	1	100.00
CONT_ASSIGN	1367	1	1	100.00
CONT_ASSIGN	1369	1	1	100.00
ALWAYS	1373	29	29	100.00
ALWAYS	1406	38	38	100.00
CONT_ASSIGN	1539	0	0
CONT_ASSIGN	1547	1	1	100.00
CONT_ASSIGN	1548	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_systems_rstmgr_reg_0.1/rtl/autogen/rstmgr_reg_top.sv' or '../src/lowrisc_systems_rstmgr_reg_0.1/rtl/autogen/rstmgr_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
82	1	1
94	1	1
95	1	1
123	1	1
124	1	1
226	1	1
241	1	1
257	1	1
433	1	1
554	1	1
880	1	1
912	1	1
944	1	1
976	1	1
1008	1	1
1040	1	1
1072	1	1
1104	1	1
1218	1	1
1219	1	1
1220	1	1
1221	1	1
1222	1	1
1223	1	1
1224	1	1
1225	1	1
1226	1	1
1227	1	1
1228	1	1
1229	1	1
1230	1	1
1231	1	1
1232	1	1
1233	1	1
1234	1	1
1235	1	1
1236	1	1
1237	1	1
1238	1	1
1239	1	1
1240	1	1
1241	1	1
1242	1	1
1243	1	1
1244	1	1
1245	1	1
1246	1	1
1249	1	1
1253	1	1
1285	1	1
1287	1	1
1289	1	1
1290	1	1
1292	1	1
1293	1	1
1295	1	1
1297	1	1
1299	1	1
1301	1	1
1302	1	1
1304	1	1
1305	1	1
1307	1	1
1309	1	1
1310	1	1
1311	1	1
1312	1	1
1314	1	1
1315	1	1
1317	1	1
1319	1	1
1320	1	1
1321	1	1
1322	1	1
1324	1	1
1325	1	1
1327	1	1
1328	1	1
1330	1	1
1331	1	1
1333	1	1
1334	1	1
1336	1	1
1337	1	1
1339	1	1
1340	1	1
1342	1	1
1343	1	1
1345	1	1
1346	1	1
1348	1	1
1349	1	1
1351	1	1
1352	1	1
1354	1	1
1355	1	1
1357	1	1
1358	1	1
1360	1	1
1361	1	1
1363	1	1
1364	1	1
1366	1	1
1367	1	1
1369	1	1
1373	1	1
1374	1	1
1375	1	1
1376	1	1
1377	1	1
1378	1	1
1379	1	1
1380	1	1
1381	1	1
1382	1	1
1383	1	1
1384	1	1
1385	1	1
1386	1	1
1387	1	1
1388	1	1
1389	1	1
1390	1	1
1391	1	1
1392	1	1
1393	1	1
1394	1	1
1395	1	1
1396	1	1
1397	1	1
1398	1	1
1399	1	1
1400	1	1
1401	1	1
1406	1	1
1407	1	1
1409	1	1
1410	1	1
1414	1	1
1418	1	1
1419	1	1
1420	1	1
1421	1	1
1425	1	1
1429	1	1
1430	1	1
1434	1	1
1438	1	1
1442	1	1
1446	1	1
1447	1	1
1451	1	1
1455	1	1
1459	1	1
1463	1	1
1467	1	1
1471	1	1
1475	1	1
1479	1	1
1483	1	1
1487	1	1
1491	1	1
1495	1	1
1499	1	1
1503	1	1
1507	1	1
1511	1	1
1515	1	1
1519	1	1
1523	1	1
1524	1	1
1525	1	1
1539		unreachable
1547	1	1
1548	1	1

---

Cond Coverage for Module : rstmgr_reg_top

	Total	Covered	Percent
Conditions	331	331	100.00
Logical	331	331	100.00
Non-Logical	0	0
Event	0	0

 LINE       63
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T77,T78,T79
1	1	Covered	T1,T2,T3

 LINE       75
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T61,T81,T82
1	0	Covered	T83,T84,T103

 LINE       82
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T61,T81,T82
0	1	0	Covered	T83,T84,T103
1	0	0	Covered	T61,T83,T84

 LINE       124
 EXPRESSION ((devmode_i & addrmiss) | wr_err | intg_err)
             -----------1----------   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T83,T84,T103
0	1	0	Covered	T77,T78,T79
1	0	0	Covered	T77,T78,T79

 LINE       124
 SUB-EXPRESSION (devmode_i & addrmiss)
                 ----1----   ----2---

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T77,T78,T79

 LINE       433
 EXPRESSION (alert_info_ctrl_we & alert_regwen_qs)
             ---------1--------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T74,T75,T130
1	1	Covered	T1,T2,T3

 LINE       554
 EXPRESSION (cpu_info_ctrl_we & cpu_regwen_qs)
             --------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T76,T83,T84
1	1	Covered	T1,T2,T3

 LINE       880
 EXPRESSION (sw_rst_ctrl_n_0_we & sw_rst_regwen_0_qs)
             ---------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T12,T49
1	1	Covered	T1,T5,T10

 LINE       912
 EXPRESSION (sw_rst_ctrl_n_1_we & sw_rst_regwen_1_qs)
             ---------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T10,T12
1	1	Covered	T1,T10,T12

 LINE       944
 EXPRESSION (sw_rst_ctrl_n_2_we & sw_rst_regwen_2_qs)
             ---------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T10,T12
1	1	Covered	T1,T10,T12

 LINE       976
 EXPRESSION (sw_rst_ctrl_n_3_we & sw_rst_regwen_3_qs)
             ---------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T10,T12
1	1	Covered	T1,T10,T12

 LINE       1008
 EXPRESSION (sw_rst_ctrl_n_4_we & sw_rst_regwen_4_qs)
             ---------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T10,T12
1	1	Covered	T1,T10,T12

 LINE       1040
 EXPRESSION (sw_rst_ctrl_n_5_we & sw_rst_regwen_5_qs)
             ---------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T10,T12
1	1	Covered	T1,T10,T12

 LINE       1072
 EXPRESSION (sw_rst_ctrl_n_6_we & sw_rst_regwen_6_qs)
             ---------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T12,T49
1	1	Covered	T1,T5,T10

 LINE       1104
 EXPRESSION (sw_rst_ctrl_n_7_we & sw_rst_regwen_7_qs)
             ---------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T10,T12
1	1	Covered	T1,T10,T12

 LINE       1219
 EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_ALERT_TEST_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T7,T9

 LINE       1220
 EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_RESET_REQ_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       1221
 EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_RESET_INFO_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       1222
 EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_ALERT_REGWEN_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T11,T23

 LINE       1223
 EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_ALERT_INFO_CTRL_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1224
 EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_ALERT_INFO_ATTR_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T23,T24

 LINE       1225
 EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_ALERT_INFO_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       1226
 EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_CPU_REGWEN_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T13,T23

 LINE       1227
 EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_CPU_INFO_CTRL_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1228
 EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_CPU_INFO_ATTR_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T23,T24

 LINE       1229
 EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_CPU_INFO_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       1230
 EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_SW_RST_REGWEN_0_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T10

 LINE       1231
 EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_SW_RST_REGWEN_1_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T10

 LINE       1232
 EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_SW_RST_REGWEN_2_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T10

 LINE       1233
 EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_SW_RST_REGWEN_3_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T10

 LINE       1234
 EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_SW_RST_REGWEN_4_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T10

 LINE       1235
 EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_SW_RST_REGWEN_5_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T10

 LINE       1236
 EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_SW_RST_REGWEN_6_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T10

 LINE       1237
 EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_SW_RST_REGWEN_7_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T10

 LINE       1238
 EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_SW_RST_CTRL_N_0_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       1239
 EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_SW_RST_CTRL_N_1_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       1240
 EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_SW_RST_CTRL_N_2_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       1241
 EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_SW_RST_CTRL_N_3_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       1242
 EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_SW_RST_CTRL_N_4_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       1243
 EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_SW_RST_CTRL_N_5_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       1244
 EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_SW_RST_CTRL_N_6_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       1245
 EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_SW_RST_CTRL_N_7_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       1246
 EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_ERR_CODE_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T23,T24

 LINE       1249
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1249
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       1253
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1 & (~reg_be))))) | (addr_hit[17] & ((|(4'b1 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1 & (~reg_be))))) | (addr_hit[19] & ((|(4'b1 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1 & (~reg_be))))) | (addr_hit[22] & ((|(4'b1 & (~reg_be))))) | (addr_hit[23] & ((|(4'b1 & (~reg_be))))) | (addr_hit[24] & ((|(4'b1 & (~reg_be))))) | (addr_hit[25] & ((|(4'b1 & (~reg_be))))) | (addr_hit[26] & ((|(4'b1 & (~reg_be))))) | (addr_hit[27] & ((|(4'b1 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T77,T78,T79

 LINE       1253
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b1 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b1 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b1 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b1 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b1 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b1 & (~reg_be))))) | 
     22  (addr_hit[21] & ((|(4'b1 & (~reg_be))))) | 
     23  (addr_hit[22] & ((|(4'b1 & (~reg_be))))) | 
     24  (addr_hit[23] & ((|(4'b1 & (~reg_be))))) | 
     25  (addr_hit[24] & ((|(4'b1 & (~reg_be))))) | 
     26  (addr_hit[25] & ((|(4'b1 & (~reg_be))))) | 
     27  (addr_hit[26] & ((|(4'b1 & (~reg_be))))) | 
     28  (addr_hit[27] & ((|(4'b1 & (~reg_be))))))

Sensitive Expression == 1	Status	Tests
ALL ZEROS	Covered	T1,T2,T3
28 (addr_hit[27] & ((|(4'...	Covered	T2,T23,T24
27 (addr_hit[26] & ((|(4'...	Covered	T1,T2,T5
26 (addr_hit[25] & ((|(4'...	Covered	T1,T2,T5
25 (addr_hit[24] & ((|(4'...	Covered	T1,T2,T5
24 (addr_hit[23] & ((|(4'...	Covered	T1,T2,T5
23 (addr_hit[22] & ((|(4'...	Covered	T1,T2,T5
22 (addr_hit[21] & ((|(4'...	Covered	T1,T2,T5
21 (addr_hit[20] & ((|(4'...	Covered	T1,T2,T5
20 (addr_hit[19] & ((|(4'...	Covered	T1,T2,T5
19 (addr_hit[18] & ((|(4'...	Covered	T2,T5,T10
18 (addr_hit[17] & ((|(4'...	Covered	T2,T10,T12
17 (addr_hit[16] & ((|(4'...	Covered	T2,T5,T10
16 (addr_hit[15] & ((|(4'...	Covered	T2,T5,T10
15 (addr_hit[14] & ((|(4'...	Covered	T2,T5,T10
14 (addr_hit[13] & ((|(4'...	Covered	T2,T5,T10
13 (addr_hit[12] & ((|(4'...	Covered	T2,T10,T12
12 (addr_hit[11] & ((|(4'...	Covered	T2,T5,T10
11 (addr_hit[10] & ((|(4'...	Covered	T2,T3,T5
10 (addr_hit[9] & ((|(4'b...	Covered	T2,T23,T24
9 (addr_hit[8] & ((|(4'b...	Covered	T2,T23,T24
8 (addr_hit[7] & ((|(4'b...	Covered	T2,T23,T24
7 (addr_hit[6] & ((|(4'b...	Covered	T2,T3,T5
6 (addr_hit[5] & ((|(4'b...	Covered	T2,T23,T24
5 (addr_hit[4] & ((|(4'b...	Covered	T2,T23,T24
4 (addr_hit[3] & ((|(4'b...	Covered	T2,T23,T24
3 (addr_hit[2] & ((|(4'b...	Covered	T2,T3,T5
2 (addr_hit[1] & ((|(4'b...	Covered	T2,T11,T23
1 (addr_hit[0] & ((|(4'b...	Covered	T2,T23,T24

 LINE       1253
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T9
1	1	Covered	T2,T23,T24

 LINE       1253
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T2,T11,T23

 LINE       1253
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T5

 LINE       1253
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T11,T23
1	1	Covered	T2,T23,T24

 LINE       1253
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T23,T24

 LINE       1253
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T23,T24
1	1	Covered	T2,T23,T24

 LINE       1253
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T2,T3,T5

 LINE       1253
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T13,T23
1	1	Covered	T2,T23,T24

 LINE       1253
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T23,T24

 LINE       1253
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T23,T24
1	1	Covered	T2,T23,T24

 LINE       1253
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T2,T3,T5

 LINE       1253
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T10
1	1	Covered	T2,T5,T10

 LINE       1253
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T10
1	1	Covered	T2,T10,T12

 LINE       1253
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T10
1	1	Covered	T2,T5,T10

 LINE       1253
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T10
1	1	Covered	T2,T5,T10

 LINE       1253
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T10
1	1	Covered	T2,T5,T10

 LINE       1253
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T10
1	1	Covered	T2,T5,T10

 LINE       1253
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T10
1	1	Covered	T2,T10,T12

 LINE       1253
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T10
1	1	Covered	T2,T5,T10

 LINE       1253
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       1253
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       1253
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       1253
 SUB-EXPRESSION (addr_hit[22] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       1253
 SUB-EXPRESSION (addr_hit[23] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       1253
 SUB-EXPRESSION (addr_hit[24] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       1253
 SUB-EXPRESSION (addr_hit[25] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       1253
 SUB-EXPRESSION (addr_hit[26] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       1253
 SUB-EXPRESSION (addr_hit[27] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T23,T24
1	1	Covered	T2,T23,T24

 LINE       1285
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T7,T9
1	1	0	Covered	T77,T78,T102
1	1	1	Covered	T7,T9,T53

 LINE       1290
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T5
1	1	0	Covered	T77,T78,T79
1	1	1	Covered	T2,T3,T5

 LINE       1293
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T77,T78,T102
1	1	1	Covered	T2,T3,T5

 LINE       1302
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T23
1	1	0	Covered	T84,T102,T105
1	1	1	Covered	T74,T75,T76

 LINE       1305
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T78,T79,T102
1	1	1	Covered	T1,T2,T3

 LINE       1310
 EXPRESSION (addr_hit[5] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T23,T24
1	1	0	Covered	T135,T136
1	1	1	Covered	T2,T24,T51

 LINE       1311
 EXPRESSION (addr_hit[6] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T5
1	1	0	Covered	T135,T136,T137
1	1	1	Covered	T2,T3,T5

 LINE       1312
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T13,T23
1	1	0	Covered	T78,T83,T138
1	1	1	Covered	T74,T75,T76

 LINE       1315
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T77,T78,T79
1	1	1	Covered	T1,T2,T3

 LINE       1320
 EXPRESSION (addr_hit[9] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T23,T24
1	1	0	Covered	T84,T137
1	1	1	Covered	T2,T24,T51

 LINE       1321
 EXPRESSION (addr_hit[10] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T5
1	1	0	Covered	T139,T140,T141
1	1	1	Covered	T2,T3,T5

 LINE       1322
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T5,T10
1	1	0	Covered	T78,T102,T104
1	1	1	Covered	T5,T10,T12

 LINE       1325
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T5,T10
1	1	0	Covered	T77,T78,T102
1	1	1	Covered	T5,T10,T12

 LINE       1328
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T5,T10
1	1	0	Covered	T78,T79,T102
1	1	1	Covered	T5,T10,T12

 LINE       1331
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T5,T10
1	1	0	Covered	T78,T102,T104
1	1	1	Covered	T5,T10,T12

 LINE       1334
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T5,T10
1	1	0	Covered	T78,T79,T104
1	1	1	Covered	T5,T10,T12

 LINE       1337
 EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T5,T10
1	1	0	Covered	T78,T79,T105
1	1	1	Covered	T5,T10,T12

 LINE       1340
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T5,T10
1	1	0	Covered	T78,T79,T102
1	1	1	Covered	T5,T10,T12

 LINE       1343
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T5,T10
1	1	0	Covered	T77,T78,T83
1	1	1	Covered	T5,T10,T12

 LINE       1346
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T5
1	1	0	Covered	T77,T78,T79
1	1	1	Covered	T1,T5,T10

 LINE       1349
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T5
1	1	0	Covered	T77,T78,T104
1	1	1	Covered	T1,T5,T10

 LINE       1352
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T5
1	1	0	Covered	T78,T104,T105
1	1	1	Covered	T1,T5,T10

 LINE       1355
 EXPRESSION (addr_hit[22] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T5
1	1	0	Covered	T78,T79,T102
1	1	1	Covered	T1,T5,T10

 LINE       1358
 EXPRESSION (addr_hit[23] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T5
1	1	0	Covered	T77,T78,T79
1	1	1	Covered	T1,T5,T10

 LINE       1361
 EXPRESSION (addr_hit[24] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T5
1	1	0	Covered	T78,T79,T84
1	1	1	Covered	T1,T5,T10

 LINE       1364
 EXPRESSION (addr_hit[25] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T5
1	1	0	Covered	T78,T79,T104
1	1	1	Covered	T1,T5,T10

 LINE       1367
 EXPRESSION (addr_hit[26] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T5
1	1	0	Covered	T77,T78,T79
1	1	1	Covered	T1,T5,T10

---

Branch Coverage for Module : rstmgr_reg_top

	Line No.	Total	Covered	Percent
Branches		34	34	100.00
TERNARY	1249	2	2	100.00
IF	73	3	3	100.00
CASE	1407	29	29	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_systems_rstmgr_reg_0.1/rtl/autogen/rstmgr_reg_top.sv' or '../src/lowrisc_systems_rstmgr_reg_0.1/rtl/autogen/rstmgr_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	1249	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	73	if ((!rst_ni))
-2-:	75	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T61,T83,T84
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1407	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T1,T2,T3
addr_hit[2]	Covered	T1,T2,T3
addr_hit[3]	Covered	T1,T2,T3
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T1,T2,T3
addr_hit[6]	Covered	T1,T2,T3
addr_hit[7]	Covered	T1,T2,T3
addr_hit[8]	Covered	T1,T2,T3
addr_hit[9]	Covered	T1,T2,T3
addr_hit[10]	Covered	T1,T2,T3
addr_hit[11]	Covered	T1,T2,T3
addr_hit[12]	Covered	T1,T2,T3
addr_hit[13]	Covered	T1,T2,T3
addr_hit[14]	Covered	T1,T2,T3
addr_hit[15]	Covered	T1,T2,T3
addr_hit[16]	Covered	T1,T2,T3
addr_hit[17]	Covered	T1,T2,T3
addr_hit[18]	Covered	T1,T2,T3
addr_hit[19]	Covered	T1,T2,T3
addr_hit[20]	Covered	T1,T2,T3
addr_hit[21]	Covered	T1,T2,T3
addr_hit[22]	Covered	T1,T2,T3
addr_hit[23]	Covered	T1,T2,T3
addr_hit[24]	Covered	T1,T2,T3
addr_hit[25]	Covered	T1,T2,T3
addr_hit[26]	Covered	T1,T2,T3
addr_hit[27]	Covered	T1,T2,T3
default	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	11653439	937216	0	0
reAfterRv	11653439	937055	0	0
rePulse	11653439	500766	0	0
wePulse	11653439	436289	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	11653439	937216	0	0
T1	5241	450	0	0
T2	15819	2633	0	0
T3	2098	212	0	0
T4	2681	1	0	0
T5	5601	379	0	0
T6	3861	212	0	0
T7	1988	33	0	0
T8	2874	1	0	0
T9	1969	29	0	0
T10	6230	712	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	11653439	937055	0	0
T1	5241	450	0	0
T2	15819	2633	0	0
T3	2098	212	0	0
T4	2681	1	0	0
T5	5601	379	0	0
T6	3861	212	0	0
T7	1988	33	0	0
T8	2874	1	0	0
T9	1969	29	0	0
T10	6230	712	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	11653439	500766	0	0
T1	5241	224	0	0
T2	15819	1482	0	0
T3	2098	99	0	0
T4	2681	1	0	0
T5	5601	186	0	0
T6	3861	99	0	0
T7	1988	0	0	0
T8	2874	1	0	0
T9	1969	0	0	0
T10	6230	379	0	0
T11	0	1	0	0
T12	0	515	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	11653439	436289	0	0
T1	5241	226	0	0
T2	15819	1151	0	0
T3	2098	113	0	0
T4	2681	0	0	0
T5	5601	193	0	0
T6	3861	113	0	0
T7	1988	33	0	0
T8	2874	0	0	0
T9	1969	29	0	0
T10	6230	333	0	0
T12	0	469	0	0
T14	0	53	0	0