Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	11653439	8592	0	0
alert_regwen_rd_A	11653439	3929	0	0
cpu_regwen_rd_A	11653439	3953	0	0
sw_rst_ctrl_n_0_rd_A	11653439	8150	0	0
sw_rst_ctrl_n_1_rd_A	11653439	7979	0	0
sw_rst_ctrl_n_2_rd_A	11653439	8297	0	0
sw_rst_ctrl_n_3_rd_A	11653439	8174	0	0
sw_rst_ctrl_n_4_rd_A	11653439	8107	0	0
sw_rst_ctrl_n_5_rd_A	11653439	8382	0	0
sw_rst_ctrl_n_6_rd_A	11653439	8316	0	0
sw_rst_ctrl_n_7_rd_A	11653439	8324	0	0
sw_rst_regwen_0_rd_A	11653439	4494	0	0
sw_rst_regwen_1_rd_A	11653439	4400	0	0
sw_rst_regwen_2_rd_A	11653439	4684	0	0
sw_rst_regwen_3_rd_A	11653439	4525	0	0
sw_rst_regwen_4_rd_A	11653439	4540	0	0
sw_rst_regwen_5_rd_A	11653439	4507	0	0
sw_rst_regwen_6_rd_A	11653439	4547	0	0
sw_rst_regwen_7_rd_A	11653439	4420	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11653439	8592	0	0
T74	2197	8	0	0
T77	7779	163	0	0
T78	12449	345	0	0
T79	8837	363	0	0
T84	22013	6	0	0
T102	13080	603	0	0
T103	21684	3	0	0
T107	3090	0	0	0
T108	2287	0	0	0
T111	0	12	0	0
T142	4002	3	0	0
T143	0	4	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11653439	3929	0	0
T52	95620	147	0	0
T53	1669	0	0	0
T54	26194	0	0	0
T60	5891	0	0	0
T61	385962	0	0	0
T77	0	8	0	0
T78	0	26	0	0
T79	0	6	0	0
T84	0	65	0	0
T100	8836	0	0	0
T102	0	4	0	0
T113	34918	33	0	0
T116	32445	43	0	0
T117	88886	0	0	0
T121	0	1	0	0
T142	0	11	0	0
T144	1617	0	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11653439	3953	0	0
T52	95620	148	0	0
T53	1669	0	0	0
T54	26194	0	0	0
T60	5891	0	0	0
T61	385962	0	0	0
T77	0	10	0	0
T78	0	24	0	0
T79	0	24	0	0
T84	0	89	0	0
T100	8836	0	0	0
T102	0	37	0	0
T113	34918	25	0	0
T116	32445	65	0	0
T117	88886	0	0	0
T121	0	3	0	0
T142	0	2	0	0
T144	1617	0	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11653439	8150	0	0
T5	5601	5	0	0
T6	3861	0	0	0
T7	1988	0	0	0
T8	2874	0	0	0
T9	1969	0	0	0
T10	6230	0	0	0
T11	3468	0	0	0
T12	8032	0	0	0
T13	5500	0	0	0
T14	1539	0	0	0
T41	0	131	0	0
T42	0	17	0	0
T50	0	114	0	0
T52	0	175	0	0
T60	0	19	0	0
T93	0	8	0	0
T97	0	70	0	0
T98	0	12	0	0
T113	0	41	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11653439	7979	0	0
T5	5601	16	0	0
T6	3861	0	0	0
T7	1988	0	0	0
T8	2874	0	0	0
T9	1969	0	0	0
T10	6230	0	0	0
T11	3468	0	0	0
T12	8032	0	0	0
T13	5500	0	0	0
T14	1539	0	0	0
T41	0	125	0	0
T42	0	23	0	0
T50	0	126	0	0
T52	0	213	0	0
T60	0	9	0	0
T93	0	4	0	0
T97	0	34	0	0
T98	0	10	0	0
T113	0	22	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11653439	8297	0	0
T5	5601	4	0	0
T6	3861	0	0	0
T7	1988	0	0	0
T8	2874	0	0	0
T9	1969	0	0	0
T10	6230	0	0	0
T11	3468	0	0	0
T12	8032	0	0	0
T13	5500	0	0	0
T14	1539	0	0	0
T41	0	128	0	0
T42	0	17	0	0
T50	0	126	0	0
T52	0	238	0	0
T60	0	12	0	0
T93	0	8	0	0
T97	0	60	0	0
T98	0	13	0	0
T113	0	28	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11653439	8174	0	0
T5	5601	19	0	0
T6	3861	0	0	0
T7	1988	0	0	0
T8	2874	0	0	0
T9	1969	0	0	0
T10	6230	0	0	0
T11	3468	0	0	0
T12	8032	0	0	0
T13	5500	0	0	0
T14	1539	0	0	0
T41	0	114	0	0
T42	0	19	0	0
T50	0	145	0	0
T52	0	213	0	0
T60	0	18	0	0
T93	0	17	0	0
T97	0	72	0	0
T98	0	15	0	0
T113	0	32	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11653439	8107	0	0
T5	5601	18	0	0
T6	3861	0	0	0
T7	1988	0	0	0
T8	2874	0	0	0
T9	1969	0	0	0
T10	6230	0	0	0
T11	3468	0	0	0
T12	8032	0	0	0
T13	5500	0	0	0
T14	1539	0	0	0
T41	0	146	0	0
T42	0	31	0	0
T50	0	113	0	0
T52	0	194	0	0
T60	0	17	0	0
T93	0	19	0	0
T97	0	64	0	0
T98	0	13	0	0
T113	0	32	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11653439	8382	0	0
T5	5601	13	0	0
T6	3861	0	0	0
T7	1988	0	0	0
T8	2874	0	0	0
T9	1969	0	0	0
T10	6230	0	0	0
T11	3468	0	0	0
T12	8032	0	0	0
T13	5500	0	0	0
T14	1539	0	0	0
T41	0	149	0	0
T42	0	23	0	0
T50	0	102	0	0
T52	0	205	0	0
T60	0	18	0	0
T93	0	14	0	0
T97	0	84	0	0
T98	0	12	0	0
T113	0	39	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11653439	8316	0	0
T5	5601	2	0	0
T6	3861	0	0	0
T7	1988	0	0	0
T8	2874	0	0	0
T9	1969	0	0	0
T10	6230	0	0	0
T11	3468	0	0	0
T12	8032	0	0	0
T13	5500	0	0	0
T14	1539	0	0	0
T41	0	137	0	0
T42	0	22	0	0
T50	0	133	0	0
T52	0	222	0	0
T60	0	29	0	0
T93	0	10	0	0
T97	0	76	0	0
T98	0	16	0	0
T113	0	20	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11653439	8324	0	0
T5	5601	17	0	0
T6	3861	0	0	0
T7	1988	0	0	0
T8	2874	0	0	0
T9	1969	0	0	0
T10	6230	0	0	0
T11	3468	0	0	0
T12	8032	0	0	0
T13	5500	0	0	0
T14	1539	0	0	0
T41	0	135	0	0
T42	0	22	0	0
T50	0	161	0	0
T52	0	220	0	0
T60	0	12	0	0
T93	0	8	0	0
T97	0	77	0	0
T98	0	12	0	0
T113	0	26	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11653439	4494	0	0
T5	5601	4	0	0
T6	3861	0	0	0
T7	1988	0	0	0
T8	2874	0	0	0
T9	1969	0	0	0
T10	6230	0	0	0
T11	3468	0	0	0
T12	8032	0	0	0
T13	5500	0	0	0
T14	1539	0	0	0
T41	0	37	0	0
T43	0	2	0	0
T50	0	32	0	0
T52	0	117	0	0
T60	0	8	0	0
T97	0	39	0	0
T98	0	12	0	0
T113	0	29	0	0
T145	0	23	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11653439	4400	0	0
T5	5601	9	0	0
T6	3861	0	0	0
T7	1988	0	0	0
T8	2874	0	0	0
T9	1969	0	0	0
T10	6230	0	0	0
T11	3468	0	0	0
T12	8032	0	0	0
T13	5500	0	0	0
T14	1539	0	0	0
T41	0	38	0	0
T43	0	5	0	0
T50	0	22	0	0
T52	0	119	0	0
T60	0	5	0	0
T97	0	16	0	0
T98	0	3	0	0
T113	0	25	0	0
T145	0	29	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11653439	4684	0	0
T5	5601	10	0	0
T6	3861	0	0	0
T7	1988	0	0	0
T8	2874	0	0	0
T9	1969	0	0	0
T10	6230	0	0	0
T11	3468	0	0	0
T12	8032	0	0	0
T13	5500	0	0	0
T14	1539	0	0	0
T41	0	46	0	0
T43	0	7	0	0
T50	0	27	0	0
T52	0	110	0	0
T60	0	9	0	0
T93	0	2	0	0
T97	0	25	0	0
T98	0	16	0	0
T113	0	22	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11653439	4525	0	0
T5	5601	13	0	0
T6	3861	0	0	0
T7	1988	0	0	0
T8	2874	0	0	0
T9	1969	0	0	0
T10	6230	0	0	0
T11	3468	0	0	0
T12	8032	0	0	0
T13	5500	0	0	0
T14	1539	0	0	0
T41	0	31	0	0
T43	0	10	0	0
T50	0	29	0	0
T52	0	139	0	0
T60	0	9	0	0
T97	0	13	0	0
T98	0	13	0	0
T113	0	11	0	0
T145	0	27	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11653439	4540	0	0
T5	5601	6	0	0
T6	3861	0	0	0
T7	1988	0	0	0
T8	2874	0	0	0
T9	1969	0	0	0
T10	6230	0	0	0
T11	3468	0	0	0
T12	8032	0	0	0
T13	5500	0	0	0
T14	1539	0	0	0
T41	0	25	0	0
T43	0	8	0	0
T50	0	30	0	0
T52	0	105	0	0
T60	0	5	0	0
T93	0	10	0	0
T97	0	26	0	0
T98	0	9	0	0
T113	0	21	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11653439	4507	0	0
T5	5601	11	0	0
T6	3861	0	0	0
T7	1988	0	0	0
T8	2874	0	0	0
T9	1969	0	0	0
T10	6230	0	0	0
T11	3468	0	0	0
T12	8032	0	0	0
T13	5500	0	0	0
T14	1539	0	0	0
T41	0	33	0	0
T43	0	6	0	0
T50	0	21	0	0
T52	0	117	0	0
T60	0	4	0	0
T93	0	5	0	0
T97	0	23	0	0
T98	0	5	0	0
T113	0	24	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11653439	4547	0	0
T5	5601	4	0	0
T6	3861	0	0	0
T7	1988	0	0	0
T8	2874	0	0	0
T9	1969	0	0	0
T10	6230	0	0	0
T11	3468	0	0	0
T12	8032	0	0	0
T13	5500	0	0	0
T14	1539	0	0	0
T41	0	34	0	0
T43	0	11	0	0
T50	0	46	0	0
T52	0	117	0	0
T60	0	14	0	0
T93	0	8	0	0
T97	0	15	0	0
T98	0	16	0	0
T113	0	42	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11653439	4420	0	0
T5	5601	7	0	0
T6	3861	0	0	0
T7	1988	0	0	0
T8	2874	0	0	0
T9	1969	0	0	0
T10	6230	0	0	0
T11	3468	0	0	0
T12	8032	0	0	0
T13	5500	0	0	0
T14	1539	0	0	0
T41	0	28	0	0
T43	0	3	0	0
T50	0	31	0	0
T52	0	121	0	0
T60	0	5	0	0
T93	0	10	0	0
T97	0	19	0	0
T98	0	7	0	0
T113	0	35	0	0