Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : rstmgr_cnsty_chk
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rstmgr_cnsty_chk_0/rtl/rstmgr_cnsty_chk.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_rst_chk 82.35 82.35
tb.dut.u_daon_por.gen_rst_chk.u_rst_chk 100.00 100.00
tb.dut.u_daon_por_io.gen_rst_chk.u_rst_chk 100.00 100.00
tb.dut.u_daon_por_io_div2.gen_rst_chk.u_rst_chk 100.00 100.00
tb.dut.u_daon_por_io_div4.gen_rst_chk.u_rst_chk 100.00 100.00
tb.dut.u_daon_por_usb.gen_rst_chk.u_rst_chk 100.00 100.00
tb.dut.u_daon_lc.gen_rst_chk.u_rst_chk 100.00 100.00
tb.dut.u_d0_lc.gen_rst_chk.u_rst_chk 100.00 100.00
tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_rst_chk 100.00 100.00
tb.dut.u_daon_lc_aon.gen_rst_chk.u_rst_chk 100.00 100.00
tb.dut.u_daon_lc_io.gen_rst_chk.u_rst_chk 100.00 100.00
tb.dut.u_d0_lc_io.gen_rst_chk.u_rst_chk 100.00 100.00
tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_rst_chk 100.00 100.00
tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_rst_chk 100.00 100.00
tb.dut.u_daon_lc_usb.gen_rst_chk.u_rst_chk 100.00 100.00
tb.dut.u_d0_lc_usb.gen_rst_chk.u_rst_chk 100.00 100.00
tb.dut.u_d0_sys.gen_rst_chk.u_rst_chk 100.00 100.00
tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_rst_chk 100.00 100.00
tb.dut.u_d0_spi_device.gen_rst_chk.u_rst_chk 100.00 100.00
tb.dut.u_d0_spi_host0.gen_rst_chk.u_rst_chk 100.00 100.00
tb.dut.u_d0_spi_host1.gen_rst_chk.u_rst_chk 100.00 100.00
tb.dut.u_d0_usb.gen_rst_chk.u_rst_chk 100.00 100.00
tb.dut.u_d0_usb_aon.gen_rst_chk.u_rst_chk 100.00 100.00
tb.dut.u_d0_i2c0.gen_rst_chk.u_rst_chk 100.00 100.00
tb.dut.u_d0_i2c1.gen_rst_chk.u_rst_chk 100.00 100.00
tb.dut.u_d0_i2c2.gen_rst_chk.u_rst_chk 100.00 100.00



Module Instance : tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_rst_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
82.35 82.35


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
82.35 82.35


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_d0_lc_shadowed


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_daon_por.gen_rst_chk.u_rst_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_por


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_daon_por_io.gen_rst_chk.u_rst_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_por_io


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_daon_por_io_div2.gen_rst_chk.u_rst_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_por_io_div2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_daon_por_io_div4.gen_rst_chk.u_rst_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_por_io_div4


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_daon_por_usb.gen_rst_chk.u_rst_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_por_usb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_daon_lc.gen_rst_chk.u_rst_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_lc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_lc.gen_rst_chk.u_rst_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_d0_lc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_rst_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_lc_shadowed


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_daon_lc_aon.gen_rst_chk.u_rst_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_lc_aon


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_daon_lc_io.gen_rst_chk.u_rst_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_lc_io


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_lc_io.gen_rst_chk.u_rst_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_d0_lc_io


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_rst_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_lc_io_div2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_rst_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_d0_lc_io_div2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_daon_lc_usb.gen_rst_chk.u_rst_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_lc_usb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_lc_usb.gen_rst_chk.u_rst_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_d0_lc_usb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_sys.gen_rst_chk.u_rst_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_d0_sys


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_rst_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_sys_io_div4


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_spi_device.gen_rst_chk.u_rst_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 100.00 90.00 100.00 u_d0_spi_device


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_spi_host0.gen_rst_chk.u_rst_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 100.00 90.00 100.00 u_d0_spi_host0


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_spi_host1.gen_rst_chk.u_rst_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 100.00 90.00 100.00 u_d0_spi_host1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_usb.gen_rst_chk.u_rst_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 100.00 90.00 100.00 u_d0_usb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_usb_aon.gen_rst_chk.u_rst_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_d0_usb_aon


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_i2c0.gen_rst_chk.u_rst_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 100.00 90.00 100.00 u_d0_i2c0


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_i2c1.gen_rst_chk.u_rst_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 100.00 90.00 100.00 u_d0_i2c1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_d0_i2c2.gen_rst_chk.u_rst_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 100.00 90.00 100.00 u_d0_i2c2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : rstmgr_cnsty_chk
TotalCoveredPercent
Totals 10 10 100.00
Total Bits 20 20 100.00
Total Bits 0->1 10 10 100.00
Total Bits 1->0 10 10 100.00

Ports 10 10 100.00
Port Bits 20 20 100.00
Port Bits 0->1 10 10 100.00
Port Bits 1->0 10 10 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
child_clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
child_rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
child_chk_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
parent_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
sw_rst_req_i Yes Yes T21,T54,T26 Yes T21,T54,T26 INPUT
sw_rst_req_clr_o Yes Yes T21,T54,T26 Yes T21,T54,T26 OUTPUT
err_o Yes Yes T21,T80,T54 Yes T21,T80,T54 OUTPUT
fsm_err_o Yes Yes T61,T81,T82 Yes T61,T81,T82 OUTPUT

Toggle Coverage for Instance : tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_rst_chk
TotalCoveredPercent
Totals 9 7 77.78
Total Bits 17 14 82.35
Total Bits 0->1 9 7 77.78
Total Bits 1->0 8 7 87.50

Ports 9 7 77.78
Port Bits 17 14 82.35
Port Bits 0->1 9 7 77.78
Port Bits 1->0 8 7 87.50

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
child_clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
child_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
child_chk_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
parent_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
sw_rst_req_i Unreachable Unreachable Unreachable INPUT
sw_rst_req_clr_o No No No OUTPUT
err_o No Excluded No OUTPUT 1->0:VC_COV_UNR
fsm_err_o Yes Yes T61,T81,T82 Yes T61,T81,T82 OUTPUT

Toggle Coverage for Instance : tb.dut.u_daon_por.gen_rst_chk.u_rst_chk
TotalCoveredPercent
Totals 9 9 100.00
Total Bits 18 18 100.00
Total Bits 0->1 9 9 100.00
Total Bits 1->0 9 9 100.00

Ports 9 9 100.00
Port Bits 18 18 100.00
Port Bits 0->1 9 9 100.00
Port Bits 1->0 9 9 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
child_clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
child_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
child_chk_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
parent_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
sw_rst_req_i Unreachable Unreachable Unreachable INPUT
sw_rst_req_clr_o Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
err_o Yes Yes T21,T54,T26 Yes T21,T54,T26 OUTPUT
fsm_err_o Yes Yes T61,T81,T82 Yes T61,T81,T82 OUTPUT

Toggle Coverage for Instance : tb.dut.u_daon_por_io.gen_rst_chk.u_rst_chk
TotalCoveredPercent
Totals 9 9 100.00
Total Bits 18 18 100.00
Total Bits 0->1 9 9 100.00
Total Bits 1->0 9 9 100.00

Ports 9 9 100.00
Port Bits 18 18 100.00
Port Bits 0->1 9 9 100.00
Port Bits 1->0 9 9 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
child_clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
child_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
child_chk_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
parent_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
sw_rst_req_i Unreachable Unreachable Unreachable INPUT
sw_rst_req_clr_o Yes Yes T21,T54,T47 Yes T21,T54,T47 OUTPUT
err_o Yes Yes T21,T54,T26 Yes T21,T54,T26 OUTPUT
fsm_err_o Yes Yes T61,T81,T82 Yes T61,T81,T82 OUTPUT

Toggle Coverage for Instance : tb.dut.u_daon_por_io_div2.gen_rst_chk.u_rst_chk
TotalCoveredPercent
Totals 9 9 100.00
Total Bits 18 18 100.00
Total Bits 0->1 9 9 100.00
Total Bits 1->0 9 9 100.00

Ports 9 9 100.00
Port Bits 18 18 100.00
Port Bits 0->1 9 9 100.00
Port Bits 1->0 9 9 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
child_clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
child_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
child_chk_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
parent_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
sw_rst_req_i Unreachable Unreachable Unreachable INPUT
sw_rst_req_clr_o Yes Yes T21,T26,T45 Yes T21,T26,T45 OUTPUT
err_o Yes Yes T21,T54,T26 Yes T21,T54,T26 OUTPUT
fsm_err_o Yes Yes T61,T81,T82 Yes T61,T81,T82 OUTPUT

Toggle Coverage for Instance : tb.dut.u_daon_por_io_div4.gen_rst_chk.u_rst_chk
TotalCoveredPercent
Totals 9 9 100.00
Total Bits 18 18 100.00
Total Bits 0->1 9 9 100.00
Total Bits 1->0 9 9 100.00

Ports 9 9 100.00
Port Bits 18 18 100.00
Port Bits 0->1 9 9 100.00
Port Bits 1->0 9 9 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
child_clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
child_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
child_chk_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
parent_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
sw_rst_req_i Unreachable Unreachable Unreachable INPUT
sw_rst_req_clr_o Yes Yes T21,T54,T45 Yes T21,T54,T45 OUTPUT
err_o Yes Yes T21,T54,T26 Yes T21,T54,T26 OUTPUT
fsm_err_o Yes Yes T61,T81,T82 Yes T61,T81,T82 OUTPUT

Toggle Coverage for Instance : tb.dut.u_daon_por_usb.gen_rst_chk.u_rst_chk
TotalCoveredPercent
Totals 9 9 100.00
Total Bits 18 18 100.00
Total Bits 0->1 9 9 100.00
Total Bits 1->0 9 9 100.00

Ports 9 9 100.00
Port Bits 18 18 100.00
Port Bits 0->1 9 9 100.00
Port Bits 1->0 9 9 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
child_clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
child_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
child_chk_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
parent_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
sw_rst_req_i Unreachable Unreachable Unreachable INPUT
sw_rst_req_clr_o Yes Yes T54,T46,T65 Yes T54,T46,T65 OUTPUT
err_o Yes Yes T21,T54,T26 Yes T21,T54,T26 OUTPUT
fsm_err_o Yes Yes T61,T81,T82 Yes T61,T81,T82 OUTPUT

Toggle Coverage for Instance : tb.dut.u_daon_lc.gen_rst_chk.u_rst_chk
TotalCoveredPercent
Totals 9 9 100.00
Total Bits 18 18 100.00
Total Bits 0->1 9 9 100.00
Total Bits 1->0 9 9 100.00

Ports 9 9 100.00
Port Bits 18 18 100.00
Port Bits 0->1 9 9 100.00
Port Bits 1->0 9 9 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
child_clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
child_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
child_chk_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
parent_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
sw_rst_req_i Unreachable Unreachable Unreachable INPUT
sw_rst_req_clr_o Yes Yes T21,T54,T26 Yes T21,T54,T26 OUTPUT
err_o Yes Yes T21,T80,T54 Yes T21,T80,T54 OUTPUT
fsm_err_o Yes Yes T61,T81,T82 Yes T61,T81,T82 OUTPUT

Toggle Coverage for Instance : tb.dut.u_d0_lc.gen_rst_chk.u_rst_chk
TotalCoveredPercent
Totals 9 9 100.00
Total Bits 18 18 100.00
Total Bits 0->1 9 9 100.00
Total Bits 1->0 9 9 100.00

Ports 9 9 100.00
Port Bits 18 18 100.00
Port Bits 0->1 9 9 100.00
Port Bits 1->0 9 9 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
child_clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
child_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
child_chk_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
parent_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
sw_rst_req_i Unreachable Unreachable Unreachable INPUT
sw_rst_req_clr_o Yes Yes T54,T26,T45 Yes T54,T26,T45 OUTPUT
err_o Yes Yes T21,T54,T26 Yes T21,T54,T26 OUTPUT
fsm_err_o Yes Yes T61,T81,T82 Yes T61,T81,T82 OUTPUT

Toggle Coverage for Instance : tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_rst_chk
TotalCoveredPercent
Totals 9 9 100.00
Total Bits 18 18 100.00
Total Bits 0->1 9 9 100.00
Total Bits 1->0 9 9 100.00

Ports 9 9 100.00
Port Bits 18 18 100.00
Port Bits 0->1 9 9 100.00
Port Bits 1->0 9 9 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
child_clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
child_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
child_chk_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
parent_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
sw_rst_req_i Unreachable Unreachable Unreachable INPUT
sw_rst_req_clr_o Yes Yes T21,T26,T45 Yes T21,T26,T45 OUTPUT
err_o Yes Yes T21,T80,T54 Yes T21,T80,T54 OUTPUT
fsm_err_o Yes Yes T61,T81,T82 Yes T61,T81,T82 OUTPUT

Toggle Coverage for Instance : tb.dut.u_daon_lc_aon.gen_rst_chk.u_rst_chk
TotalCoveredPercent
Totals 9 9 100.00
Total Bits 18 18 100.00
Total Bits 0->1 9 9 100.00
Total Bits 1->0 9 9 100.00

Ports 9 9 100.00
Port Bits 18 18 100.00
Port Bits 0->1 9 9 100.00
Port Bits 1->0 9 9 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
child_clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
child_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
child_chk_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
parent_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
sw_rst_req_i Unreachable Unreachable Unreachable INPUT
sw_rst_req_clr_o Yes Yes T21,T54,T46 Yes T21,T54,T46 OUTPUT
err_o Yes Yes T21,T54,T26 Yes T21,T54,T26 OUTPUT
fsm_err_o Yes Yes T61,T81,T82 Yes T61,T81,T82 OUTPUT

Toggle Coverage for Instance : tb.dut.u_daon_lc_io.gen_rst_chk.u_rst_chk
TotalCoveredPercent
Totals 9 9 100.00
Total Bits 18 18 100.00
Total Bits 0->1 9 9 100.00
Total Bits 1->0 9 9 100.00

Ports 9 9 100.00
Port Bits 18 18 100.00
Port Bits 0->1 9 9 100.00
Port Bits 1->0 9 9 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
child_clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
child_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
child_chk_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
parent_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
sw_rst_req_i Unreachable Unreachable Unreachable INPUT
sw_rst_req_clr_o Yes Yes T21,T54,T26 Yes T21,T54,T26 OUTPUT
err_o Yes Yes T21,T54,T26 Yes T21,T54,T26 OUTPUT
fsm_err_o Yes Yes T61,T81,T82 Yes T61,T81,T82 OUTPUT

Toggle Coverage for Instance : tb.dut.u_d0_lc_io.gen_rst_chk.u_rst_chk
TotalCoveredPercent
Totals 9 9 100.00
Total Bits 18 18 100.00
Total Bits 0->1 9 9 100.00
Total Bits 1->0 9 9 100.00

Ports 9 9 100.00
Port Bits 18 18 100.00
Port Bits 0->1 9 9 100.00
Port Bits 1->0 9 9 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
child_clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
child_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
child_chk_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
parent_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
sw_rst_req_i Unreachable Unreachable Unreachable INPUT
sw_rst_req_clr_o Yes Yes T21,T54,T26 Yes T21,T54,T26 OUTPUT
err_o Yes Yes T21,T54,T26 Yes T21,T54,T26 OUTPUT
fsm_err_o Yes Yes T61,T81,T82 Yes T61,T81,T82 OUTPUT

Toggle Coverage for Instance : tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_rst_chk
TotalCoveredPercent
Totals 9 9 100.00
Total Bits 18 18 100.00
Total Bits 0->1 9 9 100.00
Total Bits 1->0 9 9 100.00

Ports 9 9 100.00
Port Bits 18 18 100.00
Port Bits 0->1 9 9 100.00
Port Bits 1->0 9 9 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
child_clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
child_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
child_chk_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
parent_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
sw_rst_req_i Unreachable Unreachable Unreachable INPUT
sw_rst_req_clr_o Yes Yes T21,T54,T65 Yes T21,T54,T65 OUTPUT
err_o Yes Yes T21,T54,T26 Yes T21,T54,T26 OUTPUT
fsm_err_o Yes Yes T61,T81,T82 Yes T61,T81,T82 OUTPUT

Toggle Coverage for Instance : tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_rst_chk
TotalCoveredPercent
Totals 9 9 100.00
Total Bits 18 18 100.00
Total Bits 0->1 9 9 100.00
Total Bits 1->0 9 9 100.00

Ports 9 9 100.00
Port Bits 18 18 100.00
Port Bits 0->1 9 9 100.00
Port Bits 1->0 9 9 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
child_clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
child_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
child_chk_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
parent_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
sw_rst_req_i Unreachable Unreachable Unreachable INPUT
sw_rst_req_clr_o Yes Yes T54,T45,T65 Yes T54,T45,T65 OUTPUT
err_o Yes Yes T21,T54,T26 Yes T21,T54,T26 OUTPUT
fsm_err_o Yes Yes T61,T81,T82 Yes T61,T81,T82 OUTPUT

Toggle Coverage for Instance : tb.dut.u_daon_lc_usb.gen_rst_chk.u_rst_chk
TotalCoveredPercent
Totals 9 9 100.00
Total Bits 18 18 100.00
Total Bits 0->1 9 9 100.00
Total Bits 1->0 9 9 100.00

Ports 9 9 100.00
Port Bits 18 18 100.00
Port Bits 0->1 9 9 100.00
Port Bits 1->0 9 9 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
child_clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
child_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
child_chk_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
parent_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
sw_rst_req_i Unreachable Unreachable Unreachable INPUT
sw_rst_req_clr_o Yes Yes T21,T54,T45 Yes T21,T54,T45 OUTPUT
err_o Yes Yes T21,T54,T26 Yes T21,T54,T26 OUTPUT
fsm_err_o Yes Yes T61,T81,T82 Yes T61,T81,T82 OUTPUT

Toggle Coverage for Instance : tb.dut.u_d0_lc_usb.gen_rst_chk.u_rst_chk
TotalCoveredPercent
Totals 9 9 100.00
Total Bits 18 18 100.00
Total Bits 0->1 9 9 100.00
Total Bits 1->0 9 9 100.00

Ports 9 9 100.00
Port Bits 18 18 100.00
Port Bits 0->1 9 9 100.00
Port Bits 1->0 9 9 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
child_clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
child_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
child_chk_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
parent_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
sw_rst_req_i Unreachable Unreachable Unreachable INPUT
sw_rst_req_clr_o Yes Yes T54,T65,T27 Yes T54,T65,T27 OUTPUT
err_o Yes Yes T21,T54,T26 Yes T21,T54,T26 OUTPUT
fsm_err_o Yes Yes T61,T81,T82 Yes T61,T81,T82 OUTPUT

Toggle Coverage for Instance : tb.dut.u_d0_sys.gen_rst_chk.u_rst_chk
TotalCoveredPercent
Totals 9 9 100.00
Total Bits 18 18 100.00
Total Bits 0->1 9 9 100.00
Total Bits 1->0 9 9 100.00

Ports 9 9 100.00
Port Bits 18 18 100.00
Port Bits 0->1 9 9 100.00
Port Bits 1->0 9 9 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
child_clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
child_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
child_chk_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
parent_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
sw_rst_req_i Unreachable Unreachable Unreachable INPUT
sw_rst_req_clr_o Yes Yes T45,T65,T27 Yes T45,T65,T27 OUTPUT
err_o Yes Yes T21,T54,T26 Yes T21,T54,T26 OUTPUT
fsm_err_o Yes Yes T61,T81,T82 Yes T61,T81,T82 OUTPUT

Toggle Coverage for Instance : tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_rst_chk
TotalCoveredPercent
Totals 9 9 100.00
Total Bits 18 18 100.00
Total Bits 0->1 9 9 100.00
Total Bits 1->0 9 9 100.00

Ports 9 9 100.00
Port Bits 18 18 100.00
Port Bits 0->1 9 9 100.00
Port Bits 1->0 9 9 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
child_clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
child_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
child_chk_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
parent_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
sw_rst_req_i Unreachable Unreachable Unreachable INPUT
sw_rst_req_clr_o Yes Yes T65,T28,T66 Yes T65,T28,T66 OUTPUT
err_o Yes Yes T21,T54,T26 Yes T21,T54,T26 OUTPUT
fsm_err_o Yes Yes T61,T81,T82 Yes T61,T81,T82 OUTPUT

Toggle Coverage for Instance : tb.dut.u_d0_spi_device.gen_rst_chk.u_rst_chk
TotalCoveredPercent
Totals 10 10 100.00
Total Bits 20 20 100.00
Total Bits 0->1 10 10 100.00
Total Bits 1->0 10 10 100.00

Ports 10 10 100.00
Port Bits 20 20 100.00
Port Bits 0->1 10 10 100.00
Port Bits 1->0 10 10 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
child_clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
child_rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
child_chk_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
parent_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
sw_rst_req_i Yes Yes T1,T10,T12 Yes T1,T10,T12 INPUT
sw_rst_req_clr_o Yes Yes T1,T10,T12 Yes T1,T10,T12 OUTPUT
err_o Yes Yes T21,T54,T26 Yes T21,T54,T26 OUTPUT
fsm_err_o Yes Yes T61,T81,T82 Yes T61,T81,T82 OUTPUT

Toggle Coverage for Instance : tb.dut.u_d0_spi_host0.gen_rst_chk.u_rst_chk
TotalCoveredPercent
Totals 10 10 100.00
Total Bits 20 20 100.00
Total Bits 0->1 10 10 100.00
Total Bits 1->0 10 10 100.00

Ports 10 10 100.00
Port Bits 20 20 100.00
Port Bits 0->1 10 10 100.00
Port Bits 1->0 10 10 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
child_clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
child_rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
child_chk_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
parent_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
sw_rst_req_i Yes Yes T1,T10,T12 Yes T1,T10,T12 INPUT
sw_rst_req_clr_o Yes Yes T1,T10,T12 Yes T1,T10,T12 OUTPUT
err_o Yes Yes T21,T54,T26 Yes T21,T54,T26 OUTPUT
fsm_err_o Yes Yes T61,T81,T82 Yes T61,T81,T82 OUTPUT

Toggle Coverage for Instance : tb.dut.u_d0_spi_host1.gen_rst_chk.u_rst_chk
TotalCoveredPercent
Totals 10 10 100.00
Total Bits 20 20 100.00
Total Bits 0->1 10 10 100.00
Total Bits 1->0 10 10 100.00

Ports 10 10 100.00
Port Bits 20 20 100.00
Port Bits 0->1 10 10 100.00
Port Bits 1->0 10 10 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
child_clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
child_rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
child_chk_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
parent_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
sw_rst_req_i Yes Yes T1,T10,T12 Yes T1,T10,T12 INPUT
sw_rst_req_clr_o Yes Yes T1,T10,T12 Yes T1,T10,T12 OUTPUT
err_o Yes Yes T21,T54,T26 Yes T21,T54,T26 OUTPUT
fsm_err_o Yes Yes T61,T81,T82 Yes T61,T81,T82 OUTPUT

Toggle Coverage for Instance : tb.dut.u_d0_usb.gen_rst_chk.u_rst_chk
TotalCoveredPercent
Totals 10 10 100.00
Total Bits 20 20 100.00
Total Bits 0->1 10 10 100.00
Total Bits 1->0 10 10 100.00

Ports 10 10 100.00
Port Bits 20 20 100.00
Port Bits 0->1 10 10 100.00
Port Bits 1->0 10 10 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
child_clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
child_rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
child_chk_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
parent_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
sw_rst_req_i Yes Yes T1,T10,T12 Yes T1,T10,T12 INPUT
sw_rst_req_clr_o Yes Yes T1,T10,T12 Yes T1,T10,T12 OUTPUT
err_o Yes Yes T21,T54,T26 Yes T21,T54,T26 OUTPUT
fsm_err_o Yes Yes T61,T81,T82 Yes T61,T81,T82 OUTPUT

Toggle Coverage for Instance : tb.dut.u_d0_usb_aon.gen_rst_chk.u_rst_chk
TotalCoveredPercent
Totals 10 10 100.00
Total Bits 20 20 100.00
Total Bits 0->1 10 10 100.00
Total Bits 1->0 10 10 100.00

Ports 10 10 100.00
Port Bits 20 20 100.00
Port Bits 0->1 10 10 100.00
Port Bits 1->0 10 10 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
child_clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
child_rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
child_chk_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
parent_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
sw_rst_req_i Yes Yes T1,T10,T12 Yes T1,T10,T12 INPUT
sw_rst_req_clr_o Yes Yes T1,T10,T12 Yes T1,T10,T12 OUTPUT
err_o Yes Yes T21,T54,T26 Yes T21,T54,T26 OUTPUT
fsm_err_o Yes Yes T61,T81,T82 Yes T61,T81,T82 OUTPUT

Toggle Coverage for Instance : tb.dut.u_d0_i2c0.gen_rst_chk.u_rst_chk
TotalCoveredPercent
Totals 10 10 100.00
Total Bits 20 20 100.00
Total Bits 0->1 10 10 100.00
Total Bits 1->0 10 10 100.00

Ports 10 10 100.00
Port Bits 20 20 100.00
Port Bits 0->1 10 10 100.00
Port Bits 1->0 10 10 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
child_clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
child_rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
child_chk_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
parent_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
sw_rst_req_i Yes Yes T1,T10,T12 Yes T1,T10,T12 INPUT
sw_rst_req_clr_o Yes Yes T1,T10,T12 Yes T1,T10,T12 OUTPUT
err_o Yes Yes T21,T54,T26 Yes T21,T54,T26 OUTPUT
fsm_err_o Yes Yes T61,T81,T82 Yes T61,T81,T82 OUTPUT

Toggle Coverage for Instance : tb.dut.u_d0_i2c1.gen_rst_chk.u_rst_chk
TotalCoveredPercent
Totals 10 10 100.00
Total Bits 20 20 100.00
Total Bits 0->1 10 10 100.00
Total Bits 1->0 10 10 100.00

Ports 10 10 100.00
Port Bits 20 20 100.00
Port Bits 0->1 10 10 100.00
Port Bits 1->0 10 10 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
child_clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
child_rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
child_chk_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
parent_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
sw_rst_req_i Yes Yes T1,T10,T12 Yes T1,T10,T12 INPUT
sw_rst_req_clr_o Yes Yes T1,T10,T12 Yes T1,T10,T12 OUTPUT
err_o Yes Yes T21,T54,T26 Yes T21,T54,T26 OUTPUT
fsm_err_o Yes Yes T61,T81,T82 Yes T61,T81,T82 OUTPUT

Toggle Coverage for Instance : tb.dut.u_d0_i2c2.gen_rst_chk.u_rst_chk
TotalCoveredPercent
Totals 10 10 100.00
Total Bits 20 20 100.00
Total Bits 0->1 10 10 100.00
Total Bits 1->0 10 10 100.00

Ports 10 10 100.00
Port Bits 20 20 100.00
Port Bits 0->1 10 10 100.00
Port Bits 1->0 10 10 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
child_clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
child_rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
child_chk_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
parent_rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
sw_rst_req_i Yes Yes T1,T10,T12 Yes T1,T10,T12 INPUT
sw_rst_req_clr_o Yes Yes T1,T10,T12 Yes T1,T10,T12 OUTPUT
err_o Yes Yes T21,T54,T26 Yes T21,T54,T26 OUTPUT
fsm_err_o Yes Yes T61,T81,T82 Yes T61,T81,T82 OUTPUT

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%