Line Coverage for Module :
pwrmgr_rstmgr_sva_if
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
ALWAYS | 33 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
33 |
1 |
1 |
Cond Coverage for Module :
pwrmgr_rstmgr_sva_if
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (((!rst_slow_ni)) || disable_sva)
--------1------- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T2,T3,T4 |
Assert Coverage for Module :
pwrmgr_rstmgr_sva_if
Assertion Details
gen_assertions_per_power_domains[0].LcHandshakeOff_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10907855 |
12504 |
0 |
0 |
T2 |
15819 |
34 |
0 |
0 |
T3 |
2098 |
4 |
0 |
0 |
T4 |
2681 |
0 |
0 |
0 |
T5 |
5601 |
4 |
0 |
0 |
T6 |
3861 |
4 |
0 |
0 |
T7 |
1988 |
0 |
0 |
0 |
T8 |
2874 |
0 |
0 |
0 |
T9 |
1969 |
0 |
0 |
0 |
T10 |
6230 |
0 |
0 |
0 |
T11 |
3468 |
0 |
0 |
0 |
T14 |
0 |
5 |
0 |
0 |
T21 |
0 |
75 |
0 |
0 |
T22 |
0 |
4 |
0 |
0 |
T23 |
0 |
4 |
0 |
0 |
T24 |
0 |
43 |
0 |
0 |
T25 |
0 |
11 |
0 |
0 |
gen_assertions_per_power_domains[0].LcHandshakeOn_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10907855 |
115367 |
0 |
0 |
T2 |
15819 |
317 |
0 |
0 |
T3 |
2098 |
37 |
0 |
0 |
T4 |
2681 |
0 |
0 |
0 |
T5 |
5601 |
38 |
0 |
0 |
T6 |
3861 |
38 |
0 |
0 |
T7 |
1988 |
0 |
0 |
0 |
T8 |
2874 |
0 |
0 |
0 |
T9 |
1969 |
0 |
0 |
0 |
T10 |
6230 |
0 |
0 |
0 |
T11 |
3468 |
0 |
0 |
0 |
T14 |
0 |
45 |
0 |
0 |
T21 |
0 |
703 |
0 |
0 |
T22 |
0 |
38 |
0 |
0 |
T23 |
0 |
38 |
0 |
0 |
T24 |
0 |
391 |
0 |
0 |
T25 |
0 |
99 |
0 |
0 |
gen_assertions_per_power_domains[0].SysHandshakeOff_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10907855 |
6224661 |
0 |
0 |
T1 |
5241 |
4666 |
0 |
0 |
T2 |
15819 |
7307 |
0 |
0 |
T3 |
2098 |
1128 |
0 |
0 |
T4 |
2681 |
892 |
0 |
0 |
T5 |
5601 |
4640 |
0 |
0 |
T6 |
3861 |
2877 |
0 |
0 |
T7 |
1988 |
1398 |
0 |
0 |
T8 |
2874 |
640 |
0 |
0 |
T9 |
1969 |
1398 |
0 |
0 |
T10 |
6230 |
5617 |
0 |
0 |
gen_assertions_per_power_domains[0].SysHandshakeOn_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10907855 |
183722 |
0 |
0 |
T2 |
15819 |
488 |
0 |
0 |
T3 |
2098 |
62 |
0 |
0 |
T4 |
2681 |
0 |
0 |
0 |
T5 |
5601 |
60 |
0 |
0 |
T6 |
3861 |
59 |
0 |
0 |
T7 |
1988 |
0 |
0 |
0 |
T8 |
2874 |
0 |
0 |
0 |
T9 |
1969 |
0 |
0 |
0 |
T10 |
6230 |
0 |
0 |
0 |
T11 |
3468 |
0 |
0 |
0 |
T14 |
0 |
78 |
0 |
0 |
T21 |
0 |
1101 |
0 |
0 |
T22 |
0 |
64 |
0 |
0 |
T23 |
0 |
64 |
0 |
0 |
T24 |
0 |
629 |
0 |
0 |
T25 |
0 |
151 |
0 |
0 |
gen_assertions_per_power_domains[1].LcHandshakeOff_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10907855 |
12504 |
0 |
0 |
T2 |
15819 |
34 |
0 |
0 |
T3 |
2098 |
4 |
0 |
0 |
T4 |
2681 |
0 |
0 |
0 |
T5 |
5601 |
4 |
0 |
0 |
T6 |
3861 |
4 |
0 |
0 |
T7 |
1988 |
0 |
0 |
0 |
T8 |
2874 |
0 |
0 |
0 |
T9 |
1969 |
0 |
0 |
0 |
T10 |
6230 |
0 |
0 |
0 |
T11 |
3468 |
0 |
0 |
0 |
T14 |
0 |
5 |
0 |
0 |
T21 |
0 |
75 |
0 |
0 |
T22 |
0 |
4 |
0 |
0 |
T23 |
0 |
4 |
0 |
0 |
T24 |
0 |
43 |
0 |
0 |
T25 |
0 |
11 |
0 |
0 |
gen_assertions_per_power_domains[1].LcHandshakeOn_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10907855 |
115367 |
0 |
0 |
T2 |
15819 |
317 |
0 |
0 |
T3 |
2098 |
37 |
0 |
0 |
T4 |
2681 |
0 |
0 |
0 |
T5 |
5601 |
38 |
0 |
0 |
T6 |
3861 |
38 |
0 |
0 |
T7 |
1988 |
0 |
0 |
0 |
T8 |
2874 |
0 |
0 |
0 |
T9 |
1969 |
0 |
0 |
0 |
T10 |
6230 |
0 |
0 |
0 |
T11 |
3468 |
0 |
0 |
0 |
T14 |
0 |
45 |
0 |
0 |
T21 |
0 |
703 |
0 |
0 |
T22 |
0 |
38 |
0 |
0 |
T23 |
0 |
38 |
0 |
0 |
T24 |
0 |
391 |
0 |
0 |
T25 |
0 |
99 |
0 |
0 |
gen_assertions_per_power_domains[1].SysHandshakeOff_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10907855 |
6224661 |
0 |
0 |
T1 |
5241 |
4666 |
0 |
0 |
T2 |
15819 |
7307 |
0 |
0 |
T3 |
2098 |
1128 |
0 |
0 |
T4 |
2681 |
892 |
0 |
0 |
T5 |
5601 |
4640 |
0 |
0 |
T6 |
3861 |
2877 |
0 |
0 |
T7 |
1988 |
1398 |
0 |
0 |
T8 |
2874 |
640 |
0 |
0 |
T9 |
1969 |
1398 |
0 |
0 |
T10 |
6230 |
5617 |
0 |
0 |
gen_assertions_per_power_domains[1].SysHandshakeOn_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10907855 |
183722 |
0 |
0 |
T2 |
15819 |
488 |
0 |
0 |
T3 |
2098 |
62 |
0 |
0 |
T4 |
2681 |
0 |
0 |
0 |
T5 |
5601 |
60 |
0 |
0 |
T6 |
3861 |
59 |
0 |
0 |
T7 |
1988 |
0 |
0 |
0 |
T8 |
2874 |
0 |
0 |
0 |
T9 |
1969 |
0 |
0 |
0 |
T10 |
6230 |
0 |
0 |
0 |
T11 |
3468 |
0 |
0 |
0 |
T14 |
0 |
78 |
0 |
0 |
T21 |
0 |
1101 |
0 |
0 |
T22 |
0 |
64 |
0 |
0 |
T23 |
0 |
64 |
0 |
0 |
T24 |
0 |
629 |
0 |
0 |
T25 |
0 |
151 |
0 |
0 |