Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T5
0	1	Covered	T3,T5,T23
1	0	Covered	T2,T24,T51

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T8
1	0	Covered	T2,T3,T5
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	51453055	8639	0	0
CascadeEffAonToRstPorAboveRise_A	51453055	8639	0	0
CascadeEffAonToRstPorIoAboveFall_A	49394234	8639	0	0
CascadeEffAonToRstPorIoAboveRise_A	49394234	8639	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	24697834	8639	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	24697834	8639	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	12348402	8639	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	12348402	8639	0	0
CascadeEffAonToRstPorUcbAboveFall_A	24697893	8639	0	0
CascadeEffAonToRstPorUcbAboveRise_A	24697893	8639	0	0
CascadeLcToLcAboveFall_A	51453055	21143	0	0
CascadeLcToLcAboveRise_A	51453055	21143	0	0
CascadeLcToLcAonAboveFall_A	1558611	21143	0	0
CascadeLcToLcAonAboveRise_A	1558611	21143	0	0
CascadeLcToLcShadowedAboveFall_A	51453055	21143	0	0
CascadeLcToLcShadowedAboveRise_A	51453055	21143	0	0
CascadePorToAonAboveFall_A	1558611	6961	0	0
CascadeSysToSysAboveFall_A	51453055	21143	0	0
CascadeSysToSysAboveRise_A	51453055	21143	0	0
ScanRstToAonRise_A	1558611	204	0	0
StablePorToAonRise_A	1558611	8639	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	10907855	21143	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	10907855	21143	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	10907855	21143	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	10907855	21143	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	12348402	21143	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	12348402	21143	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	10907855	21143	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	10907855	21143	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	10907855	21143	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	10907855	21143	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51453055	8639	0	0
T1	22219	1	0	0
T2	85541	18	0	0
T3	9759	2	0	0
T4	11751	2	0	0
T5	24144	2	0	0
T6	17104	2	0	0
T7	8563	1	0	0
T8	12155	2	0	0
T9	8585	1	0	0
T10	26143	1	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51453055	8639	0	0
T1	22219	1	0	0
T2	85541	18	0	0
T3	9759	2	0	0
T4	11751	2	0	0
T5	24144	2	0	0
T6	17104	2	0	0
T7	8563	1	0	0
T8	12155	2	0	0
T9	8585	1	0	0
T10	26143	1	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49394234	8639	0	0
T1	21328	1	0	0
T2	82133	18	0	0
T3	9357	2	0	0
T4	11280	2	0	0
T5	23180	2	0	0
T6	16421	2	0	0
T7	8221	1	0	0
T8	11669	2	0	0
T9	8242	1	0	0
T10	25094	1	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49394234	8639	0	0
T1	21328	1	0	0
T2	82133	18	0	0
T3	9357	2	0	0
T4	11280	2	0	0
T5	23180	2	0	0
T6	16421	2	0	0
T7	8221	1	0	0
T8	11669	2	0	0
T9	8242	1	0	0
T10	25094	1	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24697834	8639	0	0
T1	10664	1	0	0
T2	41063	18	0	0
T3	4679	2	0	0
T4	5640	2	0	0
T5	11587	2	0	0
T6	8208	2	0	0
T7	4109	1	0	0
T8	5834	2	0	0
T9	4120	1	0	0
T10	12546	1	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24697834	8639	0	0
T1	10664	1	0	0
T2	41063	18	0	0
T3	4679	2	0	0
T4	5640	2	0	0
T5	11587	2	0	0
T6	8208	2	0	0
T7	4109	1	0	0
T8	5834	2	0	0
T9	4120	1	0	0
T10	12546	1	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12348402	8639	0	0
T1	5332	1	0	0
T2	20532	18	0	0
T3	2339	2	0	0
T4	2819	2	0	0
T5	5793	2	0	0
T6	4103	2	0	0
T7	2053	1	0	0
T8	2916	2	0	0
T9	2059	1	0	0
T10	6272	1	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12348402	8639	0	0
T1	5332	1	0	0
T2	20532	18	0	0
T3	2339	2	0	0
T4	2819	2	0	0
T5	5793	2	0	0
T6	4103	2	0	0
T7	2053	1	0	0
T8	2916	2	0	0
T9	2059	1	0	0
T10	6272	1	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24697893	8639	0	0
T1	10663	1	0	0
T2	41068	18	0	0
T3	4683	2	0	0
T4	5640	2	0	0
T5	11588	2	0	0
T6	8209	2	0	0
T7	4109	1	0	0
T8	5834	2	0	0
T9	4120	1	0	0
T10	12547	1	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24697893	8639	0	0
T1	10663	1	0	0
T2	41068	18	0	0
T3	4683	2	0	0
T4	5640	2	0	0
T5	11588	2	0	0
T6	8209	2	0	0
T7	4109	1	0	0
T8	5834	2	0	0
T9	4120	1	0	0
T10	12547	1	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51453055	21143	0	0
T1	22219	1	0	0
T2	85541	52	0	0
T3	9759	6	0	0
T4	11751	2	0	0
T5	24144	6	0	0
T6	17104	6	0	0
T7	8563	1	0	0
T8	12155	2	0	0
T9	8585	1	0	0
T10	26143	1	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51453055	21143	0	0
T1	22219	1	0	0
T2	85541	52	0	0
T3	9759	6	0	0
T4	11751	2	0	0
T5	24144	6	0	0
T6	17104	6	0	0
T7	8563	1	0	0
T8	12155	2	0	0
T9	8585	1	0	0
T10	26143	1	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1558611	21143	0	0
T1	665	1	0	0
T2	2655	52	0	0
T3	290	6	0	0
T4	352	2	0	0
T5	724	6	0	0
T6	511	6	0	0
T7	256	1	0	0
T8	363	2	0	0
T9	256	1	0	0
T10	784	1	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1558611	21143	0	0
T1	665	1	0	0
T2	2655	52	0	0
T3	290	6	0	0
T4	352	2	0	0
T5	724	6	0	0
T6	511	6	0	0
T7	256	1	0	0
T8	363	2	0	0
T9	256	1	0	0
T10	784	1	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51453055	21143	0	0
T1	22219	1	0	0
T2	85541	52	0	0
T3	9759	6	0	0
T4	11751	2	0	0
T5	24144	6	0	0
T6	17104	6	0	0
T7	8563	1	0	0
T8	12155	2	0	0
T9	8585	1	0	0
T10	26143	1	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51453055	21143	0	0
T1	22219	1	0	0
T2	85541	52	0	0
T3	9759	6	0	0
T4	11751	2	0	0
T5	24144	6	0	0
T6	17104	6	0	0
T7	8563	1	0	0
T8	12155	2	0	0
T9	8585	1	0	0
T10	26143	1	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1558611	6961	0	0
T1	665	1	0	0
T2	2655	10	0	0
T3	290	1	0	0
T4	352	7	0	0
T5	724	1	0	0
T6	511	1	0	0
T7	256	1	0	0
T8	363	7	0	0
T9	256	1	0	0
T10	784	1	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51453055	21143	0	0
T1	22219	1	0	0
T2	85541	52	0	0
T3	9759	6	0	0
T4	11751	2	0	0
T5	24144	6	0	0
T6	17104	6	0	0
T7	8563	1	0	0
T8	12155	2	0	0
T9	8585	1	0	0
T10	26143	1	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51453055	21143	0	0
T1	22219	1	0	0
T2	85541	52	0	0
T3	9759	6	0	0
T4	11751	2	0	0
T5	24144	6	0	0
T6	17104	6	0	0
T7	8563	1	0	0
T8	12155	2	0	0
T9	8585	1	0	0
T10	26143	1	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1558611	204	0	0
T3	290	1	0	0
T4	352	0	0	0
T5	724	0	0	0
T6	511	0	0	0
T7	256	0	0	0
T8	363	0	0	0
T9	256	0	0	0
T10	784	0	0	0
T11	444	0	0	0
T12	1005	0	0	0
T24	0	2	0	0
T51	0	2	0	0
T52	0	3	0	0
T113	0	1	0	0
T114	0	5	0	0
T116	0	1	0	0
T117	0	6	0	0
T146	0	1	0	0
T147	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1558611	8639	0	0
T1	665	1	0	0
T2	2655	18	0	0
T3	290	2	0	0
T4	352	2	0	0
T5	724	2	0	0
T6	511	2	0	0
T7	256	1	0	0
T8	363	2	0	0
T9	256	1	0	0
T10	784	1	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10907855	21143	0	0
T1	5241	1	0	0
T2	15819	52	0	0
T3	2098	6	0	0
T4	2681	2	0	0
T5	5601	6	0	0
T6	3861	6	0	0
T7	1988	1	0	0
T8	2874	2	0	0
T9	1969	1	0	0
T10	6230	1	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10907855	21143	0	0
T1	5241	1	0	0
T2	15819	52	0	0
T3	2098	6	0	0
T4	2681	2	0	0
T5	5601	6	0	0
T6	3861	6	0	0
T7	1988	1	0	0
T8	2874	2	0	0
T9	1969	1	0	0
T10	6230	1	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10907855	21143	0	0
T1	5241	1	0	0
T2	15819	52	0	0
T3	2098	6	0	0
T4	2681	2	0	0
T5	5601	6	0	0
T6	3861	6	0	0
T7	1988	1	0	0
T8	2874	2	0	0
T9	1969	1	0	0
T10	6230	1	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10907855	21143	0	0
T1	5241	1	0	0
T2	15819	52	0	0
T3	2098	6	0	0
T4	2681	2	0	0
T5	5601	6	0	0
T6	3861	6	0	0
T7	1988	1	0	0
T8	2874	2	0	0
T9	1969	1	0	0
T10	6230	1	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12348402	21143	0	0
T1	5332	1	0	0
T2	20532	52	0	0
T3	2339	6	0	0
T4	2819	2	0	0
T5	5793	6	0	0
T6	4103	6	0	0
T7	2053	1	0	0
T8	2916	2	0	0
T9	2059	1	0	0
T10	6272	1	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12348402	21143	0	0
T1	5332	1	0	0
T2	20532	52	0	0
T3	2339	6	0	0
T4	2819	2	0	0
T5	5793	6	0	0
T6	4103	6	0	0
T7	2053	1	0	0
T8	2916	2	0	0
T9	2059	1	0	0
T10	6272	1	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10907855	21143	0	0
T1	5241	1	0	0
T2	15819	52	0	0
T3	2098	6	0	0
T4	2681	2	0	0
T5	5601	6	0	0
T6	3861	6	0	0
T7	1988	1	0	0
T8	2874	2	0	0
T9	1969	1	0	0
T10	6230	1	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10907855	21143	0	0
T1	5241	1	0	0
T2	15819	52	0	0
T3	2098	6	0	0
T4	2681	2	0	0
T5	5601	6	0	0
T6	3861	6	0	0
T7	1988	1	0	0
T8	2874	2	0	0
T9	1969	1	0	0
T10	6230	1	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10907855	21143	0	0
T1	5241	1	0	0
T2	15819	52	0	0
T3	2098	6	0	0
T4	2681	2	0	0
T5	5601	6	0	0
T6	3861	6	0	0
T7	1988	1	0	0
T8	2874	2	0	0
T9	1969	1	0	0
T10	6230	1	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10907855	21143	0	0
T1	5241	1	0	0
T2	15819	52	0	0
T3	2098	6	0	0
T4	2681	2	0	0
T5	5601	6	0	0
T6	3861	6	0	0
T7	1988	1	0	0
T8	2874	2	0	0
T9	1969	1	0	0
T10	6230	1	0	0