Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7772

1

T1

18

T4

20

T12

74

auto[1]

10753

1

T1

83

T3

4

T4

81

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5770	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6236	1			T1	27		T2	1		T3	2
reset_info_cp[2]	2829	1			T1	14		T3	1		T4	15
reset_info_cp[4]	3731	1			T1	19		T3	1		T4	16
reset_info_cp[8]	111	1			T12	1		T21	1		T62	2
reset_info_cp[16]	120	1			T8	1		T12	2		T56	1
reset_info_cp[32]	127	1			T20	1		T59	1		T24	3
reset_info_cp[64]	116	1			T1	1		T7	1		T12	1
reset_info_cp[128]	105	1			T3	1		T22	1		T62	2

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	2993	1			T1	18		T4	20		T12	30
reset_info_cp[1]	auto[1]	2623	1			T1	8		T3	1		T4	6
reset_info_cp[2]	auto[0]	848	1			T12	8		T21	3		T56	3
reset_info_cp[2]	auto[1]	1981	1			T1	14		T3	1		T4	15
reset_info_cp[4]	auto[0]	1315	1			T12	12		T21	12		T56	5
reset_info_cp[4]	auto[1]	2416	1			T1	19		T3	1		T4	16
reset_info_cp[8]	auto[0]	42	1			T12	1		T62	2		T67	2
reset_info_cp[8]	auto[1]	69	1			T21	1		T63	1		T125	1
reset_info_cp[16]	auto[0]	61	1			T12	1		T63	1		T91	3
reset_info_cp[16]	auto[1]	59	1			T8	1		T12	1		T56	1
reset_info_cp[32]	auto[0]	47	1			T59	1		T125	2		T93	1
reset_info_cp[32]	auto[1]	80	1			T20	1		T24	3		T124	1
reset_info_cp[64]	auto[0]	51	1			T22	1		T56	1		T62	2
reset_info_cp[64]	auto[1]	65	1			T1	1		T7	1		T12	1
reset_info_cp[128]	auto[0]	50	1			T22	1		T62	2		T59	1
reset_info_cp[128]	auto[1]	55	1			T3	1		T63	1		T91	1