Assertions
dashboard | hierarchy | modlist | groups | tests | asserts

Assertions by Category
ASSERTPROPERTIESSEQUENCES
Total733010
Category 0733010


Assertions by Severity
ASSERTPROPERTIESSEQUENCES
Total733010
Severity 0733010


Summary for Assertions
NUMBERPERCENT
Total Number733100.00
Uncovered40.55
Success72999.45
Failure00.00
Incomplete00.00
Without Attempts00.00


Summary for Cover Sequences
NUMBERPERCENT
Total Number10100.00
Uncovered00.00
All Matches10100.00
First Matches10100.00


Detail Report for Assertions

Assertions Uncovered:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorAonEnTracksRstPorAonActive_A 001589507000
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorEnTracksRstPorInactive_A 0052474987000
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoDiv4EnTracksRstPorIoDiv4Active_A 0012593550000
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoEnTracksRstPorIoInactive_A 0050374123000

Assertions Success:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
tb.dut.AlertsKnownO_A 0011229889646453900
tb.dut.FpvSecCmRegWeOnehotCheck_A 00112298898000
tb.dut.ParameterMatch_A 0050550500
tb.dut.PwrKnownO_A 0011229889646453900
tb.dut.ResetsKnownO_A 0011229889646453900
tb.dut.RstEnKnownO_A 0011229889646453900
tb.dut.TlAReadyKnownO_A 0011229889646453900
tb.dut.TlDValidKnownO_A 0011229889646453900
tb.dut.gen_d0_i2c0_assert.FpvSecCmD0I2c0FsmCheck_A 00112298898000
tb.dut.gen_d0_i2c1_assert.FpvSecCmD0I2c1FsmCheck_A 00112298898000
tb.dut.gen_d0_i2c2_assert.FpvSecCmD0I2c2FsmCheck_A 00112298898000
tb.dut.gen_d0_lc_assert.FpvSecCmD0LcFsmCheck_A 00112298898000
tb.dut.gen_d0_lc_io_assert.FpvSecCmD0LcIoFsmCheck_A 00112298898000
tb.dut.gen_d0_lc_io_div2_assert.FpvSecCmD0LcIoDiv2FsmCheck_A 00112298898000
tb.dut.gen_d0_lc_shadowed_assert.FpvSecCmD0LcShadowedFsmCheck_A 00112298898000
tb.dut.gen_d0_lc_usb_assert.FpvSecCmD0LcUsbFsmCheck_A 00112298898000
tb.dut.gen_d0_spi_device_assert.FpvSecCmD0SpiDeviceFsmCheck_A 00112298898000
tb.dut.gen_d0_spi_host0_assert.FpvSecCmD0SpiHost0FsmCheck_A 00112298898000
tb.dut.gen_d0_spi_host1_assert.FpvSecCmD0SpiHost1FsmCheck_A 00112298898000
tb.dut.gen_d0_sys_assert.FpvSecCmD0SysFsmCheck_A 00112298898000
tb.dut.gen_d0_usb_aon_assert.FpvSecCmD0UsbAonFsmCheck_A 00112298898000
tb.dut.gen_d0_usb_assert.FpvSecCmD0UsbFsmCheck_A 00112298898000
tb.dut.gen_daon_lc_aon_assert.FpvSecCmDAonLcAonFsmCheck_A 00112298898000
tb.dut.gen_daon_lc_assert.FpvSecCmDAonLcFsmCheck_A 00112298898000
tb.dut.gen_daon_lc_io_assert.FpvSecCmDAonLcIoFsmCheck_A 00112298898000
tb.dut.gen_daon_lc_io_div2_assert.FpvSecCmDAonLcIoDiv2FsmCheck_A 00112298898000
tb.dut.gen_daon_lc_shadowed_assert.FpvSecCmDAonLcShadowedFsmCheck_A 00112298898000
tb.dut.gen_daon_lc_usb_assert.FpvSecCmDAonLcUsbFsmCheck_A 00112298898000
tb.dut.gen_daon_por_assert.FpvSecCmDAonPorFsmCheck_A 00112298898000
tb.dut.gen_daon_por_io_assert.FpvSecCmDAonPorIoFsmCheck_A 00112298898000
tb.dut.gen_daon_por_io_div2_assert.FpvSecCmDAonPorIoDiv2FsmCheck_A 00112298898000
tb.dut.gen_daon_por_io_div4_assert.FpvSecCmDAonPorIoDiv4FsmCheck_A 00112298898000
tb.dut.gen_daon_por_usb_assert.FpvSecCmDAonPorUsbFsmCheck_A 00112298898000
tb.dut.gen_daon_sys_io_div4_assert.FpvSecCmDAonSysIoDiv4FsmCheck_A 00112298898000
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_prim_mubi4_sender.OutputsKnown_A 00158950796054000
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic.selKnown0 008955845000
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic.selKnown1 002639213400
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic.selKnown0 008586808100
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic.selKnown1 002639213400
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic.selKnown0 006859635400
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic.selKnown1 002639213400
tb.dut.gen_rst_por_aon[0].u_por_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.gen_rst_por_aon[0].u_por_scanmode_sync.OutputsKnown_A 0011229889646453900
tb.dut.gen_rst_por_aon[0].u_por_scanmode_sync.gen_no_flops.OutputDelay_A 0011229889646453900
tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic.selKnown0 008586808100
tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic.selKnown1 002639213400
tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_prim_mubi4_sender.OutputsKnown_A 00158950794246900
tb.dut.gen_rst_por_aon[1].u_por_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.gen_rst_por_aon[1].u_por_scanmode_sync.OutputsKnown_A 0011229889646453900
tb.dut.gen_rst_por_aon[1].u_por_scanmode_sync.gen_no_flops.OutputDelay_A 0011229889646453900
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[0].LcHandshakeOff_A 00112298891261600
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[0].LcHandshakeOn_A 001122988911631100
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[0].SysHandshakeOff_A 0011229889650369700
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[0].SysHandshakeOn_A 001122988918590100
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[1].LcHandshakeOff_A 00112298891261600
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[1].LcHandshakeOn_A 001122988911631100
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[1].SysHandshakeOff_A 0011229889650369700
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[1].SysHandshakeOn_A 001122988918590100
tb.dut.rstmgr_attrs_sva_if.AlertInfoAttr_A 0050550500
tb.dut.rstmgr_attrs_sva_if.CpuInfoAttr_A 0050550500
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorAboveFall_A 0052474987858600
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorAboveRise_A 0052474987858600
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoAboveFall_A 0050374123858600
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoAboveRise_A 0050374123858600
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoDiv2AboveFall_A 0025187975858600
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoDiv2AboveRise_A 0025187975858600
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoDiv4AboveFall_A 0012593550858600
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoDiv4AboveRise_A 0012593550858600
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorUcbAboveFall_A 0025187702858600
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorUcbAboveRise_A 0025187702858600
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcAboveFall_A 00524749872120200
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcAboveRise_A 00524749872120200
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcAonAboveFall_A 0015895072120200
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcAonAboveRise_A 0015895072120200
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcShadowedAboveFall_A 00524749872120200
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcShadowedAboveRise_A 00524749872120200
tb.dut.rstmgr_cascading_sva_if.CascadePorToAonAboveFall_A 001589507687500
tb.dut.rstmgr_cascading_sva_if.CascadeSysToSysAboveFall_A 00524749872120200
tb.dut.rstmgr_cascading_sva_if.CascadeSysToSysAboveRise_A 00524749872120200
tb.dut.rstmgr_cascading_sva_if.ScanRstToAonRise_A 00158950719700
tb.dut.rstmgr_cascading_sva_if.StablePorToAonRise_A 001589507858600
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].CascadeLcToSysAboveFall_A 00112298892120200
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].CascadeLcToSysAboveRise_A 00112298892120200
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].CascadeLocalRstToLcAboveFall_A 00112298892120200
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].CascadeLocalRstToLcAboveRise_A 00112298892120200
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A 00125935502120200
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A 00125935502120200
tb.dut.rstmgr_cascading_sva_if.g_power_domains[1].CascadeLcToSysAboveFall_A 00112298892120200
tb.dut.rstmgr_cascading_sva_if.g_power_domains[1].CascadeLcToSysAboveRise_A 00112298892120200
tb.dut.rstmgr_cascading_sva_if.g_power_domains[1].CascadeLocalRstToLcAboveFall_A 00112298892120200
tb.dut.rstmgr_cascading_sva_if.g_power_domains[1].CascadeLocalRstToLcAboveRise_A 00112298892120200
tb.dut.rstmgr_csr_assert.TlulOOBAddrErr_A 0012008071823600
tb.dut.rstmgr_csr_assert.alert_regwen_rd_A 0012008071339100
tb.dut.rstmgr_csr_assert.cpu_regwen_rd_A 0012008071316000
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_0_rd_A 0012008071799300
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_1_rd_A 0012008071810000
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_2_rd_A 0012008071818100
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_3_rd_A 0012008071807700
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_4_rd_A 0012008071791900
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_5_rd_A 0012008071821900
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_6_rd_A 0012008071770200
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_7_rd_A 0012008071793600
tb.dut.rstmgr_csr_assert.sw_rst_regwen_0_rd_A 0012008071381000
tb.dut.rstmgr_csr_assert.sw_rst_regwen_1_rd_A 0012008071370900
tb.dut.rstmgr_csr_assert.sw_rst_regwen_2_rd_A 0012008071380000
tb.dut.rstmgr_csr_assert.sw_rst_regwen_3_rd_A 0012008071395900
tb.dut.rstmgr_csr_assert.sw_rst_regwen_4_rd_A 0012008071396900
tb.dut.rstmgr_csr_assert.sw_rst_regwen_5_rd_A 0012008071383200
tb.dut.rstmgr_csr_assert.sw_rst_regwen_6_rd_A 0012008071379200
tb.dut.rstmgr_csr_assert.sw_rst_regwen_7_rd_A 0012008071389600
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c0EnTracksRstI2c0Active_A 00125935501383000
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c0EnTracksRstI2c0Inactive_A 00125935502231000
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c1EnTracksRstI2c1Active_A 00125935501385600
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c1EnTracksRstI2c1Inactive_A 00125935502234300
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c2EnTracksRstI2c2Active_A 00125935501388100
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c2EnTracksRstI2c2Inactive_A 00125935502237500
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoDiv2EnTracksRstLcIoDiv2Active_A 00251879751269600
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoDiv2EnTracksRstLcIoDiv2Inactive_A 00251879752120200
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoDiv4ShadowedEnTracksRstLcIoDiv4ShadowedActive_A 00125935501271600
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoDiv4ShadowedEnTracksRstLcIoDiv4ShadowedInactive_A 00125935502125200
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoEnTracksRstLcIoActive_A 00503741231269200
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoEnTracksRstLcIoInactive_A 00503741232120200
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcShadowedEnTracksRstLcShadowedActive_A 00524749871266600
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcShadowedEnTracksRstLcShadowedInactive_A 00524749872120200
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcUsbEnTracksRstLcUsbActive_A 00251877021269000
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcUsbEnTracksRstLcUsbInactive_A 00251877022120200
tb.dut.rstmgr_rst_en_track_sva_if.D0RstPorAonEnTracksRstPorAonActive_A 0015895075000
tb.dut.rstmgr_rst_en_track_sva_if.D0RstPorAonEnTracksRstPorAonInactive_A 001589507856500
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiDeviceEnTracksRstSpiDeviceActive_A 00125935501360700
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiDeviceEnTracksRstSpiDeviceInactive_A 00125935502208100
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiHost0EnTracksRstSpiHost0Active_A 00503741231362900
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiHost0EnTracksRstSpiHost0Inactive_A 00503741232211600
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiHost1EnTracksRstSpiHost1Active_A 00251879751367700
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiHost1EnTracksRstSpiHost1Inactive_A 00251879752216100
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSysEnTracksRstSysActive_A 00524749871269000
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSysEnTracksRstSysInactive_A 00524749872120200
tb.dut.rstmgr_rst_en_track_sva_if.D0RstUsbAonEnTracksRstUsbAonActive_A 0015895071326100
tb.dut.rstmgr_rst_en_track_sva_if.D0RstUsbAonEnTracksRstUsbAonInactive_A 0015895072136200
tb.dut.rstmgr_rst_en_track_sva_if.D0RstUsbEnTracksRstUsbActive_A 00251877021368800
tb.dut.rstmgr_rst_en_track_sva_if.D0RstUsbEnTracksRstUsbInactive_A 00251877022217200
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcAonEnTracksRstLcAonActive_A 0015895071264200
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcAonEnTracksRstLcAonInactive_A 0015895072118100
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoDiv2EnTracksRstLcIoDiv2Active_A 00251879751263800
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoDiv2EnTracksRstLcIoDiv2Inactive_A 00251879752120200
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoDiv4ShadowedEnTracksRstLcIoDiv4ShadowedActive_A 00125935501266600
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoDiv4ShadowedEnTracksRstLcIoDiv4ShadowedInactive_A 00125935502125200
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoEnTracksRstLcIoActive_A 00503741231264000
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoEnTracksRstLcIoInactive_A 00503741232120200
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcShadowedEnTracksRstLcShadowedActive_A 00524749871269200
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcShadowedEnTracksRstLcShadowedInactive_A 00524749872125200
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcUsbEnTracksRstLcUsbActive_A 00251877021263900
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcUsbEnTracksRstLcUsbInactive_A 00251877022120200
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorAonEnTracksRstPorAonInactive_A 001589507858600
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorEnTracksRstPorActive_A 00524749872800
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoDiv2EnTracksRstPorIoDiv2Active_A 00251879752300
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoDiv2EnTracksRstPorIoDiv2Inactive_A 0025187975225900
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoDiv4EnTracksRstPorIoDiv4Inactive_A 0012593550858600
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoEnTracksRstPorIoActive_A 00503741233200
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorUsbEnTracksRstPorUsbActive_A 00251877023400
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorUsbEnTracksRstPorUsbInactive_A 0025187702225900
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstSysIoDiv4EnTracksRstSysIoDiv4Active_A 00125935501264400
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstSysIoDiv4EnTracksRstSysIoDiv4Inactive_A 00125935502120200
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[0].RstEnOff_A 00125935501349400
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[0].RstEnOn_A 0012593550105000
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[0].RstNOff_A 00125935501349400
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[0].RstNOn_A 0012593550105000
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[1].RstEnOff_A 00503741231224800
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[1].RstEnOn_A 005037412398500
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[1].RstNOff_A 00503741231224800
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[1].RstNOn_A 005037412398500
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[2].RstEnOff_A 00251879751229300
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[2].RstEnOn_A 002518797599300
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[2].RstNOff_A 00251879751229300
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[2].RstNOn_A 002518797599300
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[3].RstEnOff_A 00251877021230300
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[3].RstEnOn_A 0025187702100000
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[3].RstNOff_A 00251877021230300
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[3].RstNOn_A 0025187702100000
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[4].RstEnOff_A 0015895072095400
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[4].RstEnOn_A 001589507104000
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[4].RstNOff_A 0015895072095400
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[4].RstNOn_A 001589507104000
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[5].RstEnOff_A 00125935501372300
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[5].RstEnOn_A 0012593550113800
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[5].RstNOff_A 00125935501372300
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[5].RstNOn_A 0012593550113800
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[6].RstEnOff_A 00125935501375400
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[6].RstEnOn_A 0012593550116100
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[6].RstNOff_A 00125935501375400
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[6].RstNOn_A 0012593550116100
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[7].RstEnOff_A 00125935501378600
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[7].RstEnOn_A 0012593550119300
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[7].RstNOff_A 00125935501378600
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[7].RstNOn_A 0012593550119300
tb.dut.tlul_assert_device.aKnown_A 0012008071106279800
tb.dut.tlul_assert_device.aKnown_AKnownEnable 0012008071695605300
tb.dut.tlul_assert_device.aReadyKnown_A 0012008071695605300
tb.dut.tlul_assert_device.dKnown_A 0012008071171900300
tb.dut.tlul_assert_device.dKnown_AKnownEnable 0012008071695605300
tb.dut.tlul_assert_device.dReadyKnown_A 0012008071695605300
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[119].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[11].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[120].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[121].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[122].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[123].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[124].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[125].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[126].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[127].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[128].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[129].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[12].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[130].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[131].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[132].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[133].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[134].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[135].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[136].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[137].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[138].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[139].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[13].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[140].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[141].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[142].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[143].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[144].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[145].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[146].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[147].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[148].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[149].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[14].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[150].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[151].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[152].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[153].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[154].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[155].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[156].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[157].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[158].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[159].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[15].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[160].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[161].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[162].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[163].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[164].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[165].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[166].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[167].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[168].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[169].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[16].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[170].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[171].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[172].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[173].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[174].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[175].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[176].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[177].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[178].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[179].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[17].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[180].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[181].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[182].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[183].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[184].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[185].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[186].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[187].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[188].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[189].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[18].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[190].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[191].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[192].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[193].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[194].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[195].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[196].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[197].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[198].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[199].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[19].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[1].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[200].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[201].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[202].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[203].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[204].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[205].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[206].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[207].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[208].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[209].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[20].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[210].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[211].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[212].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[213].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[214].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[215].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[216].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[217].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[218].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[219].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[21].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[220].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[221].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[222].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[223].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[224].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[225].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[226].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[227].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[228].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[229].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[22].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[230].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[231].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[232].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[233].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[234].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[235].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[236].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[237].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[238].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[239].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[23].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[240].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[241].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[242].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[243].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[244].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[245].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[246].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[247].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[248].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[249].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[24].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[250].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[251].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[252].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[253].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[254].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[255].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[25].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[26].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[27].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[28].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[29].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[2].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[30].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[31].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[32].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[33].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[34].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[35].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[36].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[37].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[38].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[39].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[3].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[40].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[41].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[42].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[43].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[44].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[45].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[46].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[47].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[48].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[49].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[4].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[50].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[51].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[52].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[53].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[54].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[55].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[56].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[57].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[58].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[59].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[5].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[60].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[61].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[62].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[63].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[64].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[65].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[66].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[67].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[68].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[69].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[6].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[70].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[71].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[72].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[73].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[74].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[75].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[76].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[77].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[78].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[79].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[7].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[80].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[81].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[82].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[83].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[84].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[85].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[86].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[87].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[88].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[89].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[8].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A 0062062000
tb.dut.tlul_assert_device.gen_device.aDataKnown_M 001200869147758900
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A 0012008071567100
tb.dut.tlul_assert_device.gen_device.contigMask_M 001200869177462800
tb.dut.tlul_assert_device.gen_device.dDataKnown_A 001200869188289100
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A 0012008071628000
tb.dut.tlul_assert_device.gen_device.legalAParam_M 0012008691106292900
tb.dut.tlul_assert_device.gen_device.legalDParam_A 0012008691171918600
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M 0012008691106292900
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A 0012008691171918600
tb.dut.tlul_assert_device.gen_device.respOpcode_A 0012008691171918600
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A 0012008691171918600
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A 0012008071354700
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A 0012008071281500
tb.dut.tlul_assert_device.p_dbw.TlDbw_A 0062062000
tb.dut.u_alert_info.CntStoreSlot_A 0050550500
tb.dut.u_alert_info.CntWidth_A 0050550500
tb.dut.u_cpu_info.CntStoreSlot_A 0050550500
tb.dut.u_cpu_info.CntWidth_A 0050550500
tb.dut.u_ctrl_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_ctrl_scanmode_sync.OutputsKnown_A 0012593550753613500
tb.dut.u_ctrl_scanmode_sync.gen_no_flops.OutputDelay_A 0012593550753613500
tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00212522074700
tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002639213400
tb.dut.u_d0_i2c0.u_prim_mubi4_sender.OutputsKnown_A 0012593550635854200
tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00223092180400
tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002639213400
tb.dut.u_d0_i2c0.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_d0_i2c0.u_scanmode_sync.OutputsKnown_A 0011229889646453900
tb.dut.u_d0_i2c0.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011229889646453900
tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00212522074700
tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002639213400
tb.dut.u_d0_i2c1.u_prim_mubi4_sender.OutputsKnown_A 0012593550636813400
tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00223402183500
tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002639213400
tb.dut.u_d0_i2c1.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_d0_i2c1.u_scanmode_sync.OutputsKnown_A 0011229889646453900
tb.dut.u_d0_i2c1.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011229889646453900
tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00212522074700
tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002639213400
tb.dut.u_d0_i2c2.u_prim_mubi4_sender.OutputsKnown_A 0012593550637032400
tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00223722186700
tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002639213400
tb.dut.u_d0_i2c2.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_d0_i2c2.u_scanmode_sync.OutputsKnown_A 0011229889646453900
tb.dut.u_d0_i2c2.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011229889646453900
tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00212522074700
tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002639213400
tb.dut.u_d0_lc.u_prim_mubi4_sender.OutputsKnown_A 00524749872719833500
tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00212022069700
tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002639213400
tb.dut.u_d0_lc.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_d0_lc.u_scanmode_sync.OutputsKnown_A 0011229889646453900
tb.dut.u_d0_lc.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011229889646453900
tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00212522074700
tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002639213400
tb.dut.u_d0_lc_io.u_prim_mubi4_sender.OutputsKnown_A 00503741232610845400
tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00212022069700
tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002639213400
tb.dut.u_d0_lc_io.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_d0_lc_io.u_scanmode_sync.OutputsKnown_A 0011229889646453900
tb.dut.u_d0_lc_io.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011229889646453900
tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00212522074700
tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002639213400
tb.dut.u_d0_lc_io_div2.u_prim_mubi4_sender.OutputsKnown_A 00251879751304431200
tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00212022069700
tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002639213400
tb.dut.u_d0_lc_io_div2.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_d0_lc_io_div2.u_scanmode_sync.OutputsKnown_A 0011229889646453900
tb.dut.u_d0_lc_io_div2.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011229889646453900
tb.dut.u_d0_lc_io_div4.u_prim_mubi4_sender.OutputsKnown_A 0012593550649532900
tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00212022069700
tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002639213400
tb.dut.u_d0_lc_io_div4.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_d0_lc_io_div4.u_scanmode_sync.OutputsKnown_A 0011229889646453900
tb.dut.u_d0_lc_io_div4.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011229889646453900
tb.dut.u_d0_lc_io_div4_shadowed.u_prim_mubi4_sender.OutputsKnown_A 0012593550649532900
tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00212022069700
tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002639213400
tb.dut.u_d0_lc_io_div4_shadowed.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_d0_lc_io_div4_shadowed.u_scanmode_sync.OutputsKnown_A 0011229889646453900
tb.dut.u_d0_lc_io_div4_shadowed.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011229889646453900
tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00212522074700
tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002639213400
tb.dut.u_d0_lc_shadowed.u_prim_mubi4_sender.OutputsKnown_A 00524749872719969600
tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00212022069700
tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002639213400
tb.dut.u_d0_lc_shadowed.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_d0_lc_shadowed.u_scanmode_sync.OutputsKnown_A 0011229889646453900
tb.dut.u_d0_lc_shadowed.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011229889646453900
tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00212522074700
tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002639213400
tb.dut.u_d0_lc_usb.u_prim_mubi4_sender.OutputsKnown_A 00251877021304439700
tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00212022069700
tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002639213400
tb.dut.u_d0_lc_usb.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_d0_lc_usb.u_scanmode_sync.OutputsKnown_A 0011229889646453900
tb.dut.u_d0_lc_usb.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011229889646453900
tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00212522074700
tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002639213400
tb.dut.u_d0_spi_device.u_prim_mubi4_sender.OutputsKnown_A 0012593550635116400
tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00220802157500
tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002639213400
tb.dut.u_d0_spi_device.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_d0_spi_device.u_scanmode_sync.OutputsKnown_A 0011229889646453900
tb.dut.u_d0_spi_device.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011229889646453900
tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00212522074700
tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002639213400
tb.dut.u_d0_spi_host0.u_prim_mubi4_sender.OutputsKnown_A 00503741232556259800
tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00221142160900
tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002639213400
tb.dut.u_d0_spi_host0.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_d0_spi_host0.u_scanmode_sync.OutputsKnown_A 0011229889646453900
tb.dut.u_d0_spi_host0.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011229889646453900
tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00212522074700
tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002639213400
tb.dut.u_d0_spi_host1.u_prim_mubi4_sender.OutputsKnown_A 00251879751276203500
tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00221592165400
tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002639213400
tb.dut.u_d0_spi_host1.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_d0_spi_host1.u_scanmode_sync.OutputsKnown_A 0011229889646453900
tb.dut.u_d0_spi_host1.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011229889646453900
tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00212522074700
tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002639213400
tb.dut.u_d0_sys.u_prim_mubi4_sender.OutputsKnown_A 00524749872690828200
tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00212022069700
tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002639213400
tb.dut.u_d0_sys.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_d0_sys.u_scanmode_sync.OutputsKnown_A 0011229889646453900
tb.dut.u_d0_sys.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011229889646453900
tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00212522074700
tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002639213400
tb.dut.u_d0_usb.u_prim_mubi4_sender.OutputsKnown_A 00251877021278150200
tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00221692166400
tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002639213400
tb.dut.u_d0_usb.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_d0_usb.u_scanmode_sync.OutputsKnown_A 0011229889646453900
tb.dut.u_d0_usb.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011229889646453900
tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00211312062600
tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002639213400
tb.dut.u_d0_usb_aon.u_prim_mubi4_sender.OutputsKnown_A 00158950778970500
tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00221972169200
tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002639213400
tb.dut.u_d0_usb_aon.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_d0_usb_aon.u_scanmode_sync.OutputsKnown_A 0011229889646453900
tb.dut.u_d0_usb_aon.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011229889646453900
tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00212522074700
tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002639213400
tb.dut.u_daon_lc.u_prim_mubi4_sender.OutputsKnown_A 00524749872790376800
tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00212022069700
tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002639213400
tb.dut.u_daon_lc.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_daon_lc.u_scanmode_sync.OutputsKnown_A 0011229889646453900
tb.dut.u_daon_lc.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011229889646453900
tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00211312062600
tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002639213400
tb.dut.u_daon_lc_aon.u_prim_mubi4_sender.OutputsKnown_A 00158950782717400
tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00212022069700
tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002639213400
tb.dut.u_daon_lc_aon.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_daon_lc_aon.u_scanmode_sync.OutputsKnown_A 0011229889646453900
tb.dut.u_daon_lc_aon.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011229889646453900
tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00212522074700
tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002639213400
tb.dut.u_daon_lc_io.u_prim_mubi4_sender.OutputsKnown_A 00503741232678772000
tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00212022069700
tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002639213400
tb.dut.u_daon_lc_io.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_daon_lc_io.u_scanmode_sync.OutputsKnown_A 0011229889646453900
tb.dut.u_daon_lc_io.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011229889646453900
tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00212522074700
tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002639213400
tb.dut.u_daon_lc_io_div2.u_prim_mubi4_sender.OutputsKnown_A 00251879751338416300
tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00212022069700
tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002639213400
tb.dut.u_daon_lc_io_div2.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_daon_lc_io_div2.u_scanmode_sync.OutputsKnown_A 0011229889646453900
tb.dut.u_daon_lc_io_div2.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011229889646453900
tb.dut.u_daon_lc_io_div4.u_prim_mubi4_sender.OutputsKnown_A 0012593550666512600
tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00212022069700
tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002639213400
tb.dut.u_daon_lc_io_div4.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_daon_lc_io_div4.u_scanmode_sync.OutputsKnown_A 0011229889646453900
tb.dut.u_daon_lc_io_div4.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011229889646453900
tb.dut.u_daon_lc_io_div4_shadowed.u_prim_mubi4_sender.OutputsKnown_A 0012593550666512600
tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00212022069700
tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002639213400
tb.dut.u_daon_lc_io_div4_shadowed.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_daon_lc_io_div4_shadowed.u_scanmode_sync.OutputsKnown_A 0011229889646453900
tb.dut.u_daon_lc_io_div4_shadowed.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011229889646453900
tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00212522074700
tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002639213400
tb.dut.u_daon_lc_shadowed.u_prim_mubi4_sender.OutputsKnown_A 00524749872790362400
tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00212022069700
tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002639213400
tb.dut.u_daon_lc_shadowed.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_daon_lc_shadowed.u_scanmode_sync.OutputsKnown_A 0011229889646453900
tb.dut.u_daon_lc_shadowed.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011229889646453900
tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00212522074700
tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002639213400
tb.dut.u_daon_lc_usb.u_prim_mubi4_sender.OutputsKnown_A 00251877021338405800
tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00212022069700
tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002639213400
tb.dut.u_daon_lc_usb.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_daon_lc_usb.u_scanmode_sync.OutputsKnown_A 0011229889646453900
tb.dut.u_daon_lc_usb.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011229889646453900
tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00212522074700
tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002639213400
tb.dut.u_daon_por.u_prim_mubi4_sender.OutputsKnown_A 00524749873142333800
tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic.selKnown0 008586808100
tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002639213400
tb.dut.u_daon_por.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_daon_por.u_scanmode_sync.OutputsKnown_A 0011229889646453900
tb.dut.u_daon_por.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011229889646453900
tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00212522074700
tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002639213400
tb.dut.u_daon_por_io.u_prim_mubi4_sender.OutputsKnown_A 00503741233016470400
tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic.selKnown0 008586808100
tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002639213400
tb.dut.u_daon_por_io.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_daon_por_io.u_scanmode_sync.OutputsKnown_A 0011229889646453900
tb.dut.u_daon_por_io.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011229889646453900
tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00212522074700
tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002639213400
tb.dut.u_daon_por_io_div2.u_prim_mubi4_sender.OutputsKnown_A 00251879751507900300
tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown0 008586808100
tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002639213400
tb.dut.u_daon_por_io_div2.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_daon_por_io_div2.u_scanmode_sync.OutputsKnown_A 0011229889646453900
tb.dut.u_daon_por_io_div2.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011229889646453900
tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00212522074700
tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002639213400
tb.dut.u_daon_por_io_div4.u_prim_mubi4_sender.OutputsKnown_A 0012593550753613500
tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown0 008586808100
tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002639213400
tb.dut.u_daon_por_io_div4.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_daon_por_io_div4.u_scanmode_sync.OutputsKnown_A 0011229889646453900
tb.dut.u_daon_por_io_div4.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011229889646453900
tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00212522074700
tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002639213400
tb.dut.u_daon_por_usb.u_prim_mubi4_sender.OutputsKnown_A 00251877021507863200
tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown0 008586808100
tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002639213400
tb.dut.u_daon_por_usb.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_daon_por_usb.u_scanmode_sync.OutputsKnown_A 0011229889646453900
tb.dut.u_daon_por_usb.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011229889646453900
tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00212522074700
tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002639213400
tb.dut.u_daon_sys_io_div4.u_prim_mubi4_sender.OutputsKnown_A 0012593550659561700
tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00212022069700
tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002639213400
tb.dut.u_daon_sys_io_div4.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050550500
tb.dut.u_daon_sys_io_div4.u_scanmode_sync.OutputsKnown_A 0011229889646453900
tb.dut.u_daon_sys_io_div4.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011229889646453900
tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic.selKnown0 00212022069700
tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic.selKnown1 002639213400
tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic.selKnown0 00212022069700
tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic.selKnown1 002639213400
tb.dut.u_reg.en2addrHit 001200807193236900
tb.dut.u_reg.reAfterRv 001200807193223200
tb.dut.u_reg.rePulse 001200807149919500
tb.dut.u_reg.u_chk.PayLoadWidthCheck 0062062000
tb.dut.u_reg.u_reg_if.AllowedLatency_A 0062062000
tb.dut.u_reg.u_reg_if.MatchedWidthAssert 0062062000
tb.dut.u_reg.u_reg_if.u_err.dataWidthOnly32_A 0062062000
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A 0062062000
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck 0062062000
tb.dut.u_reg.u_rsp_intg_gen.DataWidthCheck_A 0062062000
tb.dut.u_reg.u_rsp_intg_gen.PayLoadWidthCheck 0062062000
tb.dut.u_reg.wePulse 001200807143303700
tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic.selKnown0 00212022069700
tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic.selKnown1 002639213400
tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic.selKnown0 00212022069700
tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic.selKnown1 002639213400


Detail Report for Cover Sequences

Cover Sequences All Matches:
COVER SEQUENCESCATEGORYSEVERITYATTEMPTSALL MATCHESFIRST MATCHESINCOMPLETESRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C 0012008691515051500
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C 0012008691212721271
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C 0012008691213021301
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C 0012008691152215221
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C 001200869184841
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C 0012008691118211821
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C 0012008691103510351
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C 0012008691264226420
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C 001200869144165441650
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C 0012008691437535437535454

Cover Sequences First Matches:
COVER SEQUENCESCATEGORYSEVERITYATTEMPTSALL MATCHESFIRST MATCHESINCOMPLETESRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C 0012008691515051500
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C 0012008691212721271
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C 0012008691213021301
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C 0012008691152215221
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C 001200869184841
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C 0012008691118211821
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C 0012008691103510351
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C 0012008691264226420
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C 001200869144165441650
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C 0012008691437535437535454

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%