Group : rstmgr_env_pkg::rstmgr_env_cov::reset_stretcher_cg
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Group : rstmgr_env_pkg::rstmgr_env_cov::reset_stretcher_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv



Summary for Group rstmgr_env_pkg::rstmgr_env_cov::reset_stretcher_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00


Variables for Group rstmgr_env_pkg::rstmgr_env_cov::reset_stretcher_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
count_cp 4 0 4 100.00 100 1 1 0
length_cp 8 0 8 100.00 100 1 1 0


Summary for Variable count_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for count_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
others 9159 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
cb[0] 1286 1 T1 3 T2 3 T3 1
cb[1] 1144 1 T1 4 T2 4 T4 4
cb[2] 1076 1 T1 4 T2 3 T4 4
cb[3] 990 1 T1 4 T4 4 T5 3



Summary for Variable length_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for length_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
others 11198 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
lb[0] 377 1 T1 2 T2 1 T4 1
lb[1] 377 1 T2 3 T4 1 T5 3
lb[2] 310 1 T4 1 T5 3 T10 22
lb[3] 279 1 T2 1 T5 1 T10 27
lb[4] 282 1 T1 2 T2 3 T5 4
lb[5] 287 1 T10 18 T12 1 T20 1
lb[6] 310 1 T1 3 T2 1 T5 2
lb[7] 235 1 T1 3 T4 2 T10 26

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