Group : rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg
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Group : rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv



Summary for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 16 0 16 100.00


Variables for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
enable_cp 2 0 2 100.00 100 1 1 2
reset_info_cp 8 0 8 100.00 100 1 1 0


Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
capture_cross 16 0 16 100.00 100 1 1 0


Summary for Variable enable_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 7742 1 T1 18 T4 20 T12 77
auto[1] 10783 1 T1 83 T3 4 T4 81



Summary for Variable reset_info_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for reset_info_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
others 5770 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
reset_info_cp[1] 6236 1 T1 27 T2 1 T3 2
reset_info_cp[2] 2829 1 T1 14 T3 1 T4 15
reset_info_cp[4] 3731 1 T1 19 T3 1 T4 16
reset_info_cp[8] 111 1 T12 1 T21 1 T62 2
reset_info_cp[16] 120 1 T8 1 T12 2 T56 1
reset_info_cp[32] 127 1 T20 1 T59 1 T24 3
reset_info_cp[64] 116 1 T1 1 T7 1 T12 1
reset_info_cp[128] 105 1 T3 1 T22 1 T62 2



Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for capture_cross

Bins
reset_info_cpenable_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
reset_info_cp[1] auto[0] 2997 1 T1 18 T4 20 T12 33
reset_info_cp[1] auto[1] 2619 1 T1 8 T3 1 T4 6
reset_info_cp[2] auto[0] 861 1 T12 8 T21 6 T56 1
reset_info_cp[2] auto[1] 1968 1 T1 14 T3 1 T4 15
reset_info_cp[4] auto[0] 1284 1 T12 12 T21 8 T56 3
reset_info_cp[4] auto[1] 2447 1 T1 19 T3 1 T4 16
reset_info_cp[8] auto[0] 50 1 T12 1 T62 2 T67 2
reset_info_cp[8] auto[1] 61 1 T21 1 T63 1 T125 1
reset_info_cp[16] auto[0] 50 1 T12 1 T56 1 T91 2
reset_info_cp[16] auto[1] 70 1 T8 1 T12 1 T63 1
reset_info_cp[32] auto[0] 49 1 T125 2 T93 1 T67 1
reset_info_cp[32] auto[1] 78 1 T20 1 T59 1 T24 3
reset_info_cp[64] auto[0] 50 1 T12 1 T22 1 T56 1
reset_info_cp[64] auto[1] 66 1 T1 1 T7 1 T63 1
reset_info_cp[128] auto[0] 45 1 T22 1 T62 2 T91 1
reset_info_cp[128] auto[1] 60 1 T3 1 T59 1 T63 1

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