Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.88 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T503 /workspace/coverage/default/2.rstmgr_smoke.4211753586 Dec 31 12:47:54 PM PST 23 Dec 31 12:47:56 PM PST 23 205660791 ps
T504 /workspace/coverage/default/9.rstmgr_sw_rst.1859962996 Dec 31 12:47:58 PM PST 23 Dec 31 12:48:02 PM PST 23 454917022 ps
T505 /workspace/coverage/default/42.rstmgr_por_stretcher.374094453 Dec 31 12:48:11 PM PST 23 Dec 31 12:48:15 PM PST 23 167078509 ps
T506 /workspace/coverage/default/47.rstmgr_reset.4057308125 Dec 31 12:48:37 PM PST 23 Dec 31 12:48:43 PM PST 23 1014326928 ps
T507 /workspace/coverage/default/30.rstmgr_por_stretcher.3974559367 Dec 31 12:48:06 PM PST 23 Dec 31 12:48:08 PM PST 23 195569243 ps
T508 /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.3751564993 Dec 31 12:47:46 PM PST 23 Dec 31 12:47:49 PM PST 23 100356845 ps
T509 /workspace/coverage/default/37.rstmgr_alert_test.1515721479 Dec 31 12:47:58 PM PST 23 Dec 31 12:48:01 PM PST 23 66022049 ps
T510 /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.3876651751 Dec 31 12:48:46 PM PST 23 Dec 31 12:48:53 PM PST 23 92164119 ps
T511 /workspace/coverage/default/38.rstmgr_stress_all.2941599646 Dec 31 12:48:11 PM PST 23 Dec 31 12:48:38 PM PST 23 5066780479 ps
T512 /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.2491168459 Dec 31 12:48:23 PM PST 23 Dec 31 12:48:28 PM PST 23 154740742 ps
T513 /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.2431690244 Dec 31 12:48:06 PM PST 23 Dec 31 12:48:09 PM PST 23 244365646 ps
T514 /workspace/coverage/default/9.rstmgr_reset.824323893 Dec 31 12:48:00 PM PST 23 Dec 31 12:48:09 PM PST 23 1640245222 ps
T515 /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.1548431130 Dec 31 12:47:58 PM PST 23 Dec 31 12:48:00 PM PST 23 140410462 ps
T516 /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.3575197233 Dec 31 12:48:15 PM PST 23 Dec 31 12:48:29 PM PST 23 1898287393 ps
T517 /workspace/coverage/default/28.rstmgr_stress_all.3850745068 Dec 31 12:48:26 PM PST 23 Dec 31 12:48:41 PM PST 23 2866345009 ps
T54 /workspace/coverage/default/3.rstmgr_sec_cm.3299288763 Dec 31 12:47:24 PM PST 23 Dec 31 12:47:51 PM PST 23 16694488070 ps
T518 /workspace/coverage/default/10.rstmgr_smoke.3167748020 Dec 31 12:47:47 PM PST 23 Dec 31 12:47:54 PM PST 23 192240946 ps
T519 /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.3162492013 Dec 31 12:48:13 PM PST 23 Dec 31 12:48:29 PM PST 23 2357507046 ps
T520 /workspace/coverage/default/35.rstmgr_smoke.2067780244 Dec 31 12:48:29 PM PST 23 Dec 31 12:48:32 PM PST 23 114482487 ps
T521 /workspace/coverage/default/34.rstmgr_por_stretcher.2615608687 Dec 31 12:49:15 PM PST 23 Dec 31 12:49:17 PM PST 23 161027196 ps
T522 /workspace/coverage/default/29.rstmgr_reset.3613362645 Dec 31 12:48:52 PM PST 23 Dec 31 12:48:59 PM PST 23 1731627408 ps
T523 /workspace/coverage/default/32.rstmgr_sw_rst.422893551 Dec 31 12:47:52 PM PST 23 Dec 31 12:47:55 PM PST 23 151361999 ps
T524 /workspace/coverage/default/26.rstmgr_smoke.3888980471 Dec 31 12:48:15 PM PST 23 Dec 31 12:48:24 PM PST 23 239034264 ps
T525 /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.1841908097 Dec 31 12:47:15 PM PST 23 Dec 31 12:47:17 PM PST 23 109198113 ps
T526 /workspace/coverage/default/42.rstmgr_alert_test.2888768934 Dec 31 12:48:52 PM PST 23 Dec 31 12:48:54 PM PST 23 67033601 ps
T55 /workspace/coverage/default/2.rstmgr_sec_cm.2890610902 Dec 31 12:47:23 PM PST 23 Dec 31 12:47:57 PM PST 23 16512244069 ps
T527 /workspace/coverage/default/38.rstmgr_alert_test.3453689765 Dec 31 12:47:51 PM PST 23 Dec 31 12:47:53 PM PST 23 75982954 ps
T528 /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.3839175350 Dec 31 12:47:49 PM PST 23 Dec 31 12:47:52 PM PST 23 210489404 ps
T529 /workspace/coverage/default/19.rstmgr_sw_rst.3555990865 Dec 31 12:48:40 PM PST 23 Dec 31 12:48:44 PM PST 23 309738633 ps
T530 /workspace/coverage/default/3.rstmgr_por_stretcher.2551342584 Dec 31 12:47:24 PM PST 23 Dec 31 12:47:27 PM PST 23 182528389 ps
T531 /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.3613091475 Dec 31 12:48:18 PM PST 23 Dec 31 12:48:23 PM PST 23 244541746 ps
T532 /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.544471270 Dec 31 12:48:29 PM PST 23 Dec 31 12:48:32 PM PST 23 243941683 ps
T533 /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.1826513390 Dec 31 12:48:08 PM PST 23 Dec 31 12:48:12 PM PST 23 242874951 ps
T534 /workspace/coverage/default/12.rstmgr_reset.3774787270 Dec 31 12:47:35 PM PST 23 Dec 31 12:47:45 PM PST 23 748155375 ps
T535 /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.2144044296 Dec 31 12:48:40 PM PST 23 Dec 31 12:48:42 PM PST 23 101249056 ps
T536 /workspace/coverage/default/10.rstmgr_stress_all.3788731063 Dec 31 12:47:57 PM PST 23 Dec 31 12:48:22 PM PST 23 6683467120 ps
T537 /workspace/coverage/default/36.rstmgr_smoke.3539822192 Dec 31 12:48:41 PM PST 23 Dec 31 12:48:53 PM PST 23 118690275 ps
T538 /workspace/coverage/default/12.rstmgr_sw_rst.596073830 Dec 31 12:47:30 PM PST 23 Dec 31 12:47:40 PM PST 23 538158396 ps
T539 /workspace/coverage/default/40.rstmgr_sw_rst.2472737744 Dec 31 12:48:40 PM PST 23 Dec 31 12:48:44 PM PST 23 115120305 ps
T540 /workspace/coverage/default/24.rstmgr_smoke.2901479499 Dec 31 12:47:26 PM PST 23 Dec 31 12:47:34 PM PST 23 264875852 ps
T541 /workspace/coverage/default/31.rstmgr_smoke.2008129198 Dec 31 12:47:57 PM PST 23 Dec 31 12:48:00 PM PST 23 203242484 ps
T542 /workspace/coverage/default/38.rstmgr_por_stretcher.942639563 Dec 31 12:48:35 PM PST 23 Dec 31 12:48:37 PM PST 23 170368706 ps
T543 /workspace/coverage/default/46.rstmgr_sw_rst.2394681756 Dec 31 12:48:02 PM PST 23 Dec 31 12:48:07 PM PST 23 330821924 ps
T544 /workspace/coverage/default/31.rstmgr_alert_test.2692355734 Dec 31 12:48:43 PM PST 23 Dec 31 12:48:46 PM PST 23 56832037 ps
T545 /workspace/coverage/default/49.rstmgr_sw_rst.1919190413 Dec 31 12:48:20 PM PST 23 Dec 31 12:48:28 PM PST 23 124118941 ps
T546 /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.2353787054 Dec 31 12:48:05 PM PST 23 Dec 31 12:48:08 PM PST 23 244370415 ps
T547 /workspace/coverage/default/9.rstmgr_smoke.2292261610 Dec 31 12:48:16 PM PST 23 Dec 31 12:48:23 PM PST 23 195904726 ps
T548 /workspace/coverage/default/19.rstmgr_reset.709400075 Dec 31 12:48:42 PM PST 23 Dec 31 12:48:49 PM PST 23 1257789283 ps
T549 /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.2425257139 Dec 31 12:47:51 PM PST 23 Dec 31 12:47:53 PM PST 23 244245800 ps
T550 /workspace/coverage/default/44.rstmgr_por_stretcher.2204533960 Dec 31 12:49:22 PM PST 23 Dec 31 12:49:24 PM PST 23 119072964 ps
T551 /workspace/coverage/default/10.rstmgr_por_stretcher.1348911409 Dec 31 12:47:45 PM PST 23 Dec 31 12:47:47 PM PST 23 108903880 ps
T552 /workspace/coverage/default/42.rstmgr_stress_all.103521925 Dec 31 12:48:45 PM PST 23 Dec 31 12:49:34 PM PST 23 13251553907 ps
T553 /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.671880571 Dec 31 12:47:31 PM PST 23 Dec 31 12:47:44 PM PST 23 1893010322 ps
T554 /workspace/coverage/default/44.rstmgr_sw_rst.3889944715 Dec 31 12:49:13 PM PST 23 Dec 31 12:49:16 PM PST 23 116624922 ps
T555 /workspace/coverage/default/14.rstmgr_stress_all.1270030922 Dec 31 12:47:49 PM PST 23 Dec 31 12:48:03 PM PST 23 3822895158 ps
T556 /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.321431050 Dec 31 12:47:52 PM PST 23 Dec 31 12:47:54 PM PST 23 108325978 ps
T557 /workspace/coverage/default/45.rstmgr_smoke.2020878751 Dec 31 12:49:08 PM PST 23 Dec 31 12:49:10 PM PST 23 189702877 ps
T558 /workspace/coverage/default/32.rstmgr_alert_test.2234843783 Dec 31 12:48:16 PM PST 23 Dec 31 12:48:23 PM PST 23 84327301 ps
T559 /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.3817792516 Dec 31 12:47:29 PM PST 23 Dec 31 12:47:38 PM PST 23 244666987 ps
T560 /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.3203377047 Dec 31 12:49:14 PM PST 23 Dec 31 12:49:17 PM PST 23 257497178 ps
T561 /workspace/coverage/default/8.rstmgr_stress_all.3528191151 Dec 31 12:47:36 PM PST 23 Dec 31 12:48:05 PM PST 23 5530791446 ps
T562 /workspace/coverage/default/26.rstmgr_stress_all.2197630651 Dec 31 12:48:40 PM PST 23 Dec 31 12:49:05 PM PST 23 6166588276 ps
T563 /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.2890231465 Dec 31 12:48:18 PM PST 23 Dec 31 12:48:23 PM PST 23 164327427 ps
T564 /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.1220885680 Dec 31 12:48:07 PM PST 23 Dec 31 12:48:10 PM PST 23 156287400 ps
T565 /workspace/coverage/default/0.rstmgr_reset.350006391 Dec 31 12:47:19 PM PST 23 Dec 31 12:47:23 PM PST 23 751157717 ps
T566 /workspace/coverage/default/39.rstmgr_sw_rst.3807205064 Dec 31 12:48:28 PM PST 23 Dec 31 12:48:32 PM PST 23 265404566 ps
T567 /workspace/coverage/default/42.rstmgr_smoke.997131244 Dec 31 12:48:29 PM PST 23 Dec 31 12:48:31 PM PST 23 113730483 ps
T568 /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.1242829986 Dec 31 12:47:56 PM PST 23 Dec 31 12:48:05 PM PST 23 2371499976 ps
T569 /workspace/coverage/default/45.rstmgr_stress_all.3348112960 Dec 31 12:48:48 PM PST 23 Dec 31 12:49:06 PM PST 23 4952400491 ps
T570 /workspace/coverage/default/11.rstmgr_stress_all.97537464 Dec 31 12:47:48 PM PST 23 Dec 31 12:48:21 PM PST 23 7156999806 ps
T571 /workspace/coverage/default/3.rstmgr_sw_rst.2123046133 Dec 31 12:47:59 PM PST 23 Dec 31 12:48:04 PM PST 23 339988525 ps
T572 /workspace/coverage/default/43.rstmgr_smoke.719859478 Dec 31 12:48:46 PM PST 23 Dec 31 12:48:53 PM PST 23 194783048 ps
T573 /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.312574249 Dec 31 12:48:44 PM PST 23 Dec 31 12:48:46 PM PST 23 96573526 ps
T574 /workspace/coverage/default/27.rstmgr_alert_test.437815753 Dec 31 12:48:33 PM PST 23 Dec 31 12:48:35 PM PST 23 66497831 ps
T575 /workspace/coverage/default/11.rstmgr_reset.430972305 Dec 31 12:47:42 PM PST 23 Dec 31 12:47:50 PM PST 23 1508374306 ps
T576 /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.91631733 Dec 31 12:48:40 PM PST 23 Dec 31 12:48:48 PM PST 23 1224252845 ps
T577 /workspace/coverage/default/39.rstmgr_por_stretcher.4136974851 Dec 31 12:48:18 PM PST 23 Dec 31 12:48:23 PM PST 23 115404222 ps
T578 /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.1233543817 Dec 31 12:48:08 PM PST 23 Dec 31 12:48:12 PM PST 23 173118637 ps
T579 /workspace/coverage/default/48.rstmgr_sw_rst.117250735 Dec 31 12:48:42 PM PST 23 Dec 31 12:48:46 PM PST 23 388825419 ps
T580 /workspace/coverage/default/5.rstmgr_smoke.593847742 Dec 31 12:47:33 PM PST 23 Dec 31 12:47:39 PM PST 23 244740889 ps
T581 /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.1189172195 Dec 31 12:48:21 PM PST 23 Dec 31 12:48:35 PM PST 23 2358919732 ps
T582 /workspace/coverage/default/30.rstmgr_smoke.4152033054 Dec 31 12:48:42 PM PST 23 Dec 31 12:48:45 PM PST 23 187823560 ps
T583 /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.3823586581 Dec 31 12:47:30 PM PST 23 Dec 31 12:47:39 PM PST 23 243774411 ps
T584 /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.2703681474 Dec 31 12:47:59 PM PST 23 Dec 31 12:48:02 PM PST 23 126523502 ps
T585 /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.4277792005 Dec 31 12:47:57 PM PST 23 Dec 31 12:47:59 PM PST 23 245065656 ps
T586 /workspace/coverage/default/35.rstmgr_stress_all.874898499 Dec 31 12:48:39 PM PST 23 Dec 31 12:48:50 PM PST 23 1945801999 ps
T587 /workspace/coverage/default/35.rstmgr_por_stretcher.1167397295 Dec 31 12:48:08 PM PST 23 Dec 31 12:48:11 PM PST 23 158665159 ps
T588 /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.19404868 Dec 31 12:47:33 PM PST 23 Dec 31 12:47:39 PM PST 23 244375641 ps
T589 /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.3659097387 Dec 31 12:48:01 PM PST 23 Dec 31 12:48:05 PM PST 23 244745867 ps
T590 /workspace/coverage/default/18.rstmgr_reset.2551372187 Dec 31 12:48:44 PM PST 23 Dec 31 12:48:52 PM PST 23 1721369181 ps
T591 /workspace/coverage/default/40.rstmgr_por_stretcher.1905647674 Dec 31 12:48:24 PM PST 23 Dec 31 12:48:28 PM PST 23 135577265 ps
T592 /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.1886542940 Dec 31 12:47:45 PM PST 23 Dec 31 12:47:48 PM PST 23 165623116 ps
T593 /workspace/coverage/default/34.rstmgr_stress_all.1764815797 Dec 31 12:48:26 PM PST 23 Dec 31 12:48:40 PM PST 23 2221293843 ps
T594 /workspace/coverage/default/16.rstmgr_reset.2562572174 Dec 31 12:47:56 PM PST 23 Dec 31 12:48:01 PM PST 23 906255207 ps
T595 /workspace/coverage/default/8.rstmgr_por_stretcher.486913215 Dec 31 12:47:40 PM PST 23 Dec 31 12:47:44 PM PST 23 126065016 ps
T596 /workspace/coverage/default/41.rstmgr_por_stretcher.1542047856 Dec 31 12:48:33 PM PST 23 Dec 31 12:48:35 PM PST 23 104859232 ps
T597 /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.1261794212 Dec 31 12:48:00 PM PST 23 Dec 31 12:48:10 PM PST 23 1900163927 ps
T598 /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.1738700962 Dec 31 12:48:12 PM PST 23 Dec 31 12:48:22 PM PST 23 1907664624 ps
T599 /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.311659976 Dec 31 12:47:39 PM PST 23 Dec 31 12:47:48 PM PST 23 1229712602 ps
T600 /workspace/coverage/default/3.rstmgr_smoke.1683687096 Dec 31 12:47:40 PM PST 23 Dec 31 12:47:45 PM PST 23 262324886 ps
T601 /workspace/coverage/default/6.rstmgr_sw_rst.1456968015 Dec 31 12:47:24 PM PST 23 Dec 31 12:47:29 PM PST 23 332867039 ps
T602 /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.1809883959 Dec 31 12:47:42 PM PST 23 Dec 31 12:47:51 PM PST 23 1224038323 ps
T603 /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.351503810 Dec 31 12:48:56 PM PST 23 Dec 31 12:48:59 PM PST 23 149080000 ps
T604 /workspace/coverage/default/12.rstmgr_alert_test.786721445 Dec 31 12:47:57 PM PST 23 Dec 31 12:48:03 PM PST 23 70360288 ps
T605 /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.2246646226 Dec 31 12:48:33 PM PST 23 Dec 31 12:48:35 PM PST 23 243452225 ps
T606 /workspace/coverage/default/16.rstmgr_alert_test.2439076404 Dec 31 12:47:51 PM PST 23 Dec 31 12:47:53 PM PST 23 67231297 ps
T607 /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.1160776903 Dec 31 12:48:22 PM PST 23 Dec 31 12:48:35 PM PST 23 2360090453 ps
T608 /workspace/coverage/default/0.rstmgr_smoke.530626893 Dec 31 12:47:28 PM PST 23 Dec 31 12:47:39 PM PST 23 223526702 ps
T609 /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.1764480968 Dec 31 12:48:05 PM PST 23 Dec 31 12:48:08 PM PST 23 244820503 ps
T610 /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.778098561 Dec 31 12:48:10 PM PST 23 Dec 31 12:48:14 PM PST 23 157664678 ps
T611 /workspace/coverage/default/25.rstmgr_stress_all.2263726822 Dec 31 12:48:10 PM PST 23 Dec 31 12:48:32 PM PST 23 5880290504 ps
T612 /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.2409718518 Dec 31 12:49:01 PM PST 23 Dec 31 12:49:03 PM PST 23 244201081 ps
T613 /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.1191484130 Dec 31 12:47:32 PM PST 23 Dec 31 12:47:39 PM PST 23 245198898 ps
T614 /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.1702167855 Dec 31 12:48:01 PM PST 23 Dec 31 12:48:06 PM PST 23 261458885 ps
T615 /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.2902527302 Dec 31 12:48:25 PM PST 23 Dec 31 12:48:33 PM PST 23 1235331494 ps
T616 /workspace/coverage/default/32.rstmgr_smoke.28063702 Dec 31 12:48:09 PM PST 23 Dec 31 12:48:14 PM PST 23 110705690 ps
T617 /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.1170757625 Dec 31 12:47:50 PM PST 23 Dec 31 12:48:00 PM PST 23 2190178719 ps
T618 /workspace/coverage/default/15.rstmgr_alert_test.3936666026 Dec 31 12:47:34 PM PST 23 Dec 31 12:47:42 PM PST 23 75906044 ps
T619 /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.2443731024 Dec 31 12:47:37 PM PST 23 Dec 31 12:47:44 PM PST 23 159458517 ps
T620 /workspace/coverage/default/49.rstmgr_por_stretcher.1362263740 Dec 31 12:48:11 PM PST 23 Dec 31 12:48:15 PM PST 23 156240680 ps

Test location /workspace/coverage/default/7.rstmgr_smoke.2952407046
Short name T8
Test name
Test status
Simulation time 189356776 ps
CPU time 1.38 seconds
Started Dec 31 12:47:53 PM PST 23
Finished Dec 31 12:47:55 PM PST 23
Peak memory 199476 kb
Host smart-20b0f7bf-56f9-4fa0-b217-280957a9b864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952407046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.2952407046
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.3617896655
Short name T12
Test name
Test status
Simulation time 3813777244 ps
CPU time 13.84 seconds
Started Dec 31 12:47:37 PM PST 23
Finished Dec 31 12:47:56 PM PST 23
Peak memory 199488 kb
Host smart-b87ebaf9-a239-42b5-b479-b27f2df89448
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617896655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.3617896655
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.3459226658
Short name T43
Test name
Test status
Simulation time 170372922 ps
CPU time 1.71 seconds
Started Dec 31 12:19:21 PM PST 23
Finished Dec 31 12:19:26 PM PST 23
Peak memory 215972 kb
Host smart-900c58a3-4ec3-49ef-8694-818b93a0995a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459226658 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.3459226658
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.2370985091
Short name T47
Test name
Test status
Simulation time 8529592534 ps
CPU time 12.52 seconds
Started Dec 31 12:47:36 PM PST 23
Finished Dec 31 12:47:54 PM PST 23
Peak memory 216260 kb
Host smart-1c67eacc-fd19-4082-9034-37cb12c7869b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370985091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.2370985091
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.4130758561
Short name T65
Test name
Test status
Simulation time 460154352 ps
CPU time 2.49 seconds
Started Dec 31 12:48:17 PM PST 23
Finished Dec 31 12:48:25 PM PST 23
Peak memory 199248 kb
Host smart-495a8970-b1e6-4eea-8d05-73219f6d23b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130758561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.4130758561
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.2209695739
Short name T25
Test name
Test status
Simulation time 2348751886 ps
CPU time 7.78 seconds
Started Dec 31 12:48:03 PM PST 23
Finished Dec 31 12:48:13 PM PST 23
Peak memory 217420 kb
Host smart-6a4d1f1c-ade7-4174-afc8-f15b7710e8eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209695739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.2209695739
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3292668298
Short name T89
Test name
Test status
Simulation time 763630087 ps
CPU time 2.81 seconds
Started Dec 31 12:25:38 PM PST 23
Finished Dec 31 12:25:50 PM PST 23
Peak memory 199476 kb
Host smart-889549cb-7533-4eee-bc4e-90008cd63efa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292668298 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.3292668298
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.2287079157
Short name T124
Test name
Test status
Simulation time 145482291 ps
CPU time 1.08 seconds
Started Dec 31 12:47:58 PM PST 23
Finished Dec 31 12:48:00 PM PST 23
Peak memory 199276 kb
Host smart-2afc2d17-1de9-4311-8b81-e8612842d78e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287079157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.2287079157
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.605424160
Short name T126
Test name
Test status
Simulation time 76696264 ps
CPU time 0.76 seconds
Started Dec 31 12:47:11 PM PST 23
Finished Dec 31 12:47:14 PM PST 23
Peak memory 199036 kb
Host smart-b7e9e7f3-f17d-4e82-8cac-143b04a5fc4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605424160 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.605424160
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.2120843728
Short name T71
Test name
Test status
Simulation time 7116871971 ps
CPU time 24.3 seconds
Started Dec 31 12:48:06 PM PST 23
Finished Dec 31 12:48:32 PM PST 23
Peak memory 199552 kb
Host smart-64fb51bd-8fed-456d-8d0a-964dd2f9eecb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120843728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.2120843728
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.379683058
Short name T113
Test name
Test status
Simulation time 220163402 ps
CPU time 2.91 seconds
Started Dec 31 12:24:16 PM PST 23
Finished Dec 31 12:24:22 PM PST 23
Peak memory 199488 kb
Host smart-92d1c1c3-c788-41b8-ba38-7030281f092b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379683058 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.379683058
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.2687013912
Short name T143
Test name
Test status
Simulation time 282574773 ps
CPU time 1.41 seconds
Started Dec 31 12:48:20 PM PST 23
Finished Dec 31 12:48:25 PM PST 23
Peak memory 199416 kb
Host smart-a3cdabce-2137-4882-8075-5058b1d72952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687013912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.2687013912
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.4196581643
Short name T24
Test name
Test status
Simulation time 2343631742 ps
CPU time 8.81 seconds
Started Dec 31 12:48:02 PM PST 23
Finished Dec 31 12:48:13 PM PST 23
Peak memory 221316 kb
Host smart-8d1713b0-feb3-4c0c-ba43-d44594719ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196581643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.4196581643
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.2975991464
Short name T42
Test name
Test status
Simulation time 255907397 ps
CPU time 1.44 seconds
Started Dec 31 12:22:55 PM PST 23
Finished Dec 31 12:22:58 PM PST 23
Peak memory 199152 kb
Host smart-8795655f-23ec-4bea-a954-236cea923531
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975991464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.2975991464
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.1745192620
Short name T76
Test name
Test status
Simulation time 868332800 ps
CPU time 2.82 seconds
Started Dec 31 12:25:23 PM PST 23
Finished Dec 31 12:25:31 PM PST 23
Peak memory 198688 kb
Host smart-ddd1f317-7e1b-4969-a4b7-b0fa77642403
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745192620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.1745192620
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.328883318
Short name T13
Test name
Test status
Simulation time 201826767 ps
CPU time 0.88 seconds
Started Dec 31 12:47:24 PM PST 23
Finished Dec 31 12:47:27 PM PST 23
Peak memory 199120 kb
Host smart-11158614-f717-4d7c-a837-76323eeff287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328883318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.328883318
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.990355957
Short name T23
Test name
Test status
Simulation time 244237651 ps
CPU time 1.09 seconds
Started Dec 31 12:47:41 PM PST 23
Finished Dec 31 12:47:45 PM PST 23
Peak memory 216516 kb
Host smart-bd5a10c9-bb53-43fc-a211-de6754ac8e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990355957 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.990355957
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.2853898624
Short name T26
Test name
Test status
Simulation time 1888007909 ps
CPU time 7.36 seconds
Started Dec 31 12:48:05 PM PST 23
Finished Dec 31 12:48:14 PM PST 23
Peak memory 216728 kb
Host smart-a041b9de-e97e-4ab8-99a7-720066e2ff07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853898624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.2853898624
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.4232752263
Short name T117
Test name
Test status
Simulation time 1233581798 ps
CPU time 3.25 seconds
Started Dec 31 12:23:00 PM PST 23
Finished Dec 31 12:23:04 PM PST 23
Peak memory 199488 kb
Host smart-f1ff3132-2003-45fd-83a0-7006819b661f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232752263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.4232752263
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.46948448
Short name T40
Test name
Test status
Simulation time 149368056 ps
CPU time 1.61 seconds
Started Dec 31 12:47:32 PM PST 23
Finished Dec 31 12:47:39 PM PST 23
Peak memory 199284 kb
Host smart-78c76f07-9558-47b7-af93-482fb36d9979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46948448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.46948448
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2248180200
Short name T103
Test name
Test status
Simulation time 106324354 ps
CPU time 1.37 seconds
Started Dec 31 12:24:14 PM PST 23
Finished Dec 31 12:24:18 PM PST 23
Peak memory 198180 kb
Host smart-71d9594c-47f6-4221-bd59-a1448b9cc930
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248180200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.2
248180200
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3333613892
Short name T197
Test name
Test status
Simulation time 1549674711 ps
CPU time 8.05 seconds
Started Dec 31 12:23:00 PM PST 23
Finished Dec 31 12:23:09 PM PST 23
Peak memory 199372 kb
Host smart-d6eeda83-6624-4055-99d8-c5a878da615f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333613892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.3
333613892
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.1311397014
Short name T165
Test name
Test status
Simulation time 104789803 ps
CPU time 0.81 seconds
Started Dec 31 12:20:27 PM PST 23
Finished Dec 31 12:20:29 PM PST 23
Peak memory 199308 kb
Host smart-d4b1e9d6-d8b6-40f6-982b-3f4a150f9e7e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311397014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.1
311397014
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.3825233942
Short name T41
Test name
Test status
Simulation time 182333058 ps
CPU time 1.25 seconds
Started Dec 31 12:22:21 PM PST 23
Finished Dec 31 12:22:23 PM PST 23
Peak memory 199620 kb
Host smart-7e6e2b1e-6e52-4198-8390-bacefdc54bb8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825233942 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.3825233942
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.1391791593
Short name T190
Test name
Test status
Simulation time 80410797 ps
CPU time 0.74 seconds
Started Dec 31 12:28:07 PM PST 23
Finished Dec 31 12:28:11 PM PST 23
Peak memory 199376 kb
Host smart-dc5ceb64-17a4-4ce2-b912-80f6fd23d4d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391791593 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.1391791593
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.857875343
Short name T182
Test name
Test status
Simulation time 226161369 ps
CPU time 1.38 seconds
Started Dec 31 12:26:59 PM PST 23
Finished Dec 31 12:27:02 PM PST 23
Peak memory 199552 kb
Host smart-c50ba7e6-2857-4e0a-8a09-0ae8a2151756
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857875343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sam
e_csr_outstanding.857875343
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.898279825
Short name T74
Test name
Test status
Simulation time 432745453 ps
CPU time 2.8 seconds
Started Dec 31 12:26:34 PM PST 23
Finished Dec 31 12:26:40 PM PST 23
Peak memory 199540 kb
Host smart-37a15a71-ef4d-4ad9-a2fb-e1b91277aadc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898279825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.898279825
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.841372570
Short name T191
Test name
Test status
Simulation time 367278374 ps
CPU time 2.29 seconds
Started Dec 31 12:27:01 PM PST 23
Finished Dec 31 12:27:06 PM PST 23
Peak memory 199456 kb
Host smart-d86cdd71-4d55-4901-b553-b807965e623d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841372570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.841372570
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1643293975
Short name T218
Test name
Test status
Simulation time 805578893 ps
CPU time 4.16 seconds
Started Dec 31 12:23:11 PM PST 23
Finished Dec 31 12:23:16 PM PST 23
Peak memory 199112 kb
Host smart-9cb55915-f4c5-420c-973d-c1db412c6dab
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643293975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.1
643293975
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.536663340
Short name T203
Test name
Test status
Simulation time 93244475 ps
CPU time 0.84 seconds
Started Dec 31 12:23:10 PM PST 23
Finished Dec 31 12:23:12 PM PST 23
Peak memory 197900 kb
Host smart-0efb101e-78a3-4ddc-9109-ef6e437716ab
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536663340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.536663340
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3607946740
Short name T84
Test name
Test status
Simulation time 103868670 ps
CPU time 0.92 seconds
Started Dec 31 12:25:58 PM PST 23
Finished Dec 31 12:26:06 PM PST 23
Peak memory 199372 kb
Host smart-5a0569a2-5a69-4ae2-9ef4-e3d608ee5590
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607946740 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.3607946740
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.1034002831
Short name T233
Test name
Test status
Simulation time 64742085 ps
CPU time 0.74 seconds
Started Dec 31 12:26:27 PM PST 23
Finished Dec 31 12:26:28 PM PST 23
Peak memory 199380 kb
Host smart-a4a5cde4-3263-491e-87f9-9ddf90b3a5a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034002831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.1034002831
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.3881776084
Short name T177
Test name
Test status
Simulation time 90193472 ps
CPU time 0.97 seconds
Started Dec 31 12:25:54 PM PST 23
Finished Dec 31 12:26:03 PM PST 23
Peak memory 198724 kb
Host smart-7e4a04ee-3365-40a2-a31d-0fb1f76026a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881776084 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.3881776084
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.3367410689
Short name T174
Test name
Test status
Simulation time 306609073 ps
CPU time 2.1 seconds
Started Dec 31 12:18:22 PM PST 23
Finished Dec 31 12:18:25 PM PST 23
Peak memory 199424 kb
Host smart-5f95981f-c11c-4f28-af73-2a68e8f3c220
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367410689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.3367410689
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.93436939
Short name T88
Test name
Test status
Simulation time 435831185 ps
CPU time 1.96 seconds
Started Dec 31 12:19:08 PM PST 23
Finished Dec 31 12:19:10 PM PST 23
Peak memory 199828 kb
Host smart-3132ebe9-afc7-47ad-bc22-c730697ac63d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93436939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err.93436939
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.3799284595
Short name T189
Test name
Test status
Simulation time 138695194 ps
CPU time 1.16 seconds
Started Dec 31 12:24:02 PM PST 23
Finished Dec 31 12:24:09 PM PST 23
Peak memory 198288 kb
Host smart-d521a1ef-eb1a-4114-ba76-915335e125b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799284595 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.3799284595
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.143620909
Short name T166
Test name
Test status
Simulation time 77813306 ps
CPU time 0.77 seconds
Started Dec 31 12:24:02 PM PST 23
Finished Dec 31 12:24:09 PM PST 23
Peak memory 199028 kb
Host smart-eef5de58-0b90-4da3-a982-62e9960aca60
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143620909 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.143620909
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.3784404485
Short name T87
Test name
Test status
Simulation time 119782608 ps
CPU time 1.09 seconds
Started Dec 31 12:19:24 PM PST 23
Finished Dec 31 12:19:26 PM PST 23
Peak memory 199304 kb
Host smart-7c0694a5-b508-4155-bcc0-8e5bec4f0006
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784404485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.3784404485
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.365152789
Short name T112
Test name
Test status
Simulation time 174040665 ps
CPU time 1.71 seconds
Started Dec 31 12:19:30 PM PST 23
Finished Dec 31 12:19:32 PM PST 23
Peak memory 199872 kb
Host smart-b5e235f6-89fd-4bdc-a44d-106c17a52a66
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365152789 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.365152789
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.2910005221
Short name T214
Test name
Test status
Simulation time 781075719 ps
CPU time 2.85 seconds
Started Dec 31 12:22:56 PM PST 23
Finished Dec 31 12:23:01 PM PST 23
Peak memory 199492 kb
Host smart-857625a2-02bd-4f34-949f-f39248826a01
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910005221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.2910005221
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.3099903619
Short name T205
Test name
Test status
Simulation time 63497438 ps
CPU time 0.82 seconds
Started Dec 31 12:22:56 PM PST 23
Finished Dec 31 12:22:59 PM PST 23
Peak memory 199288 kb
Host smart-d79541f5-ed65-4a1e-bb78-ebdccaf69094
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099903619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.3099903619
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.67508617
Short name T110
Test name
Test status
Simulation time 89863942 ps
CPU time 1.01 seconds
Started Dec 31 12:19:08 PM PST 23
Finished Dec 31 12:19:10 PM PST 23
Peak memory 199824 kb
Host smart-284bfdc5-ee86-40da-b1c2-dad5807d2fba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67508617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_sam
e_csr_outstanding.67508617
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.1678764355
Short name T220
Test name
Test status
Simulation time 292326865 ps
CPU time 1.96 seconds
Started Dec 31 12:24:43 PM PST 23
Finished Dec 31 12:24:54 PM PST 23
Peak memory 198720 kb
Host smart-fe03b286-fdc4-49c5-9693-e2463fc937bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678764355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.1678764355
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1810519860
Short name T82
Test name
Test status
Simulation time 818744014 ps
CPU time 2.78 seconds
Started Dec 31 12:22:56 PM PST 23
Finished Dec 31 12:23:01 PM PST 23
Peak memory 199488 kb
Host smart-3f3ab465-b305-491a-ac2b-6d5f559ae248
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810519860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.1810519860
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.4134777482
Short name T78
Test name
Test status
Simulation time 187576588 ps
CPU time 1.38 seconds
Started Dec 31 12:22:26 PM PST 23
Finished Dec 31 12:22:28 PM PST 23
Peak memory 199468 kb
Host smart-9bbc0f86-ec21-4848-8779-6b433227f7f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134777482 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.4134777482
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.3319958392
Short name T202
Test name
Test status
Simulation time 73658916 ps
CPU time 0.8 seconds
Started Dec 31 12:23:18 PM PST 23
Finished Dec 31 12:23:20 PM PST 23
Peak memory 199084 kb
Host smart-200177b8-8121-4f98-835a-f2494bfbc75d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319958392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.3319958392
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.1122821388
Short name T228
Test name
Test status
Simulation time 74776367 ps
CPU time 0.95 seconds
Started Dec 31 12:22:51 PM PST 23
Finished Dec 31 12:22:53 PM PST 23
Peak memory 197960 kb
Host smart-1f40ec2c-cda4-4d2e-91fb-4a7934e00f72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122821388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.1122821388
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.1371059696
Short name T172
Test name
Test status
Simulation time 458409719 ps
CPU time 3.34 seconds
Started Dec 31 12:23:37 PM PST 23
Finished Dec 31 12:23:43 PM PST 23
Peak memory 207580 kb
Host smart-ecfb114e-84c4-4455-a972-b6fc256bf747
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371059696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.1371059696
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.3975732109
Short name T123
Test name
Test status
Simulation time 780296836 ps
CPU time 2.73 seconds
Started Dec 31 12:24:16 PM PST 23
Finished Dec 31 12:24:21 PM PST 23
Peak memory 199484 kb
Host smart-f74fa309-1097-499c-b255-ac85ecd495d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975732109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.3975732109
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.176525477
Short name T209
Test name
Test status
Simulation time 94860928 ps
CPU time 0.95 seconds
Started Dec 31 12:21:16 PM PST 23
Finished Dec 31 12:21:17 PM PST 23
Peak memory 199444 kb
Host smart-6e3e32fe-69b9-4de1-a90e-8aba454c876a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176525477 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.176525477
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.675689878
Short name T193
Test name
Test status
Simulation time 78322680 ps
CPU time 0.8 seconds
Started Dec 31 12:19:13 PM PST 23
Finished Dec 31 12:19:15 PM PST 23
Peak memory 199348 kb
Host smart-e7e65158-7c47-47f7-931b-0cca83b2be05
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675689878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.675689878
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2474865367
Short name T111
Test name
Test status
Simulation time 140326658 ps
CPU time 1.03 seconds
Started Dec 31 12:27:18 PM PST 23
Finished Dec 31 12:27:21 PM PST 23
Peak memory 199060 kb
Host smart-16c21351-e368-4b79-8b4f-4cddc97e6445
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474865367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.2474865367
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.775081564
Short name T179
Test name
Test status
Simulation time 107951730 ps
CPU time 1.43 seconds
Started Dec 31 12:23:38 PM PST 23
Finished Dec 31 12:23:43 PM PST 23
Peak memory 199412 kb
Host smart-ee8852f6-3a71-4a70-a4f6-beaa7eb5467c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775081564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.775081564
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.2953866069
Short name T178
Test name
Test status
Simulation time 789742606 ps
CPU time 2.91 seconds
Started Dec 31 12:26:47 PM PST 23
Finished Dec 31 12:26:51 PM PST 23
Peak memory 199356 kb
Host smart-46228158-6663-4592-88da-250eedac50c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953866069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.2953866069
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.1157447740
Short name T168
Test name
Test status
Simulation time 90024456 ps
CPU time 0.81 seconds
Started Dec 31 12:18:38 PM PST 23
Finished Dec 31 12:18:40 PM PST 23
Peak memory 199388 kb
Host smart-d99a6f11-e293-4f2f-9a58-9657e89bed9d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157447740 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.1157447740
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.1208772489
Short name T176
Test name
Test status
Simulation time 57243177 ps
CPU time 0.8 seconds
Started Dec 31 12:22:29 PM PST 23
Finished Dec 31 12:22:31 PM PST 23
Peak memory 198612 kb
Host smart-cf045ee5-dc44-443a-8cb6-c3970fa1664a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208772489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.1208772489
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1300745179
Short name T187
Test name
Test status
Simulation time 116749826 ps
CPU time 0.95 seconds
Started Dec 31 12:25:13 PM PST 23
Finished Dec 31 12:25:18 PM PST 23
Peak memory 199288 kb
Host smart-c8cf4f43-eaaa-4f93-8ce6-8d0cac7b9fb3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300745179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.1300745179
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.3103695720
Short name T204
Test name
Test status
Simulation time 379122174 ps
CPU time 2.52 seconds
Started Dec 31 12:22:05 PM PST 23
Finished Dec 31 12:22:11 PM PST 23
Peak memory 207652 kb
Host smart-9f9f5324-dba3-4b83-bf02-5eb8f87f3351
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103695720 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.3103695720
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.120043584
Short name T210
Test name
Test status
Simulation time 449871708 ps
CPU time 1.8 seconds
Started Dec 31 12:22:56 PM PST 23
Finished Dec 31 12:23:00 PM PST 23
Peak memory 199464 kb
Host smart-9128c89a-af41-4974-a281-90e89d4e88d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120043584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_err
.120043584
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.2112664292
Short name T77
Test name
Test status
Simulation time 123621904 ps
CPU time 1.08 seconds
Started Dec 31 12:25:52 PM PST 23
Finished Dec 31 12:26:00 PM PST 23
Peak memory 198324 kb
Host smart-3e27d629-f498-4080-aaed-b471e913b276
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112664292 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.2112664292
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3790545038
Short name T95
Test name
Test status
Simulation time 77730152 ps
CPU time 0.87 seconds
Started Dec 31 12:23:12 PM PST 23
Finished Dec 31 12:23:14 PM PST 23
Peak memory 198564 kb
Host smart-303cbc56-fdc6-44d4-baad-be9eaca0f944
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790545038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.3790545038
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.744837302
Short name T231
Test name
Test status
Simulation time 112441849 ps
CPU time 1.39 seconds
Started Dec 31 12:22:26 PM PST 23
Finished Dec 31 12:22:28 PM PST 23
Peak memory 199548 kb
Host smart-05e35717-77fe-42e2-9595-8b581e6b0626
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744837302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_sa
me_csr_outstanding.744837302
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.505168358
Short name T201
Test name
Test status
Simulation time 178411737 ps
CPU time 2.29 seconds
Started Dec 31 12:27:28 PM PST 23
Finished Dec 31 12:27:35 PM PST 23
Peak memory 207684 kb
Host smart-00a07d1c-37a0-428c-802b-7924413529fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505168358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.505168358
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.807655257
Short name T230
Test name
Test status
Simulation time 157830613 ps
CPU time 1.38 seconds
Started Dec 31 12:27:17 PM PST 23
Finished Dec 31 12:27:19 PM PST 23
Peak memory 207708 kb
Host smart-9ffaeff6-74dd-42ec-931b-3fc3c6cbfcec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807655257 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.807655257
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.3708368432
Short name T181
Test name
Test status
Simulation time 70196772 ps
CPU time 0.79 seconds
Started Dec 31 12:19:32 PM PST 23
Finished Dec 31 12:19:34 PM PST 23
Peak memory 199280 kb
Host smart-a5ca34d5-c6bc-433c-a51f-2afa88b37ffb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708368432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.3708368432
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3967745110
Short name T229
Test name
Test status
Simulation time 74653761 ps
CPU time 0.89 seconds
Started Dec 31 12:19:17 PM PST 23
Finished Dec 31 12:19:19 PM PST 23
Peak memory 199396 kb
Host smart-ec8e8e07-8c39-4d4e-b7ea-dff8a9f5121e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967745110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.3967745110
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3391500600
Short name T173
Test name
Test status
Simulation time 592539682 ps
CPU time 3.77 seconds
Started Dec 31 12:23:39 PM PST 23
Finished Dec 31 12:23:46 PM PST 23
Peak memory 199436 kb
Host smart-c49900c1-b786-4972-aabd-69f6b0f0b9df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391500600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.3391500600
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3117814587
Short name T170
Test name
Test status
Simulation time 195278099 ps
CPU time 1.27 seconds
Started Dec 31 12:21:18 PM PST 23
Finished Dec 31 12:21:19 PM PST 23
Peak memory 199620 kb
Host smart-c4124d5c-d34e-4e06-ada2-493828680266
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117814587 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.3117814587
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.3999636447
Short name T211
Test name
Test status
Simulation time 72494740 ps
CPU time 0.76 seconds
Started Dec 31 12:24:02 PM PST 23
Finished Dec 31 12:24:09 PM PST 23
Peak memory 198956 kb
Host smart-c3e3fa7d-a091-4526-86f2-4e3b31bd5080
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999636447 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.3999636447
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.3338166321
Short name T108
Test name
Test status
Simulation time 129037520 ps
CPU time 0.98 seconds
Started Dec 31 12:19:49 PM PST 23
Finished Dec 31 12:19:54 PM PST 23
Peak memory 199412 kb
Host smart-27b66453-a1b1-4a65-a22d-bf871c8e8fd7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338166321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.3338166321
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.4108197826
Short name T232
Test name
Test status
Simulation time 171192125 ps
CPU time 2.33 seconds
Started Dec 31 12:19:54 PM PST 23
Finished Dec 31 12:19:58 PM PST 23
Peak memory 199480 kb
Host smart-89254c50-71d4-415a-874f-fe38dd15f07c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108197826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.4108197826
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.4254395120
Short name T116
Test name
Test status
Simulation time 425452030 ps
CPU time 1.82 seconds
Started Dec 31 12:25:07 PM PST 23
Finished Dec 31 12:25:12 PM PST 23
Peak memory 199380 kb
Host smart-f1a43336-f53a-473f-886d-a5bc3e37bbf3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254395120 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.4254395120
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3233913039
Short name T208
Test name
Test status
Simulation time 170442420 ps
CPU time 1.63 seconds
Started Dec 31 12:23:15 PM PST 23
Finished Dec 31 12:23:17 PM PST 23
Peak memory 207756 kb
Host smart-e89dd102-0fb5-4652-8aba-9fb7074c9741
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233913039 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.3233913039
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.4031398528
Short name T85
Test name
Test status
Simulation time 72319822 ps
CPU time 0.77 seconds
Started Dec 31 12:22:56 PM PST 23
Finished Dec 31 12:22:59 PM PST 23
Peak memory 199324 kb
Host smart-1d7fa71f-3409-4081-a383-41abfca43e49
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031398528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.4031398528
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.3732050710
Short name T188
Test name
Test status
Simulation time 109287886 ps
CPU time 1.6 seconds
Started Dec 31 12:22:55 PM PST 23
Finished Dec 31 12:22:58 PM PST 23
Peak memory 198040 kb
Host smart-98d94cb5-6735-458e-a856-d506b0af51bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732050710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.3732050710
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.130346608
Short name T118
Test name
Test status
Simulation time 793206702 ps
CPU time 2.97 seconds
Started Dec 31 12:21:17 PM PST 23
Finished Dec 31 12:21:21 PM PST 23
Peak memory 199684 kb
Host smart-7c285f5d-d9d0-4b73-93f1-98e2fe9ca0f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130346608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_err
.130346608
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.3141559828
Short name T52
Test name
Test status
Simulation time 162856495 ps
CPU time 1.12 seconds
Started Dec 31 12:21:46 PM PST 23
Finished Dec 31 12:21:49 PM PST 23
Peak memory 199840 kb
Host smart-2ea665e4-2f7a-4f61-9839-a141ccafaf4f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141559828 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.3141559828
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2302365491
Short name T104
Test name
Test status
Simulation time 85450385 ps
CPU time 0.78 seconds
Started Dec 31 12:24:03 PM PST 23
Finished Dec 31 12:24:10 PM PST 23
Peak memory 198988 kb
Host smart-75cf6ffe-5333-4df3-8493-dfbff526fa2f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302365491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.2302365491
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.2590672417
Short name T106
Test name
Test status
Simulation time 206162461 ps
CPU time 1.55 seconds
Started Dec 31 12:22:56 PM PST 23
Finished Dec 31 12:23:00 PM PST 23
Peak memory 199232 kb
Host smart-5d3c8cd4-5fef-41a2-866c-05adb58054b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590672417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.2590672417
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.585867373
Short name T198
Test name
Test status
Simulation time 96872086 ps
CPU time 1.28 seconds
Started Dec 31 12:19:02 PM PST 23
Finished Dec 31 12:19:04 PM PST 23
Peak memory 199524 kb
Host smart-984a96cf-64a1-47d5-ac34-74c9d0f1bd31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585867373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.585867373
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.1050053644
Short name T75
Test name
Test status
Simulation time 892405432 ps
CPU time 3.02 seconds
Started Dec 31 12:18:42 PM PST 23
Finished Dec 31 12:18:45 PM PST 23
Peak memory 199460 kb
Host smart-967d9a5a-df94-447e-9fee-e505daa6c8c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050053644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.1050053644
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.2567816482
Short name T183
Test name
Test status
Simulation time 159605851 ps
CPU time 1.89 seconds
Started Dec 31 12:25:37 PM PST 23
Finished Dec 31 12:25:48 PM PST 23
Peak memory 198288 kb
Host smart-15df8deb-0306-485c-b5e7-5d2506ad6470
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567816482 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.2
567816482
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3796847859
Short name T105
Test name
Test status
Simulation time 266401226 ps
CPU time 3.08 seconds
Started Dec 31 12:25:38 PM PST 23
Finished Dec 31 12:25:50 PM PST 23
Peak memory 199184 kb
Host smart-f3e42ce1-a3b7-4c2e-afdd-83268ebb6abc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796847859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.3
796847859
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.3382093416
Short name T234
Test name
Test status
Simulation time 96827931 ps
CPU time 0.78 seconds
Started Dec 31 12:25:25 PM PST 23
Finished Dec 31 12:25:32 PM PST 23
Peak memory 198936 kb
Host smart-3136d8c3-c4e5-4738-b7f7-48addbb7447e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382093416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.3
382093416
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.1938570942
Short name T80
Test name
Test status
Simulation time 107487826 ps
CPU time 1.13 seconds
Started Dec 31 12:27:48 PM PST 23
Finished Dec 31 12:27:51 PM PST 23
Peak memory 199544 kb
Host smart-6d744884-4704-49ba-802e-e6819be91fed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938570942 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.1938570942
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.2501696757
Short name T195
Test name
Test status
Simulation time 74280731 ps
CPU time 0.82 seconds
Started Dec 31 12:26:45 PM PST 23
Finished Dec 31 12:26:48 PM PST 23
Peak memory 198372 kb
Host smart-6b984180-daeb-4558-ae19-9b242e48c0d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501696757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.2501696757
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.379904372
Short name T83
Test name
Test status
Simulation time 165282172 ps
CPU time 1.15 seconds
Started Dec 31 12:34:49 PM PST 23
Finished Dec 31 12:34:53 PM PST 23
Peak memory 199416 kb
Host smart-7738ff48-78e3-4da1-a06c-d6da6a1f0393
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379904372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sam
e_csr_outstanding.379904372
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.749573146
Short name T199
Test name
Test status
Simulation time 273655593 ps
CPU time 1.9 seconds
Started Dec 31 12:25:06 PM PST 23
Finished Dec 31 12:25:11 PM PST 23
Peak memory 198928 kb
Host smart-9d8ce2ef-664f-466a-8d15-e34296a4db30
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749573146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.749573146
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.886830264
Short name T60
Test name
Test status
Simulation time 895080883 ps
CPU time 2.87 seconds
Started Dec 31 12:27:29 PM PST 23
Finished Dec 31 12:27:32 PM PST 23
Peak memory 199532 kb
Host smart-e77981af-af18-4a93-9f22-da7637a94e5b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886830264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err.
886830264
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.3660980447
Short name T90
Test name
Test status
Simulation time 151952822 ps
CPU time 1.86 seconds
Started Dec 31 12:25:53 PM PST 23
Finished Dec 31 12:26:03 PM PST 23
Peak memory 199432 kb
Host smart-31ffe41f-127a-4ec6-9cf5-98c6f99680d3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660980447 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.3
660980447
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2065864060
Short name T196
Test name
Test status
Simulation time 1542379448 ps
CPU time 8.26 seconds
Started Dec 31 12:20:09 PM PST 23
Finished Dec 31 12:20:18 PM PST 23
Peak memory 199832 kb
Host smart-63b3c545-e388-4fbc-a76d-875233f14df9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065864060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.2
065864060
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.3049414536
Short name T219
Test name
Test status
Simulation time 116865334 ps
CPU time 0.88 seconds
Started Dec 31 12:25:47 PM PST 23
Finished Dec 31 12:25:56 PM PST 23
Peak memory 199312 kb
Host smart-3194c295-f8d3-4605-9706-fb58e385ea2e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049414536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.3
049414536
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2019439356
Short name T212
Test name
Test status
Simulation time 122070363 ps
CPU time 1.24 seconds
Started Dec 31 12:24:48 PM PST 23
Finished Dec 31 12:24:55 PM PST 23
Peak memory 198568 kb
Host smart-8b2b5006-1cec-4b7a-a46e-bad3c671730d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019439356 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.2019439356
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.3308992593
Short name T225
Test name
Test status
Simulation time 97499107 ps
CPU time 0.87 seconds
Started Dec 31 12:24:44 PM PST 23
Finished Dec 31 12:24:53 PM PST 23
Peak memory 198172 kb
Host smart-8a40d156-c4e2-49e5-a8db-b40553e011ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308992593 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.3308992593
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.744785833
Short name T227
Test name
Test status
Simulation time 254453285 ps
CPU time 1.51 seconds
Started Dec 31 12:25:30 PM PST 23
Finished Dec 31 12:25:39 PM PST 23
Peak memory 199396 kb
Host smart-92c5b2d7-d4ed-4efe-8868-a1eb3f089e4f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744785833 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sam
e_csr_outstanding.744785833
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.1789593790
Short name T45
Test name
Test status
Simulation time 147244230 ps
CPU time 1.88 seconds
Started Dec 31 12:25:20 PM PST 23
Finished Dec 31 12:25:26 PM PST 23
Peak memory 199432 kb
Host smart-91af8597-a291-490b-8201-7014b3946d9d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789593790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.1789593790
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.4184669360
Short name T169
Test name
Test status
Simulation time 783030300 ps
CPU time 2.94 seconds
Started Dec 31 12:24:20 PM PST 23
Finished Dec 31 12:24:25 PM PST 23
Peak memory 199164 kb
Host smart-ae6e577d-260e-4fc5-bdf6-2c4699952645
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184669360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.4184669360
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.216248213
Short name T207
Test name
Test status
Simulation time 363198852 ps
CPU time 2.44 seconds
Started Dec 31 12:19:56 PM PST 23
Finished Dec 31 12:19:59 PM PST 23
Peak memory 199368 kb
Host smart-9cd62e15-1638-4c6c-8f19-05f5c9f65d3f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216248213 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.216248213
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.806778717
Short name T206
Test name
Test status
Simulation time 1030993913 ps
CPU time 4.79 seconds
Started Dec 31 12:19:02 PM PST 23
Finished Dec 31 12:19:07 PM PST 23
Peak memory 199452 kb
Host smart-f361d08b-1167-48e4-914a-e46ad97e2f2c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806778717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.806778717
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1047715870
Short name T44
Test name
Test status
Simulation time 145572061 ps
CPU time 0.88 seconds
Started Dec 31 12:25:25 PM PST 23
Finished Dec 31 12:25:31 PM PST 23
Peak memory 199032 kb
Host smart-c06c7da2-0a06-4bf5-a0cb-8b9ec34ab675
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047715870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.1
047715870
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1423996079
Short name T119
Test name
Test status
Simulation time 164105487 ps
CPU time 1.39 seconds
Started Dec 31 12:23:24 PM PST 23
Finished Dec 31 12:23:26 PM PST 23
Peak memory 199552 kb
Host smart-ab9751c3-84c2-4941-820c-5f9868dc53d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423996079 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.1423996079
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1629145571
Short name T86
Test name
Test status
Simulation time 83406553 ps
CPU time 0.78 seconds
Started Dec 31 12:25:20 PM PST 23
Finished Dec 31 12:25:25 PM PST 23
Peak memory 199216 kb
Host smart-e0e056fd-4b52-48b0-8b7d-3c98bd5cd110
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629145571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.1629145571
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.1926282658
Short name T186
Test name
Test status
Simulation time 106948171 ps
CPU time 0.92 seconds
Started Dec 31 12:26:55 PM PST 23
Finished Dec 31 12:26:58 PM PST 23
Peak memory 199372 kb
Host smart-65390f4e-44fa-47e8-a429-8313f4f0b17a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926282658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.1926282658
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.578357371
Short name T217
Test name
Test status
Simulation time 327818755 ps
CPU time 2.34 seconds
Started Dec 31 12:24:18 PM PST 23
Finished Dec 31 12:24:23 PM PST 23
Peak memory 199452 kb
Host smart-26759a75-ed2d-4cc9-bd31-845ec3081a9f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578357371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.578357371
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.259256143
Short name T184
Test name
Test status
Simulation time 501278670 ps
CPU time 1.94 seconds
Started Dec 31 12:28:39 PM PST 23
Finished Dec 31 12:28:50 PM PST 23
Peak memory 199464 kb
Host smart-e2bb8e51-2297-4d8d-9e89-08d573ec5db0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259256143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err.
259256143
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.879869058
Short name T175
Test name
Test status
Simulation time 103202443 ps
CPU time 0.98 seconds
Started Dec 31 12:26:36 PM PST 23
Finished Dec 31 12:26:40 PM PST 23
Peak memory 199440 kb
Host smart-2326ce99-736b-492d-a3aa-b7ed1b596e32
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879869058 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.879869058
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.2811622693
Short name T81
Test name
Test status
Simulation time 62569660 ps
CPU time 0.72 seconds
Started Dec 31 12:25:47 PM PST 23
Finished Dec 31 12:25:55 PM PST 23
Peak memory 199324 kb
Host smart-16d60931-8d7e-4626-8ba5-c2bb52cba77b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811622693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.2811622693
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.3678631559
Short name T185
Test name
Test status
Simulation time 241236566 ps
CPU time 1.56 seconds
Started Dec 31 12:26:03 PM PST 23
Finished Dec 31 12:26:10 PM PST 23
Peak memory 198348 kb
Host smart-02585993-a36a-4384-a0e2-17d1966ae5ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678631559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.3678631559
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.1911811978
Short name T46
Test name
Test status
Simulation time 415622742 ps
CPU time 3.03 seconds
Started Dec 31 12:18:07 PM PST 23
Finished Dec 31 12:18:11 PM PST 23
Peak memory 199540 kb
Host smart-5dbb65e9-1464-4f09-8479-dbb6efd03a94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911811978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.1911811978
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.3908500785
Short name T216
Test name
Test status
Simulation time 466535309 ps
CPU time 1.83 seconds
Started Dec 31 12:22:52 PM PST 23
Finished Dec 31 12:22:55 PM PST 23
Peak memory 198676 kb
Host smart-cb7b44f0-bacb-4998-94cf-920c0d7bcb0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908500785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.3908500785
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.62046123
Short name T79
Test name
Test status
Simulation time 122909592 ps
CPU time 1.24 seconds
Started Dec 31 12:26:41 PM PST 23
Finished Dec 31 12:26:44 PM PST 23
Peak memory 207728 kb
Host smart-84220920-dee3-45cf-a7f5-5f72345b7ca0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62046123 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.62046123
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.2204938903
Short name T107
Test name
Test status
Simulation time 64613178 ps
CPU time 0.7 seconds
Started Dec 31 12:27:02 PM PST 23
Finished Dec 31 12:27:06 PM PST 23
Peak memory 199260 kb
Host smart-0ff71644-201c-4317-a052-cfe5aa571ba8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204938903 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.2204938903
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.25809625
Short name T223
Test name
Test status
Simulation time 81366270 ps
CPU time 0.88 seconds
Started Dec 31 12:25:32 PM PST 23
Finished Dec 31 12:25:40 PM PST 23
Peak memory 199336 kb
Host smart-bec84459-b88b-45c4-b634-340a4eb8440f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25809625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_same
_csr_outstanding.25809625
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.3605384315
Short name T222
Test name
Test status
Simulation time 258750124 ps
CPU time 2.01 seconds
Started Dec 31 12:25:07 PM PST 23
Finished Dec 31 12:25:12 PM PST 23
Peak memory 198504 kb
Host smart-89b601de-d665-4ebc-a91f-5c486bc60701
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605384315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.3605384315
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.2727622775
Short name T200
Test name
Test status
Simulation time 505616076 ps
CPU time 2.15 seconds
Started Dec 31 12:24:50 PM PST 23
Finished Dec 31 12:24:56 PM PST 23
Peak memory 198608 kb
Host smart-468fd865-ae4a-4e65-99a9-23fbc7770dc9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727622775 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.2727622775
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.1276318179
Short name T180
Test name
Test status
Simulation time 200908005 ps
CPU time 1.42 seconds
Started Dec 31 12:23:37 PM PST 23
Finished Dec 31 12:23:42 PM PST 23
Peak memory 199456 kb
Host smart-dfd3f719-19cd-42dd-bc99-2f52f5a9d7b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276318179 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.1276318179
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.1189891781
Short name T215
Test name
Test status
Simulation time 81207945 ps
CPU time 0.79 seconds
Started Dec 31 12:24:36 PM PST 23
Finished Dec 31 12:24:46 PM PST 23
Peak memory 199336 kb
Host smart-e686fdce-2e0c-4461-9baf-44bf5dd59118
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189891781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.1189891781
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.2656538061
Short name T171
Test name
Test status
Simulation time 84691647 ps
CPU time 1.01 seconds
Started Dec 31 12:24:18 PM PST 23
Finished Dec 31 12:24:21 PM PST 23
Peak memory 199404 kb
Host smart-5b3abbbb-8d94-4944-8d7e-6e883fc5fb50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656538061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.2656538061
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.2267478923
Short name T224
Test name
Test status
Simulation time 112248588 ps
CPU time 1.67 seconds
Started Dec 31 12:22:37 PM PST 23
Finished Dec 31 12:22:39 PM PST 23
Peak memory 198444 kb
Host smart-73ec6e3a-1b8d-4ac8-a96e-094c68fe02ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267478923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.2267478923
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.379636782
Short name T194
Test name
Test status
Simulation time 874903102 ps
CPU time 2.81 seconds
Started Dec 31 12:23:00 PM PST 23
Finished Dec 31 12:23:04 PM PST 23
Peak memory 199436 kb
Host smart-0c720fd0-3b6f-4e64-a185-045dca4786f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379636782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err.
379636782
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.362873978
Short name T221
Test name
Test status
Simulation time 121733314 ps
CPU time 1.4 seconds
Started Dec 31 12:19:32 PM PST 23
Finished Dec 31 12:19:34 PM PST 23
Peak memory 208256 kb
Host smart-102cf11f-2898-4a2e-83c3-3bc12804811f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362873978 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.362873978
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.3066868543
Short name T213
Test name
Test status
Simulation time 71902409 ps
CPU time 0.85 seconds
Started Dec 31 12:23:18 PM PST 23
Finished Dec 31 12:23:20 PM PST 23
Peak memory 199244 kb
Host smart-f28fd381-79b1-449b-a213-56c1a2690bd4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066868543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.3066868543
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.3873379218
Short name T109
Test name
Test status
Simulation time 125452386 ps
CPU time 0.98 seconds
Started Dec 31 12:25:33 PM PST 23
Finished Dec 31 12:25:41 PM PST 23
Peak memory 199304 kb
Host smart-2f0168ed-0132-43b0-b055-fd0ccf331e14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873379218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.3873379218
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.448682449
Short name T114
Test name
Test status
Simulation time 426118958 ps
CPU time 1.65 seconds
Started Dec 31 12:24:03 PM PST 23
Finished Dec 31 12:24:10 PM PST 23
Peak memory 199104 kb
Host smart-3f5edd51-5b4d-4b6e-a520-d8d825aef586
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448682449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err.
448682449
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.3534702496
Short name T167
Test name
Test status
Simulation time 110776165 ps
CPU time 0.94 seconds
Started Dec 31 12:25:23 PM PST 23
Finished Dec 31 12:25:29 PM PST 23
Peak memory 199396 kb
Host smart-5c4aa5cc-89e1-48ff-9161-f147ca243cdb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534702496 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.3534702496
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.4159832901
Short name T164
Test name
Test status
Simulation time 65525216 ps
CPU time 0.76 seconds
Started Dec 31 12:18:44 PM PST 23
Finished Dec 31 12:18:45 PM PST 23
Peak memory 199756 kb
Host smart-aafd5611-31c2-4968-b887-ca08dddabe82
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159832901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.4159832901
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.509566046
Short name T226
Test name
Test status
Simulation time 87066444 ps
CPU time 1.02 seconds
Started Dec 31 12:22:05 PM PST 23
Finished Dec 31 12:22:10 PM PST 23
Peak memory 199368 kb
Host smart-7e94ba84-964c-4848-b65d-9d2e8add7f04
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509566046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sam
e_csr_outstanding.509566046
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.592744630
Short name T192
Test name
Test status
Simulation time 199325913 ps
CPU time 2.71 seconds
Started Dec 31 12:24:02 PM PST 23
Finished Dec 31 12:24:11 PM PST 23
Peak memory 198424 kb
Host smart-af48fa87-88b1-4632-bd9f-9085db05121a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592744630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.592744630
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.2288381232
Short name T115
Test name
Test status
Simulation time 906911297 ps
CPU time 3 seconds
Started Dec 31 12:18:22 PM PST 23
Finished Dec 31 12:18:26 PM PST 23
Peak memory 199172 kb
Host smart-488a9a32-c45e-4021-a3fd-d1258c5dc927
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288381232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.2288381232
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.2184307157
Short name T443
Test name
Test status
Simulation time 1221506587 ps
CPU time 5.98 seconds
Started Dec 31 12:47:24 PM PST 23
Finished Dec 31 12:47:33 PM PST 23
Peak memory 220756 kb
Host smart-aed774d8-a8aa-4c31-9774-b3352c40734e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184307157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.2184307157
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_reset.350006391
Short name T565
Test name
Test status
Simulation time 751157717 ps
CPU time 3.87 seconds
Started Dec 31 12:47:19 PM PST 23
Finished Dec 31 12:47:23 PM PST 23
Peak memory 199424 kb
Host smart-44d82e21-a603-4538-8238-30db50fcc7b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350006391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.350006391
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.2136430008
Short name T48
Test name
Test status
Simulation time 8302312134 ps
CPU time 15.25 seconds
Started Dec 31 12:47:28 PM PST 23
Finished Dec 31 12:47:51 PM PST 23
Peak memory 216392 kb
Host smart-7015b8c5-eb81-4573-b1cc-b5a93737e0a9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136430008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.2136430008
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.47945271
Short name T288
Test name
Test status
Simulation time 176028996 ps
CPU time 1.15 seconds
Started Dec 31 12:47:31 PM PST 23
Finished Dec 31 12:47:39 PM PST 23
Peak memory 199268 kb
Host smart-7e0d703c-265c-403a-9476-04bf45f61602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47945271 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.47945271
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.530626893
Short name T608
Test name
Test status
Simulation time 223526702 ps
CPU time 1.38 seconds
Started Dec 31 12:47:28 PM PST 23
Finished Dec 31 12:47:39 PM PST 23
Peak memory 199420 kb
Host smart-8b841de4-e0bd-4391-8f22-155577132d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530626893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.530626893
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.1813168749
Short name T397
Test name
Test status
Simulation time 10485862302 ps
CPU time 34.17 seconds
Started Dec 31 12:47:16 PM PST 23
Finished Dec 31 12:47:51 PM PST 23
Peak memory 199456 kb
Host smart-2b15eeb9-a86d-42ee-ba5c-932e044fdbeb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813168749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.1813168749
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.1846879158
Short name T66
Test name
Test status
Simulation time 351124649 ps
CPU time 2.42 seconds
Started Dec 31 12:47:22 PM PST 23
Finished Dec 31 12:47:26 PM PST 23
Peak memory 199280 kb
Host smart-2a311965-0386-4122-a3e0-bea44c00a7a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846879158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.1846879158
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.3731127224
Short name T155
Test name
Test status
Simulation time 272448607 ps
CPU time 1.43 seconds
Started Dec 31 12:47:30 PM PST 23
Finished Dec 31 12:47:39 PM PST 23
Peak memory 199440 kb
Host smart-5e9ec26c-b9a3-4097-88f2-fc6b17ae5c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731127224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.3731127224
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.954205494
Short name T450
Test name
Test status
Simulation time 56696746 ps
CPU time 0.68 seconds
Started Dec 31 12:47:39 PM PST 23
Finished Dec 31 12:47:44 PM PST 23
Peak memory 199092 kb
Host smart-aa4f617e-4005-4056-beb8-7f188695cf6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954205494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.954205494
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.671880571
Short name T553
Test name
Test status
Simulation time 1893010322 ps
CPU time 6.67 seconds
Started Dec 31 12:47:31 PM PST 23
Finished Dec 31 12:47:44 PM PST 23
Peak memory 220648 kb
Host smart-90d4af83-49de-4fe7-b748-9f161d8a4b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671880571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.671880571
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.2641937687
Short name T139
Test name
Test status
Simulation time 245072733 ps
CPU time 1.01 seconds
Started Dec 31 12:47:53 PM PST 23
Finished Dec 31 12:47:55 PM PST 23
Peak memory 216520 kb
Host smart-850c217c-e7c3-420a-8471-721b3c5e4d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641937687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.2641937687
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.3097138645
Short name T268
Test name
Test status
Simulation time 176447043 ps
CPU time 0.85 seconds
Started Dec 31 12:47:26 PM PST 23
Finished Dec 31 12:47:38 PM PST 23
Peak memory 199148 kb
Host smart-1cceeacb-40c9-4205-ac49-1638db48b50d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097138645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.3097138645
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.729870275
Short name T501
Test name
Test status
Simulation time 2056249781 ps
CPU time 7.95 seconds
Started Dec 31 12:47:32 PM PST 23
Finished Dec 31 12:47:45 PM PST 23
Peak memory 199420 kb
Host smart-c9fe68bb-4362-4fc2-a619-cf6495146040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729870275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.729870275
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.4030762748
Short name T10
Test name
Test status
Simulation time 16617286451 ps
CPU time 26.11 seconds
Started Dec 31 12:47:58 PM PST 23
Finished Dec 31 12:48:25 PM PST 23
Peak memory 217376 kb
Host smart-86e62584-1301-4776-929a-b4f22c2ab1fb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030762748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.4030762748
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.2178425926
Short name T96
Test name
Test status
Simulation time 158815484 ps
CPU time 1.07 seconds
Started Dec 31 12:47:51 PM PST 23
Finished Dec 31 12:47:53 PM PST 23
Peak memory 199332 kb
Host smart-5aad5d53-9963-49f6-9415-359661c3257b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178425926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.2178425926
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.862805560
Short name T7
Test name
Test status
Simulation time 199233556 ps
CPU time 1.37 seconds
Started Dec 31 12:47:36 PM PST 23
Finished Dec 31 12:47:44 PM PST 23
Peak memory 199420 kb
Host smart-f4e6461d-c09d-4351-9ec4-fd38a4560429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862805560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.862805560
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.1286379822
Short name T471
Test name
Test status
Simulation time 1199036218 ps
CPU time 5.63 seconds
Started Dec 31 12:47:15 PM PST 23
Finished Dec 31 12:47:22 PM PST 23
Peak memory 199524 kb
Host smart-c568ac8f-9658-405d-935f-5c8d0ea2a09f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286379822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.1286379822
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.3799642002
Short name T366
Test name
Test status
Simulation time 350278915 ps
CPU time 1.99 seconds
Started Dec 31 12:47:24 PM PST 23
Finished Dec 31 12:47:28 PM PST 23
Peak memory 199224 kb
Host smart-7f2c8006-04c4-4c0f-8d46-0c1a08d919f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799642002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.3799642002
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.2856542639
Short name T402
Test name
Test status
Simulation time 173291558 ps
CPU time 1.08 seconds
Started Dec 31 12:47:29 PM PST 23
Finished Dec 31 12:47:39 PM PST 23
Peak memory 199284 kb
Host smart-6ca7fbc9-45d4-4930-9218-c105424bb1a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856542639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.2856542639
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.849705506
Short name T241
Test name
Test status
Simulation time 69994245 ps
CPU time 0.76 seconds
Started Dec 31 12:47:34 PM PST 23
Finished Dec 31 12:47:39 PM PST 23
Peak memory 199236 kb
Host smart-e23cbb3a-09b4-4abe-9ac3-e025056c1a2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849705506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.849705506
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.1888241686
Short name T146
Test name
Test status
Simulation time 244905280 ps
CPU time 1.02 seconds
Started Dec 31 12:47:31 PM PST 23
Finished Dec 31 12:47:39 PM PST 23
Peak memory 216504 kb
Host smart-1f473207-3ecb-46b8-94c1-97b7f970793b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888241686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.1888241686
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.1348911409
Short name T551
Test name
Test status
Simulation time 108903880 ps
CPU time 0.76 seconds
Started Dec 31 12:47:45 PM PST 23
Finished Dec 31 12:47:47 PM PST 23
Peak memory 199128 kb
Host smart-a4686fb0-097f-4ddd-9bd4-8900b7a9e6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348911409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.1348911409
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.2115587739
Short name T92
Test name
Test status
Simulation time 1640090659 ps
CPU time 6.39 seconds
Started Dec 31 12:48:07 PM PST 23
Finished Dec 31 12:48:16 PM PST 23
Peak memory 199500 kb
Host smart-18c33a7c-3835-4f0a-bcbc-f16667d6fd10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115587739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.2115587739
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.1548431130
Short name T515
Test name
Test status
Simulation time 140410462 ps
CPU time 1.02 seconds
Started Dec 31 12:47:58 PM PST 23
Finished Dec 31 12:48:00 PM PST 23
Peak memory 199360 kb
Host smart-b99d2203-7103-4d12-9fff-3d1d98856d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548431130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.1548431130
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.3167748020
Short name T518
Test name
Test status
Simulation time 192240946 ps
CPU time 1.38 seconds
Started Dec 31 12:47:47 PM PST 23
Finished Dec 31 12:47:54 PM PST 23
Peak memory 199384 kb
Host smart-4924fa65-3d05-4d45-9bbd-64048e7f602f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167748020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.3167748020
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.3788731063
Short name T536
Test name
Test status
Simulation time 6683467120 ps
CPU time 23.35 seconds
Started Dec 31 12:47:57 PM PST 23
Finished Dec 31 12:48:22 PM PST 23
Peak memory 199472 kb
Host smart-d8a2f90b-f74c-4159-87cf-3541f88c1b00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788731063 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.3788731063
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.1982374036
Short name T413
Test name
Test status
Simulation time 366289516 ps
CPU time 1.91 seconds
Started Dec 31 12:47:37 PM PST 23
Finished Dec 31 12:47:44 PM PST 23
Peak memory 199156 kb
Host smart-a85d6a54-c775-41f9-ac15-8392ad20dcf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982374036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.1982374036
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.2703681474
Short name T584
Test name
Test status
Simulation time 126523502 ps
CPU time 0.96 seconds
Started Dec 31 12:47:59 PM PST 23
Finished Dec 31 12:48:02 PM PST 23
Peak memory 199376 kb
Host smart-18bd13c5-fbe9-4bae-beaf-999b0d16b484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703681474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.2703681474
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.3254358392
Short name T475
Test name
Test status
Simulation time 63035289 ps
CPU time 0.71 seconds
Started Dec 31 12:47:59 PM PST 23
Finished Dec 31 12:48:03 PM PST 23
Peak memory 199156 kb
Host smart-5ce517ef-285d-4f41-82c6-db055489aa43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254358392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.3254358392
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.3982362183
Short name T31
Test name
Test status
Simulation time 2348172090 ps
CPU time 8.55 seconds
Started Dec 31 12:47:53 PM PST 23
Finished Dec 31 12:48:03 PM PST 23
Peak memory 217248 kb
Host smart-6d1e2902-9884-4f7f-9594-a0af47b8948c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982362183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.3982362183
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.173630487
Short name T444
Test name
Test status
Simulation time 244160464 ps
CPU time 1.08 seconds
Started Dec 31 12:47:41 PM PST 23
Finished Dec 31 12:47:45 PM PST 23
Peak memory 216280 kb
Host smart-d0eee122-ecfb-4a3d-afa5-ff9ed2bbd4ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173630487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.173630487
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.148525939
Short name T275
Test name
Test status
Simulation time 161031029 ps
CPU time 0.88 seconds
Started Dec 31 12:47:34 PM PST 23
Finished Dec 31 12:47:41 PM PST 23
Peak memory 199076 kb
Host smart-d40903b7-ddf8-47fb-9fc3-d2c3b8597d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148525939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.148525939
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.430972305
Short name T575
Test name
Test status
Simulation time 1508374306 ps
CPU time 5.39 seconds
Started Dec 31 12:47:42 PM PST 23
Finished Dec 31 12:47:50 PM PST 23
Peak memory 199352 kb
Host smart-85697230-b6cd-4cb5-8e75-d9778089f833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430972305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.430972305
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.3914320544
Short name T420
Test name
Test status
Simulation time 104993809 ps
CPU time 0.98 seconds
Started Dec 31 12:47:44 PM PST 23
Finished Dec 31 12:47:47 PM PST 23
Peak memory 199260 kb
Host smart-8d89816a-e31a-42d2-a688-57244f1a1c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914320544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.3914320544
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.3459942836
Short name T460
Test name
Test status
Simulation time 264739150 ps
CPU time 1.55 seconds
Started Dec 31 12:47:39 PM PST 23
Finished Dec 31 12:47:45 PM PST 23
Peak memory 199528 kb
Host smart-4f4b2cb5-2f20-4d58-9108-2ac7fa733de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459942836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.3459942836
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.97537464
Short name T570
Test name
Test status
Simulation time 7156999806 ps
CPU time 30.5 seconds
Started Dec 31 12:47:48 PM PST 23
Finished Dec 31 12:48:21 PM PST 23
Peak memory 199608 kb
Host smart-2dfd5be8-b278-4de9-8f89-651efbc54cd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97537464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.97537464
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.3070770536
Short name T330
Test name
Test status
Simulation time 200789899 ps
CPU time 1.22 seconds
Started Dec 31 12:47:44 PM PST 23
Finished Dec 31 12:47:47 PM PST 23
Peak memory 199360 kb
Host smart-d02f57f3-872d-4378-84f9-6a19b96d18f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070770536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.3070770536
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.786721445
Short name T604
Test name
Test status
Simulation time 70360288 ps
CPU time 0.76 seconds
Started Dec 31 12:47:57 PM PST 23
Finished Dec 31 12:48:03 PM PST 23
Peak memory 199108 kb
Host smart-fcf47ad0-8d87-4876-afa8-a630bb107474
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786721445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.786721445
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.311659976
Short name T599
Test name
Test status
Simulation time 1229712602 ps
CPU time 5.13 seconds
Started Dec 31 12:47:39 PM PST 23
Finished Dec 31 12:47:48 PM PST 23
Peak memory 216784 kb
Host smart-5ea30971-023a-4aca-b90d-c8fba1b53003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311659976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.311659976
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.2431690244
Short name T513
Test name
Test status
Simulation time 244365646 ps
CPU time 1.07 seconds
Started Dec 31 12:48:06 PM PST 23
Finished Dec 31 12:48:09 PM PST 23
Peak memory 216456 kb
Host smart-431423cd-7f8d-4e37-8092-1a70eb739f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431690244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.2431690244
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.1456920025
Short name T2
Test name
Test status
Simulation time 131024702 ps
CPU time 0.77 seconds
Started Dec 31 12:48:02 PM PST 23
Finished Dec 31 12:48:05 PM PST 23
Peak memory 199168 kb
Host smart-818b4ccd-f126-4611-8112-f34f69758064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456920025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.1456920025
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.3774787270
Short name T534
Test name
Test status
Simulation time 748155375 ps
CPU time 3.49 seconds
Started Dec 31 12:47:35 PM PST 23
Finished Dec 31 12:47:45 PM PST 23
Peak memory 199368 kb
Host smart-96de4c6d-bbeb-4512-bfb1-7631471cc5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774787270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.3774787270
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.1886542940
Short name T592
Test name
Test status
Simulation time 165623116 ps
CPU time 1.14 seconds
Started Dec 31 12:47:45 PM PST 23
Finished Dec 31 12:47:48 PM PST 23
Peak memory 199356 kb
Host smart-4f517f4e-62b4-4a58-9f95-1845b194bff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886542940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.1886542940
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.3954860872
Short name T64
Test name
Test status
Simulation time 200785044 ps
CPU time 1.3 seconds
Started Dec 31 12:47:43 PM PST 23
Finished Dec 31 12:47:47 PM PST 23
Peak memory 199472 kb
Host smart-6648007f-9d4d-4c6d-bd8e-702840c7b8ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954860872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.3954860872
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.2009570021
Short name T394
Test name
Test status
Simulation time 2489643539 ps
CPU time 8.99 seconds
Started Dec 31 12:47:52 PM PST 23
Finished Dec 31 12:48:02 PM PST 23
Peak memory 199592 kb
Host smart-7126574d-fa66-4493-a3a2-b035fc93a203
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009570021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.2009570021
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.596073830
Short name T538
Test name
Test status
Simulation time 538158396 ps
CPU time 2.55 seconds
Started Dec 31 12:47:30 PM PST 23
Finished Dec 31 12:47:40 PM PST 23
Peak memory 199268 kb
Host smart-d52bed0b-cb78-44de-bfe7-ff40634c6e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596073830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.596073830
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.1471305288
Short name T455
Test name
Test status
Simulation time 124413639 ps
CPU time 1.01 seconds
Started Dec 31 12:48:10 PM PST 23
Finished Dec 31 12:48:15 PM PST 23
Peak memory 199360 kb
Host smart-41b150ae-75fe-4965-9b70-63bb049b76bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471305288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.1471305288
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.631453571
Short name T98
Test name
Test status
Simulation time 63446437 ps
CPU time 0.8 seconds
Started Dec 31 12:47:31 PM PST 23
Finished Dec 31 12:47:38 PM PST 23
Peak memory 199120 kb
Host smart-de46ad89-27fa-4c29-a5d4-bf234ecf882a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631453571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.631453571
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.2132473836
Short name T383
Test name
Test status
Simulation time 1219629837 ps
CPU time 5.32 seconds
Started Dec 31 12:47:44 PM PST 23
Finished Dec 31 12:47:52 PM PST 23
Peak memory 221292 kb
Host smart-936eac82-1619-4fe8-a67e-3f592d559722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132473836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.2132473836
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.1785724395
Short name T344
Test name
Test status
Simulation time 244616550 ps
CPU time 1.03 seconds
Started Dec 31 12:47:34 PM PST 23
Finished Dec 31 12:47:41 PM PST 23
Peak memory 216424 kb
Host smart-82441c43-9529-43d0-a79f-6dce4f91345e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785724395 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.1785724395
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.2334946986
Short name T14
Test name
Test status
Simulation time 132648792 ps
CPU time 0.78 seconds
Started Dec 31 12:47:51 PM PST 23
Finished Dec 31 12:47:53 PM PST 23
Peak memory 199060 kb
Host smart-abf029f7-a528-4ade-ba4d-73e8d7105800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334946986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.2334946986
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.2927783276
Short name T335
Test name
Test status
Simulation time 1489164199 ps
CPU time 5.46 seconds
Started Dec 31 12:47:37 PM PST 23
Finished Dec 31 12:47:48 PM PST 23
Peak memory 199476 kb
Host smart-211b4e94-8eb2-4901-83a7-8178b7675eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927783276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.2927783276
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.1162855155
Short name T9
Test name
Test status
Simulation time 114039396 ps
CPU time 1.03 seconds
Started Dec 31 12:48:06 PM PST 23
Finished Dec 31 12:48:09 PM PST 23
Peak memory 199244 kb
Host smart-7956176f-7b52-4cce-9193-2730e883f39c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162855155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.1162855155
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.698460528
Short name T253
Test name
Test status
Simulation time 247564959 ps
CPU time 1.42 seconds
Started Dec 31 12:47:32 PM PST 23
Finished Dec 31 12:47:39 PM PST 23
Peak memory 199404 kb
Host smart-8d11ef5d-cdf3-43fd-ae6a-8383fc9283f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698460528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.698460528
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.1053389843
Short name T279
Test name
Test status
Simulation time 11823968247 ps
CPU time 42.02 seconds
Started Dec 31 12:47:44 PM PST 23
Finished Dec 31 12:48:28 PM PST 23
Peak memory 199616 kb
Host smart-4e4e6fb5-76f6-45e6-b53d-740e0360db4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053389843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.1053389843
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.2426071376
Short name T316
Test name
Test status
Simulation time 536619813 ps
CPU time 2.78 seconds
Started Dec 31 12:47:35 PM PST 23
Finished Dec 31 12:47:44 PM PST 23
Peak memory 199368 kb
Host smart-4783fa87-f4ae-4fa0-a5a6-72e17490f97f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426071376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.2426071376
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.1632342336
Short name T401
Test name
Test status
Simulation time 155070813 ps
CPU time 1.12 seconds
Started Dec 31 12:47:46 PM PST 23
Finished Dec 31 12:47:48 PM PST 23
Peak memory 199308 kb
Host smart-003f68f2-9d61-4166-92fe-f5e6f8e254a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632342336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.1632342336
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.3268016557
Short name T157
Test name
Test status
Simulation time 88447559 ps
CPU time 0.79 seconds
Started Dec 31 12:47:54 PM PST 23
Finished Dec 31 12:47:56 PM PST 23
Peak memory 199204 kb
Host smart-888baf2b-b4c0-4282-acc5-8391557dfe8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268016557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.3268016557
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.2430977519
Short name T36
Test name
Test status
Simulation time 1891930325 ps
CPU time 6.88 seconds
Started Dec 31 12:48:00 PM PST 23
Finished Dec 31 12:48:10 PM PST 23
Peak memory 220612 kb
Host smart-fb2f742d-d769-490d-bb6f-2b9393627e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430977519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.2430977519
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.343225370
Short name T496
Test name
Test status
Simulation time 244408445 ps
CPU time 1.02 seconds
Started Dec 31 12:48:16 PM PST 23
Finished Dec 31 12:48:23 PM PST 23
Peak memory 216384 kb
Host smart-0510c02e-f3d1-4f42-bd80-fec8a88dde6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343225370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.343225370
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.2461007651
Short name T255
Test name
Test status
Simulation time 133571973 ps
CPU time 0.81 seconds
Started Dec 31 12:47:48 PM PST 23
Finished Dec 31 12:47:51 PM PST 23
Peak memory 199176 kb
Host smart-44ec2c30-2958-456d-a082-eb880fdd2228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461007651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.2461007651
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.1240021836
Short name T251
Test name
Test status
Simulation time 1662957874 ps
CPU time 5.99 seconds
Started Dec 31 12:48:06 PM PST 23
Finished Dec 31 12:48:14 PM PST 23
Peak memory 199504 kb
Host smart-609be6d2-e4c0-4d2f-b510-d7424956e120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240021836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.1240021836
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.2443731024
Short name T619
Test name
Test status
Simulation time 159458517 ps
CPU time 1.11 seconds
Started Dec 31 12:47:37 PM PST 23
Finished Dec 31 12:47:44 PM PST 23
Peak memory 199364 kb
Host smart-765b30e2-ee73-4678-9202-0523c6ae5024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443731024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.2443731024
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.1989353150
Short name T361
Test name
Test status
Simulation time 226156310 ps
CPU time 1.36 seconds
Started Dec 31 12:47:23 PM PST 23
Finished Dec 31 12:47:26 PM PST 23
Peak memory 199460 kb
Host smart-6cb7d6d0-1375-43c1-9c7e-98b2ad1258c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989353150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.1989353150
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.1270030922
Short name T555
Test name
Test status
Simulation time 3822895158 ps
CPU time 12.53 seconds
Started Dec 31 12:47:49 PM PST 23
Finished Dec 31 12:48:03 PM PST 23
Peak memory 199556 kb
Host smart-118328a8-fc2c-4e4c-b988-a4ae1e3c22dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270030922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.1270030922
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.1403392422
Short name T465
Test name
Test status
Simulation time 132495101 ps
CPU time 1.71 seconds
Started Dec 31 12:47:27 PM PST 23
Finished Dec 31 12:47:34 PM PST 23
Peak memory 199136 kb
Host smart-670075f8-32c1-4733-b7e4-081bcdcac5b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403392422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.1403392422
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.1553645600
Short name T470
Test name
Test status
Simulation time 128190931 ps
CPU time 1.09 seconds
Started Dec 31 12:47:46 PM PST 23
Finished Dec 31 12:47:49 PM PST 23
Peak memory 199328 kb
Host smart-f7818a6e-438b-4cbb-ac54-b268d6bc3ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553645600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.1553645600
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.3936666026
Short name T618
Test name
Test status
Simulation time 75906044 ps
CPU time 0.76 seconds
Started Dec 31 12:47:34 PM PST 23
Finished Dec 31 12:47:42 PM PST 23
Peak memory 199200 kb
Host smart-4a9cdf77-2e7a-4418-8974-2abce9c251ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936666026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.3936666026
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.1201237569
Short name T37
Test name
Test status
Simulation time 1905257612 ps
CPU time 7.25 seconds
Started Dec 31 12:47:48 PM PST 23
Finished Dec 31 12:47:57 PM PST 23
Peak memory 216840 kb
Host smart-a8d09b7c-2c66-4b6c-bbd5-8d681192f66e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201237569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.1201237569
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.3025320260
Short name T358
Test name
Test status
Simulation time 244482442 ps
CPU time 1.15 seconds
Started Dec 31 12:48:02 PM PST 23
Finished Dec 31 12:48:06 PM PST 23
Peak memory 216432 kb
Host smart-c6c8115c-a66b-46c5-bfee-bf7eeb0161a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025320260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.3025320260
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.1681880476
Short name T261
Test name
Test status
Simulation time 153789540 ps
CPU time 0.85 seconds
Started Dec 31 12:47:59 PM PST 23
Finished Dec 31 12:48:02 PM PST 23
Peak memory 199168 kb
Host smart-7fe93711-5688-4431-a0e6-e12432b9dc1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681880476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.1681880476
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.1923223127
Short name T310
Test name
Test status
Simulation time 1478380069 ps
CPU time 6.37 seconds
Started Dec 31 12:47:37 PM PST 23
Finished Dec 31 12:47:49 PM PST 23
Peak memory 199420 kb
Host smart-5db8bcf4-2535-4592-a389-1f5400e97acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923223127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.1923223127
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.3281336135
Short name T149
Test name
Test status
Simulation time 142272615 ps
CPU time 1.07 seconds
Started Dec 31 12:47:58 PM PST 23
Finished Dec 31 12:48:00 PM PST 23
Peak memory 199368 kb
Host smart-b498d7a5-8e62-4311-98fe-cec10ec5d53c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281336135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.3281336135
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.3096393201
Short name T462
Test name
Test status
Simulation time 192315720 ps
CPU time 1.33 seconds
Started Dec 31 12:47:53 PM PST 23
Finished Dec 31 12:47:55 PM PST 23
Peak memory 199408 kb
Host smart-080c4909-f3a4-407e-b2b8-b6b68451c16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096393201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.3096393201
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.522684536
Short name T301
Test name
Test status
Simulation time 3389190132 ps
CPU time 13.19 seconds
Started Dec 31 12:47:28 PM PST 23
Finished Dec 31 12:47:47 PM PST 23
Peak memory 199572 kb
Host smart-f80900a3-a3f0-49f7-a301-e067ce5f857b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522684536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.522684536
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.1740694096
Short name T325
Test name
Test status
Simulation time 375649047 ps
CPU time 2.54 seconds
Started Dec 31 12:47:39 PM PST 23
Finished Dec 31 12:47:46 PM PST 23
Peak memory 199236 kb
Host smart-c3d83773-6e5c-40a6-8f8e-1338d4e26230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740694096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.1740694096
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.2723767651
Short name T373
Test name
Test status
Simulation time 107281626 ps
CPU time 0.87 seconds
Started Dec 31 12:48:03 PM PST 23
Finished Dec 31 12:48:05 PM PST 23
Peak memory 199252 kb
Host smart-77d50e9d-e234-452a-933f-ef5a06a5ca6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723767651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.2723767651
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.2439076404
Short name T606
Test name
Test status
Simulation time 67231297 ps
CPU time 0.71 seconds
Started Dec 31 12:47:51 PM PST 23
Finished Dec 31 12:47:53 PM PST 23
Peak memory 199084 kb
Host smart-16a7d9df-a92d-419f-af0b-dee6534f3569
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439076404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.2439076404
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.402483443
Short name T271
Test name
Test status
Simulation time 2345599076 ps
CPU time 8.37 seconds
Started Dec 31 12:48:06 PM PST 23
Finished Dec 31 12:48:16 PM PST 23
Peak memory 221352 kb
Host smart-f91d4136-4450-42bd-9d1b-e9a27a8d1de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402483443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.402483443
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.2446775995
Short name T53
Test name
Test status
Simulation time 244371969 ps
CPU time 1.16 seconds
Started Dec 31 12:47:48 PM PST 23
Finished Dec 31 12:47:51 PM PST 23
Peak memory 216384 kb
Host smart-edcd9d01-4e12-4717-ac22-d232221f0ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446775995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.2446775995
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.1497419286
Short name T467
Test name
Test status
Simulation time 168484829 ps
CPU time 0.86 seconds
Started Dec 31 12:47:48 PM PST 23
Finished Dec 31 12:47:51 PM PST 23
Peak memory 199132 kb
Host smart-40feb60c-790e-4dcd-81b3-5b0dca1fe965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497419286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.1497419286
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.2562572174
Short name T594
Test name
Test status
Simulation time 906255207 ps
CPU time 4.44 seconds
Started Dec 31 12:47:56 PM PST 23
Finished Dec 31 12:48:01 PM PST 23
Peak memory 199496 kb
Host smart-d534c23b-8f48-4e62-95b3-6114a2ae2eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562572174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.2562572174
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.2642652587
Short name T398
Test name
Test status
Simulation time 109746556 ps
CPU time 0.98 seconds
Started Dec 31 12:47:52 PM PST 23
Finished Dec 31 12:47:54 PM PST 23
Peak memory 199360 kb
Host smart-5ce24d89-1a75-4922-ba7a-594a4475a25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642652587 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.2642652587
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.590961742
Short name T473
Test name
Test status
Simulation time 117206606 ps
CPU time 1.15 seconds
Started Dec 31 12:48:18 PM PST 23
Finished Dec 31 12:48:24 PM PST 23
Peak memory 199472 kb
Host smart-ee5adf15-9ca1-4f5d-b98f-89399f0d69aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590961742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.590961742
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.2473792464
Short name T469
Test name
Test status
Simulation time 1673994543 ps
CPU time 6.69 seconds
Started Dec 31 12:47:31 PM PST 23
Finished Dec 31 12:47:44 PM PST 23
Peak memory 199500 kb
Host smart-11a5db58-5525-4f95-8b2e-4a498400fe29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473792464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.2473792464
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.3500679504
Short name T451
Test name
Test status
Simulation time 433199641 ps
CPU time 2.38 seconds
Started Dec 31 12:48:06 PM PST 23
Finished Dec 31 12:48:10 PM PST 23
Peak memory 199228 kb
Host smart-329d4c09-314f-4ce5-86d3-02e70a346161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500679504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.3500679504
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.3839175350
Short name T528
Test name
Test status
Simulation time 210489404 ps
CPU time 1.31 seconds
Started Dec 31 12:47:49 PM PST 23
Finished Dec 31 12:47:52 PM PST 23
Peak memory 199324 kb
Host smart-60bccb5d-9b9b-4776-b8c2-1d030f21a8e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839175350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.3839175350
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.169186510
Short name T281
Test name
Test status
Simulation time 75023991 ps
CPU time 0.77 seconds
Started Dec 31 12:48:35 PM PST 23
Finished Dec 31 12:48:37 PM PST 23
Peak memory 199156 kb
Host smart-e85e90f3-2c56-4af0-abb5-0357910e743d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169186510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.169186510
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.2838536505
Short name T1
Test name
Test status
Simulation time 1221299267 ps
CPU time 5.24 seconds
Started Dec 31 12:48:40 PM PST 23
Finished Dec 31 12:48:47 PM PST 23
Peak memory 220376 kb
Host smart-8562ec7f-b282-4917-9652-c7b12f81f1e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838536505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.2838536505
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.2516334200
Short name T405
Test name
Test status
Simulation time 244948050 ps
CPU time 1.07 seconds
Started Dec 31 12:48:15 PM PST 23
Finished Dec 31 12:48:22 PM PST 23
Peak memory 216552 kb
Host smart-0109d155-efde-4d58-b843-da59c867b1be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516334200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.2516334200
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.2296944643
Short name T392
Test name
Test status
Simulation time 144274011 ps
CPU time 0.78 seconds
Started Dec 31 12:48:15 PM PST 23
Finished Dec 31 12:48:23 PM PST 23
Peak memory 199080 kb
Host smart-b25fd42b-ca53-4c4c-bc3f-0cf6cfeadc56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296944643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.2296944643
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.3196886850
Short name T91
Test name
Test status
Simulation time 1489657927 ps
CPU time 5.34 seconds
Started Dec 31 12:47:50 PM PST 23
Finished Dec 31 12:47:57 PM PST 23
Peak memory 199432 kb
Host smart-08a8785e-fb16-49e1-9d3c-8baf4329ffba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196886850 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.3196886850
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.1274806558
Short name T436
Test name
Test status
Simulation time 169490936 ps
CPU time 1.1 seconds
Started Dec 31 12:47:53 PM PST 23
Finished Dec 31 12:47:55 PM PST 23
Peak memory 199408 kb
Host smart-8920df05-9405-4c95-a328-0e727000702e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274806558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.1274806558
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.49734960
Short name T313
Test name
Test status
Simulation time 123027541 ps
CPU time 1.13 seconds
Started Dec 31 12:47:43 PM PST 23
Finished Dec 31 12:47:47 PM PST 23
Peak memory 199448 kb
Host smart-858c19cd-19c8-4651-ac16-663158af5598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49734960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.49734960
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.1903693539
Short name T244
Test name
Test status
Simulation time 4989203335 ps
CPU time 18.05 seconds
Started Dec 31 12:48:09 PM PST 23
Finished Dec 31 12:48:30 PM PST 23
Peak memory 199828 kb
Host smart-7648071c-fe6e-4ae2-8067-47d2be563317
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903693539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.1903693539
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.2951107531
Short name T148
Test name
Test status
Simulation time 243525615 ps
CPU time 1.66 seconds
Started Dec 31 12:48:21 PM PST 23
Finished Dec 31 12:48:28 PM PST 23
Peak memory 199340 kb
Host smart-ee43607d-4154-4e4e-b719-5dec5f66cd62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951107531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.2951107531
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.337350544
Short name T285
Test name
Test status
Simulation time 174064766 ps
CPU time 1.1 seconds
Started Dec 31 12:48:02 PM PST 23
Finished Dec 31 12:48:05 PM PST 23
Peak memory 199268 kb
Host smart-f28a45f9-7079-40fa-bb6d-95e32fa98ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337350544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.337350544
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.256558952
Short name T334
Test name
Test status
Simulation time 61450537 ps
CPU time 0.7 seconds
Started Dec 31 12:48:33 PM PST 23
Finished Dec 31 12:48:34 PM PST 23
Peak memory 199180 kb
Host smart-a30a92ed-74bd-4077-8d6e-c530f4b51426
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256558952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.256558952
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.1422126602
Short name T317
Test name
Test status
Simulation time 1230287462 ps
CPU time 6.18 seconds
Started Dec 31 12:48:58 PM PST 23
Finished Dec 31 12:49:06 PM PST 23
Peak memory 216728 kb
Host smart-6f670f07-9ed0-483e-97d9-243e5bbf6fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422126602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.1422126602
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.2905629128
Short name T424
Test name
Test status
Simulation time 244284513 ps
CPU time 1.12 seconds
Started Dec 31 12:48:39 PM PST 23
Finished Dec 31 12:48:41 PM PST 23
Peak memory 216456 kb
Host smart-e325e60f-b22f-4b73-8a33-746f74bc5123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905629128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.2905629128
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.1594044040
Short name T356
Test name
Test status
Simulation time 217273482 ps
CPU time 0.84 seconds
Started Dec 31 12:48:08 PM PST 23
Finished Dec 31 12:48:11 PM PST 23
Peak memory 199080 kb
Host smart-5461b48c-8c33-4f33-a899-f5d6b9fb8323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594044040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.1594044040
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.2551372187
Short name T590
Test name
Test status
Simulation time 1721369181 ps
CPU time 6.57 seconds
Started Dec 31 12:48:44 PM PST 23
Finished Dec 31 12:48:52 PM PST 23
Peak memory 199496 kb
Host smart-e2b133f7-3337-436e-962a-5887b3cd8da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551372187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.2551372187
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.206485270
Short name T287
Test name
Test status
Simulation time 102821863 ps
CPU time 1.03 seconds
Started Dec 31 12:48:37 PM PST 23
Finished Dec 31 12:48:39 PM PST 23
Peak memory 199340 kb
Host smart-0430a666-cbfe-4e17-9362-5cbfae8821fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206485270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.206485270
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.4042258011
Short name T391
Test name
Test status
Simulation time 116120013 ps
CPU time 1.17 seconds
Started Dec 31 12:48:29 PM PST 23
Finished Dec 31 12:48:32 PM PST 23
Peak memory 199432 kb
Host smart-b5e93023-3dc0-476e-941c-49bd49428f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042258011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.4042258011
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.2002947883
Short name T239
Test name
Test status
Simulation time 1477416271 ps
CPU time 6.41 seconds
Started Dec 31 12:48:39 PM PST 23
Finished Dec 31 12:48:46 PM PST 23
Peak memory 199528 kb
Host smart-51256133-1371-4981-8c60-ba9078d3689c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002947883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.2002947883
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.2516345763
Short name T39
Test name
Test status
Simulation time 354083834 ps
CPU time 2.23 seconds
Started Dec 31 12:48:27 PM PST 23
Finished Dec 31 12:48:32 PM PST 23
Peak memory 199372 kb
Host smart-615b6ac3-1c8c-4bd1-bc29-c63a9a50a419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516345763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.2516345763
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.1895856759
Short name T161
Test name
Test status
Simulation time 65412613 ps
CPU time 0.75 seconds
Started Dec 31 12:48:26 PM PST 23
Finished Dec 31 12:48:29 PM PST 23
Peak memory 199336 kb
Host smart-2d5a5a8a-b9f9-4980-8c3a-cf4985122609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895856759 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.1895856759
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.123004862
Short name T290
Test name
Test status
Simulation time 70655083 ps
CPU time 0.7 seconds
Started Dec 31 12:47:46 PM PST 23
Finished Dec 31 12:47:49 PM PST 23
Peak memory 199224 kb
Host smart-91323c03-e8bf-4077-9ac3-0d3c2b411fc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123004862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.123004862
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.152261262
Short name T284
Test name
Test status
Simulation time 244237772 ps
CPU time 1.03 seconds
Started Dec 31 12:47:33 PM PST 23
Finished Dec 31 12:47:39 PM PST 23
Peak memory 216508 kb
Host smart-546d3e83-51dd-4311-831f-8a401c93c460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152261262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.152261262
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.3406826959
Short name T11
Test name
Test status
Simulation time 102036364 ps
CPU time 0.71 seconds
Started Dec 31 12:48:10 PM PST 23
Finished Dec 31 12:48:21 PM PST 23
Peak memory 199184 kb
Host smart-eb81bb9b-fdca-4ca8-9c7b-6b8c468b869a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406826959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.3406826959
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.709400075
Short name T548
Test name
Test status
Simulation time 1257789283 ps
CPU time 5.11 seconds
Started Dec 31 12:48:42 PM PST 23
Finished Dec 31 12:48:49 PM PST 23
Peak memory 199496 kb
Host smart-0207198a-a94a-4faf-a69d-f163fa6c5826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709400075 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.709400075
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.725748926
Short name T378
Test name
Test status
Simulation time 103581448 ps
CPU time 0.96 seconds
Started Dec 31 12:48:51 PM PST 23
Finished Dec 31 12:48:53 PM PST 23
Peak memory 199324 kb
Host smart-0273704f-0684-4a17-ac45-1a2209f4a7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725748926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.725748926
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.1742975169
Short name T158
Test name
Test status
Simulation time 196375223 ps
CPU time 1.4 seconds
Started Dec 31 12:48:16 PM PST 23
Finished Dec 31 12:48:23 PM PST 23
Peak memory 199472 kb
Host smart-2d6c0d84-4dc8-4813-84fa-0f964b3891cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742975169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.1742975169
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.4194546086
Short name T339
Test name
Test status
Simulation time 8243221192 ps
CPU time 28.11 seconds
Started Dec 31 12:48:22 PM PST 23
Finished Dec 31 12:48:55 PM PST 23
Peak memory 199448 kb
Host smart-ef4e7ef6-ea09-4860-858d-03b60168beb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194546086 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.4194546086
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.3555990865
Short name T529
Test name
Test status
Simulation time 309738633 ps
CPU time 2 seconds
Started Dec 31 12:48:40 PM PST 23
Finished Dec 31 12:48:44 PM PST 23
Peak memory 199364 kb
Host smart-3b59503f-d067-4fd0-b0d1-ff0d3f6ba582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555990865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.3555990865
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.3830060598
Short name T145
Test name
Test status
Simulation time 101327673 ps
CPU time 0.83 seconds
Started Dec 31 12:49:00 PM PST 23
Finished Dec 31 12:49:02 PM PST 23
Peak memory 199304 kb
Host smart-e1587c19-63de-4b08-b50b-12e30f0d8884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830060598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.3830060598
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.2661952809
Short name T269
Test name
Test status
Simulation time 68365378 ps
CPU time 0.77 seconds
Started Dec 31 12:47:33 PM PST 23
Finished Dec 31 12:47:39 PM PST 23
Peak memory 199444 kb
Host smart-7cb4540a-61c6-4e7e-89db-92c44b9c5542
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661952809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.2661952809
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.1809883959
Short name T602
Test name
Test status
Simulation time 1224038323 ps
CPU time 5.64 seconds
Started Dec 31 12:47:42 PM PST 23
Finished Dec 31 12:47:51 PM PST 23
Peak memory 220852 kb
Host smart-9a8371bc-83c0-4d6c-822e-4800fc1a2566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809883959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.1809883959
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.3817792516
Short name T559
Test name
Test status
Simulation time 244666987 ps
CPU time 1.04 seconds
Started Dec 31 12:47:29 PM PST 23
Finished Dec 31 12:47:38 PM PST 23
Peak memory 216408 kb
Host smart-e566e454-0637-451d-b3fc-3c63625cd342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817792516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.3817792516
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.3697245090
Short name T482
Test name
Test status
Simulation time 112779036 ps
CPU time 0.73 seconds
Started Dec 31 12:47:30 PM PST 23
Finished Dec 31 12:47:38 PM PST 23
Peak memory 199092 kb
Host smart-650b22d8-c15e-4374-a592-8efbd37ce23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697245090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.3697245090
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.3313608195
Short name T360
Test name
Test status
Simulation time 1766459489 ps
CPU time 6.57 seconds
Started Dec 31 12:47:34 PM PST 23
Finished Dec 31 12:47:45 PM PST 23
Peak memory 199368 kb
Host smart-e2bf3821-717f-4ebb-99f4-50f296a645a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313608195 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.3313608195
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.2890610902
Short name T55
Test name
Test status
Simulation time 16512244069 ps
CPU time 32.21 seconds
Started Dec 31 12:47:23 PM PST 23
Finished Dec 31 12:47:57 PM PST 23
Peak memory 217312 kb
Host smart-b033a979-19ea-46fe-bc44-3a7c5df49dc3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890610902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.2890610902
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.3084271146
Short name T425
Test name
Test status
Simulation time 109316433 ps
CPU time 0.94 seconds
Started Dec 31 12:47:19 PM PST 23
Finished Dec 31 12:47:21 PM PST 23
Peak memory 199364 kb
Host smart-9137c8dc-8d1c-45f8-8876-4d3295a3e119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084271146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.3084271146
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.4211753586
Short name T503
Test name
Test status
Simulation time 205660791 ps
CPU time 1.33 seconds
Started Dec 31 12:47:54 PM PST 23
Finished Dec 31 12:47:56 PM PST 23
Peak memory 199392 kb
Host smart-06e379ac-2472-4897-b067-51552c8333fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211753586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.4211753586
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.1189680331
Short name T236
Test name
Test status
Simulation time 2965980892 ps
CPU time 10.48 seconds
Started Dec 31 12:47:24 PM PST 23
Finished Dec 31 12:47:36 PM PST 23
Peak memory 199512 kb
Host smart-6d38ad4a-a817-496f-92a5-334d35dcf4ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189680331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.1189680331
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.3370617406
Short name T410
Test name
Test status
Simulation time 519159821 ps
CPU time 2.49 seconds
Started Dec 31 12:47:23 PM PST 23
Finished Dec 31 12:47:27 PM PST 23
Peak memory 199228 kb
Host smart-3fcad176-a477-4edb-b9bd-a6d73827f671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370617406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.3370617406
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.3220989480
Short name T321
Test name
Test status
Simulation time 115078743 ps
CPU time 0.88 seconds
Started Dec 31 12:47:31 PM PST 23
Finished Dec 31 12:47:38 PM PST 23
Peak memory 199228 kb
Host smart-1f484ee6-848d-46a8-b243-8d51fbeff39f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220989480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.3220989480
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.1293343034
Short name T349
Test name
Test status
Simulation time 73403973 ps
CPU time 0.75 seconds
Started Dec 31 12:47:36 PM PST 23
Finished Dec 31 12:47:43 PM PST 23
Peak memory 199072 kb
Host smart-3acfd2f9-d18a-4d5b-ad23-477cdcb8adc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293343034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.1293343034
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.4040345154
Short name T409
Test name
Test status
Simulation time 244650911 ps
CPU time 1.17 seconds
Started Dec 31 12:47:42 PM PST 23
Finished Dec 31 12:47:46 PM PST 23
Peak memory 216480 kb
Host smart-4ac80a94-260d-420a-893c-de9a352a68eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040345154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.4040345154
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.2628780508
Short name T445
Test name
Test status
Simulation time 86784130 ps
CPU time 0.73 seconds
Started Dec 31 12:47:45 PM PST 23
Finished Dec 31 12:47:47 PM PST 23
Peak memory 199160 kb
Host smart-f49b9021-a8eb-49f2-92ae-536949e69c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628780508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.2628780508
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.2682861092
Short name T94
Test name
Test status
Simulation time 2043299352 ps
CPU time 7.26 seconds
Started Dec 31 12:48:06 PM PST 23
Finished Dec 31 12:48:14 PM PST 23
Peak memory 199564 kb
Host smart-6154a0ab-f327-4280-908d-1e5ae84d6c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682861092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.2682861092
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.4291488697
Short name T297
Test name
Test status
Simulation time 161027897 ps
CPU time 1.16 seconds
Started Dec 31 12:48:17 PM PST 23
Finished Dec 31 12:48:24 PM PST 23
Peak memory 199368 kb
Host smart-bd57d64e-fa28-41f7-8a19-8781938f91ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291488697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.4291488697
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.3751699551
Short name T70
Test name
Test status
Simulation time 246484781 ps
CPU time 1.42 seconds
Started Dec 31 12:48:18 PM PST 23
Finished Dec 31 12:48:23 PM PST 23
Peak memory 199472 kb
Host smart-ae5efafc-3c00-4fb0-aedd-44007f981bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751699551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.3751699551
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.3582041815
Short name T387
Test name
Test status
Simulation time 7539349422 ps
CPU time 26.33 seconds
Started Dec 31 12:47:35 PM PST 23
Finished Dec 31 12:48:08 PM PST 23
Peak memory 199588 kb
Host smart-0dffa5e6-13ef-49d1-8184-52fdb6113f8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582041815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.3582041815
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.158815347
Short name T73
Test name
Test status
Simulation time 144916444 ps
CPU time 1.77 seconds
Started Dec 31 12:47:39 PM PST 23
Finished Dec 31 12:47:45 PM PST 23
Peak memory 199296 kb
Host smart-85eb6650-7d04-445d-98ec-03bbb2392cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158815347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.158815347
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.17654018
Short name T362
Test name
Test status
Simulation time 69749315 ps
CPU time 0.74 seconds
Started Dec 31 12:47:42 PM PST 23
Finished Dec 31 12:47:45 PM PST 23
Peak memory 199264 kb
Host smart-23443df9-eedd-4810-8aab-0b4b63ad8747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17654018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.17654018
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.422084276
Short name T280
Test name
Test status
Simulation time 62813780 ps
CPU time 0.69 seconds
Started Dec 31 12:47:29 PM PST 23
Finished Dec 31 12:47:43 PM PST 23
Peak memory 199092 kb
Host smart-ee6a69ed-7807-456f-a935-23dc7e43cd61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422084276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.422084276
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.3575197233
Short name T516
Test name
Test status
Simulation time 1898287393 ps
CPU time 7.25 seconds
Started Dec 31 12:48:15 PM PST 23
Finished Dec 31 12:48:29 PM PST 23
Peak memory 221284 kb
Host smart-5ef5b4cf-8821-4f59-baf0-e29aad052ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575197233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.3575197233
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.2425257139
Short name T549
Test name
Test status
Simulation time 244245800 ps
CPU time 1.16 seconds
Started Dec 31 12:47:51 PM PST 23
Finished Dec 31 12:47:53 PM PST 23
Peak memory 216508 kb
Host smart-f5b9a3f9-894d-450d-b296-1e6c243ad4ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425257139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.2425257139
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.2907341260
Short name T491
Test name
Test status
Simulation time 101529381 ps
CPU time 0.83 seconds
Started Dec 31 12:48:09 PM PST 23
Finished Dec 31 12:48:13 PM PST 23
Peak memory 199064 kb
Host smart-90d270c9-7eae-44c9-ab55-f632e0d7f865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907341260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.2907341260
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.219245785
Short name T136
Test name
Test status
Simulation time 1163912972 ps
CPU time 4.7 seconds
Started Dec 31 12:48:12 PM PST 23
Finished Dec 31 12:48:19 PM PST 23
Peak memory 199352 kb
Host smart-f9b83fab-0a0b-470d-85ff-14f2bf3e1ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219245785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.219245785
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.1376183822
Short name T390
Test name
Test status
Simulation time 97286899 ps
CPU time 0.93 seconds
Started Dec 31 12:47:41 PM PST 23
Finished Dec 31 12:47:45 PM PST 23
Peak memory 199120 kb
Host smart-028b9f61-60a2-4508-b4e8-02d153b061f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376183822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.1376183822
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.1116360511
Short name T262
Test name
Test status
Simulation time 201622612 ps
CPU time 1.35 seconds
Started Dec 31 12:47:28 PM PST 23
Finished Dec 31 12:47:36 PM PST 23
Peak memory 199380 kb
Host smart-d49de07f-7030-42cc-9362-6fbfa0dfa5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116360511 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.1116360511
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.2022858650
Short name T472
Test name
Test status
Simulation time 8845981103 ps
CPU time 33.72 seconds
Started Dec 31 12:48:06 PM PST 23
Finished Dec 31 12:48:41 PM PST 23
Peak memory 199548 kb
Host smart-db5aa0c3-f1c0-436d-9a32-94f1315f8747
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022858650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.2022858650
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.860982986
Short name T400
Test name
Test status
Simulation time 137204092 ps
CPU time 1.61 seconds
Started Dec 31 12:48:02 PM PST 23
Finished Dec 31 12:48:06 PM PST 23
Peak memory 199312 kb
Host smart-9e0340f0-7290-4c60-9fe0-3b6d8a2c1c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860982986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.860982986
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.932389815
Short name T326
Test name
Test status
Simulation time 65536976 ps
CPU time 0.8 seconds
Started Dec 31 12:47:28 PM PST 23
Finished Dec 31 12:47:36 PM PST 23
Peak memory 199208 kb
Host smart-ea08710e-9632-4c6b-ad0f-98099cf26413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932389815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.932389815
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.2240705455
Short name T97
Test name
Test status
Simulation time 69523043 ps
CPU time 0.74 seconds
Started Dec 31 12:47:45 PM PST 23
Finished Dec 31 12:47:47 PM PST 23
Peak memory 199100 kb
Host smart-ba2c554b-6a7e-40c3-99e2-d95c47b3aec1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240705455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.2240705455
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.3874807407
Short name T163
Test name
Test status
Simulation time 1226038050 ps
CPU time 5.32 seconds
Started Dec 31 12:47:58 PM PST 23
Finished Dec 31 12:48:06 PM PST 23
Peak memory 215948 kb
Host smart-4134c1c3-29bb-47be-aaf5-34b53622418d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874807407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.3874807407
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.164709075
Short name T426
Test name
Test status
Simulation time 244411673 ps
CPU time 1.02 seconds
Started Dec 31 12:47:43 PM PST 23
Finished Dec 31 12:47:47 PM PST 23
Peak memory 216468 kb
Host smart-3e51b4e9-aa73-4271-b854-f448869e2c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164709075 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.164709075
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.3153944433
Short name T264
Test name
Test status
Simulation time 146456477 ps
CPU time 0.82 seconds
Started Dec 31 12:48:00 PM PST 23
Finished Dec 31 12:48:03 PM PST 23
Peak memory 199168 kb
Host smart-02567c24-07de-47a0-a771-1e202664a015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153944433 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.3153944433
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.2507529854
Short name T56
Test name
Test status
Simulation time 1498791697 ps
CPU time 5.31 seconds
Started Dec 31 12:48:03 PM PST 23
Finished Dec 31 12:48:10 PM PST 23
Peak memory 199516 kb
Host smart-874eee98-1159-4363-9554-2e75e8b12032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507529854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.2507529854
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.1005110750
Short name T327
Test name
Test status
Simulation time 179832695 ps
CPU time 1.14 seconds
Started Dec 31 12:47:54 PM PST 23
Finished Dec 31 12:47:56 PM PST 23
Peak memory 199408 kb
Host smart-22ca840d-ae37-4971-bfdd-f73b0214bd82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005110750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.1005110750
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.3759322742
Short name T341
Test name
Test status
Simulation time 114943580 ps
CPU time 1.12 seconds
Started Dec 31 12:47:50 PM PST 23
Finished Dec 31 12:47:53 PM PST 23
Peak memory 199472 kb
Host smart-3db9a0c2-b9c1-4b85-a1a9-676c4cbfa19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759322742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.3759322742
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.941527732
Short name T415
Test name
Test status
Simulation time 959579826 ps
CPU time 5 seconds
Started Dec 31 12:47:44 PM PST 23
Finished Dec 31 12:47:51 PM PST 23
Peak memory 199380 kb
Host smart-ae272948-b22f-405c-8713-6a1e40958edd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941527732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.941527732
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.435088366
Short name T487
Test name
Test status
Simulation time 345818132 ps
CPU time 2.31 seconds
Started Dec 31 12:47:31 PM PST 23
Finished Dec 31 12:47:40 PM PST 23
Peak memory 199192 kb
Host smart-4e236793-52e7-4321-a5d4-7b5c2c1dc6a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435088366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.435088366
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.3415675701
Short name T22
Test name
Test status
Simulation time 224250353 ps
CPU time 1.46 seconds
Started Dec 31 12:47:58 PM PST 23
Finished Dec 31 12:48:02 PM PST 23
Peak memory 199252 kb
Host smart-9d971712-718b-4312-b03c-aa1765e60b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415675701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.3415675701
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.4127741000
Short name T371
Test name
Test status
Simulation time 60445606 ps
CPU time 0.71 seconds
Started Dec 31 12:48:02 PM PST 23
Finished Dec 31 12:48:05 PM PST 23
Peak memory 199092 kb
Host smart-c379a08f-64e3-4e6d-9603-4ac3f8b104ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127741000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.4127741000
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.1242829986
Short name T568
Test name
Test status
Simulation time 2371499976 ps
CPU time 8.12 seconds
Started Dec 31 12:47:56 PM PST 23
Finished Dec 31 12:48:05 PM PST 23
Peak memory 217316 kb
Host smart-6b7119a3-a699-4b3b-ba88-8532e7ab882d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242829986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.1242829986
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.323092370
Short name T135
Test name
Test status
Simulation time 244413938 ps
CPU time 1.1 seconds
Started Dec 31 12:48:08 PM PST 23
Finished Dec 31 12:48:12 PM PST 23
Peak memory 216460 kb
Host smart-015ad409-75d3-4a21-b9e5-cf48fc55df5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323092370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.323092370
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.3455995256
Short name T492
Test name
Test status
Simulation time 77035720 ps
CPU time 0.7 seconds
Started Dec 31 12:48:05 PM PST 23
Finished Dec 31 12:48:08 PM PST 23
Peak memory 199128 kb
Host smart-006151d5-8d6a-4053-a69a-03951eea99f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455995256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.3455995256
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.676512575
Short name T299
Test name
Test status
Simulation time 894040442 ps
CPU time 4.66 seconds
Started Dec 31 12:48:00 PM PST 23
Finished Dec 31 12:48:07 PM PST 23
Peak memory 199700 kb
Host smart-636287d7-7b45-4784-a70c-5f6ffc6b62a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676512575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.676512575
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.2664488816
Short name T258
Test name
Test status
Simulation time 237814828 ps
CPU time 1.45 seconds
Started Dec 31 12:48:16 PM PST 23
Finished Dec 31 12:48:23 PM PST 23
Peak memory 199444 kb
Host smart-75618cb0-ffc9-496d-b892-1c9af08a634e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664488816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.2664488816
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.3437610995
Short name T305
Test name
Test status
Simulation time 712081010 ps
CPU time 3.16 seconds
Started Dec 31 12:48:03 PM PST 23
Finished Dec 31 12:48:08 PM PST 23
Peak memory 199480 kb
Host smart-5138e3e6-82ba-46ab-9a4d-a1a2cbd71539
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437610995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.3437610995
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.2027291345
Short name T478
Test name
Test status
Simulation time 124331549 ps
CPU time 1.53 seconds
Started Dec 31 12:47:40 PM PST 23
Finished Dec 31 12:47:45 PM PST 23
Peak memory 199224 kb
Host smart-055bd3ff-c5d7-462b-809a-471423de0eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027291345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.2027291345
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.3416138741
Short name T408
Test name
Test status
Simulation time 77203318 ps
CPU time 0.74 seconds
Started Dec 31 12:48:19 PM PST 23
Finished Dec 31 12:48:23 PM PST 23
Peak memory 199096 kb
Host smart-ab1276cf-20e4-4cf2-be88-537adfa4e536
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416138741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.3416138741
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.1261794212
Short name T597
Test name
Test status
Simulation time 1900163927 ps
CPU time 7.59 seconds
Started Dec 31 12:48:00 PM PST 23
Finished Dec 31 12:48:10 PM PST 23
Peak memory 217840 kb
Host smart-9e961c48-2087-4687-bf65-29affed6794d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261794212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.1261794212
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.4277792005
Short name T585
Test name
Test status
Simulation time 245065656 ps
CPU time 1.02 seconds
Started Dec 31 12:47:57 PM PST 23
Finished Dec 31 12:47:59 PM PST 23
Peak memory 216528 kb
Host smart-3eaed430-cbf3-4a76-bb2d-70b392363678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277792005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.4277792005
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.1796699213
Short name T16
Test name
Test status
Simulation time 244458180 ps
CPU time 0.93 seconds
Started Dec 31 12:47:47 PM PST 23
Finished Dec 31 12:47:50 PM PST 23
Peak memory 199108 kb
Host smart-5e68523d-2a6c-4925-b46f-748c939b529e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796699213 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.1796699213
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.1478167944
Short name T372
Test name
Test status
Simulation time 1658875784 ps
CPU time 5.48 seconds
Started Dec 31 12:47:52 PM PST 23
Finished Dec 31 12:47:58 PM PST 23
Peak memory 199428 kb
Host smart-791d769a-860b-4711-b8ba-6aba9b4b343c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478167944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.1478167944
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.222525279
Short name T385
Test name
Test status
Simulation time 164738697 ps
CPU time 1.12 seconds
Started Dec 31 12:48:08 PM PST 23
Finished Dec 31 12:48:11 PM PST 23
Peak memory 199244 kb
Host smart-86e58193-792f-4898-a362-4802d237427a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222525279 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.222525279
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.2901479499
Short name T540
Test name
Test status
Simulation time 264875852 ps
CPU time 1.48 seconds
Started Dec 31 12:47:26 PM PST 23
Finished Dec 31 12:47:34 PM PST 23
Peak memory 199388 kb
Host smart-0c037310-3b6b-4b42-aac0-2ba31a3b37ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901479499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.2901479499
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.3877329092
Short name T351
Test name
Test status
Simulation time 138362690 ps
CPU time 1.33 seconds
Started Dec 31 12:47:57 PM PST 23
Finished Dec 31 12:48:00 PM PST 23
Peak memory 199084 kb
Host smart-14e673ec-b955-4e63-804d-ba89b9d49ceb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877329092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.3877329092
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.710232079
Short name T338
Test name
Test status
Simulation time 344868300 ps
CPU time 2.11 seconds
Started Dec 31 12:47:49 PM PST 23
Finished Dec 31 12:47:53 PM PST 23
Peak memory 199280 kb
Host smart-1fcb1389-7c1c-4259-bce2-04a7c1003928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710232079 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.710232079
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.3079930402
Short name T323
Test name
Test status
Simulation time 210655867 ps
CPU time 1.26 seconds
Started Dec 31 12:48:14 PM PST 23
Finished Dec 31 12:48:21 PM PST 23
Peak memory 199400 kb
Host smart-0eccbe83-6b55-4fe6-bf6c-60e93b33daa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079930402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.3079930402
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.825807848
Short name T416
Test name
Test status
Simulation time 63230853 ps
CPU time 0.68 seconds
Started Dec 31 12:48:16 PM PST 23
Finished Dec 31 12:48:23 PM PST 23
Peak memory 199220 kb
Host smart-871edac9-ef54-40ed-80a2-8444f6a97f2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825807848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.825807848
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.3655748127
Short name T27
Test name
Test status
Simulation time 2325216266 ps
CPU time 7.49 seconds
Started Dec 31 12:48:01 PM PST 23
Finished Dec 31 12:48:11 PM PST 23
Peak memory 217296 kb
Host smart-d9b857bd-3480-40ae-8098-a7f3df8ef859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655748127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.3655748127
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.544471270
Short name T532
Test name
Test status
Simulation time 243941683 ps
CPU time 1.06 seconds
Started Dec 31 12:48:29 PM PST 23
Finished Dec 31 12:48:32 PM PST 23
Peak memory 216564 kb
Host smart-5e3ffc81-fc0f-4dfe-9544-648d7739017f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544471270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.544471270
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.4284551174
Short name T432
Test name
Test status
Simulation time 75532190 ps
CPU time 0.71 seconds
Started Dec 31 12:47:49 PM PST 23
Finished Dec 31 12:47:51 PM PST 23
Peak memory 199132 kb
Host smart-a2e181dd-8de0-4bf0-8e67-2b6ac21ea876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284551174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.4284551174
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.398212971
Short name T407
Test name
Test status
Simulation time 661789167 ps
CPU time 3.77 seconds
Started Dec 31 12:48:53 PM PST 23
Finished Dec 31 12:48:58 PM PST 23
Peak memory 199456 kb
Host smart-2bd5271c-4912-49fb-9ae9-4661f2610294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398212971 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.398212971
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.457795001
Short name T130
Test name
Test status
Simulation time 159165873 ps
CPU time 1.23 seconds
Started Dec 31 12:47:52 PM PST 23
Finished Dec 31 12:47:54 PM PST 23
Peak memory 199324 kb
Host smart-dd5f41cf-6dbf-432f-8b83-a41a54acc10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457795001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.457795001
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.1689843984
Short name T263
Test name
Test status
Simulation time 244776450 ps
CPU time 1.44 seconds
Started Dec 31 12:48:04 PM PST 23
Finished Dec 31 12:48:08 PM PST 23
Peak memory 199428 kb
Host smart-5a4edffb-ee2c-4326-bcd3-15a7e0c818ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689843984 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.1689843984
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.2263726822
Short name T611
Test name
Test status
Simulation time 5880290504 ps
CPU time 18.13 seconds
Started Dec 31 12:48:10 PM PST 23
Finished Dec 31 12:48:32 PM PST 23
Peak memory 199456 kb
Host smart-ad5ad38c-ac93-406e-89d8-5b35e5234f03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263726822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.2263726822
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.3777161673
Short name T259
Test name
Test status
Simulation time 405993799 ps
CPU time 2.27 seconds
Started Dec 31 12:48:13 PM PST 23
Finished Dec 31 12:48:21 PM PST 23
Peak memory 199152 kb
Host smart-f9046fae-4142-43ca-8c0a-5c4e37594a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777161673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.3777161673
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.1220885680
Short name T564
Test name
Test status
Simulation time 156287400 ps
CPU time 1.01 seconds
Started Dec 31 12:48:07 PM PST 23
Finished Dec 31 12:48:10 PM PST 23
Peak memory 199420 kb
Host smart-52ed8cc5-2fac-4c30-85b1-b82d004f4a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220885680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.1220885680
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.3841719891
Short name T138
Test name
Test status
Simulation time 67940373 ps
CPU time 0.72 seconds
Started Dec 31 12:48:43 PM PST 23
Finished Dec 31 12:48:46 PM PST 23
Peak memory 199164 kb
Host smart-7e95324a-741e-4140-8471-6e93505fc8fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841719891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.3841719891
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.91631733
Short name T576
Test name
Test status
Simulation time 1224252845 ps
CPU time 5.98 seconds
Started Dec 31 12:48:40 PM PST 23
Finished Dec 31 12:48:48 PM PST 23
Peak memory 220700 kb
Host smart-b05bfba2-be5e-45cb-a9fc-c8e3db93d360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91631733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.91631733
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.1041692397
Short name T377
Test name
Test status
Simulation time 244249037 ps
CPU time 1.18 seconds
Started Dec 31 12:48:52 PM PST 23
Finished Dec 31 12:48:54 PM PST 23
Peak memory 216536 kb
Host smart-f7074ead-0225-4134-b8ad-cf425579c517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041692397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.1041692397
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.243841173
Short name T272
Test name
Test status
Simulation time 90449402 ps
CPU time 0.73 seconds
Started Dec 31 12:48:28 PM PST 23
Finished Dec 31 12:48:31 PM PST 23
Peak memory 199132 kb
Host smart-4b2f8ab2-8a65-4041-9b23-81a46ced8f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243841173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.243841173
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.1245994817
Short name T500
Test name
Test status
Simulation time 1661303912 ps
CPU time 6.22 seconds
Started Dec 31 12:48:15 PM PST 23
Finished Dec 31 12:48:29 PM PST 23
Peak memory 199440 kb
Host smart-043d664e-c687-46ea-a50f-a122ad05dd03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245994817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.1245994817
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.2491168459
Short name T512
Test name
Test status
Simulation time 154740742 ps
CPU time 1.07 seconds
Started Dec 31 12:48:23 PM PST 23
Finished Dec 31 12:48:28 PM PST 23
Peak memory 199332 kb
Host smart-77529a7a-dd94-4582-ad7a-8292a0d20672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491168459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.2491168459
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.3888980471
Short name T524
Test name
Test status
Simulation time 239034264 ps
CPU time 1.5 seconds
Started Dec 31 12:48:15 PM PST 23
Finished Dec 31 12:48:24 PM PST 23
Peak memory 199476 kb
Host smart-1364a21e-d327-4a90-a875-b766b24567d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888980471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.3888980471
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.2197630651
Short name T562
Test name
Test status
Simulation time 6166588276 ps
CPU time 23.27 seconds
Started Dec 31 12:48:40 PM PST 23
Finished Dec 31 12:49:05 PM PST 23
Peak memory 199620 kb
Host smart-50db3c7c-2582-42ad-9eaf-5df42964088c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197630651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.2197630651
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.2386180290
Short name T468
Test name
Test status
Simulation time 492986522 ps
CPU time 2.39 seconds
Started Dec 31 12:48:38 PM PST 23
Finished Dec 31 12:48:41 PM PST 23
Peak memory 199304 kb
Host smart-fb330890-0926-4249-a0b3-b8a97765f8be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386180290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.2386180290
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.929730905
Short name T430
Test name
Test status
Simulation time 172114716 ps
CPU time 1.25 seconds
Started Dec 31 12:48:59 PM PST 23
Finished Dec 31 12:49:01 PM PST 23
Peak memory 199528 kb
Host smart-c1c1211f-0905-4e42-9398-eeb42518780b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929730905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.929730905
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.437815753
Short name T574
Test name
Test status
Simulation time 66497831 ps
CPU time 0.73 seconds
Started Dec 31 12:48:33 PM PST 23
Finished Dec 31 12:48:35 PM PST 23
Peak memory 199176 kb
Host smart-0ce305bb-8145-4150-888f-266b738d6891
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437815753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.437815753
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.2928478319
Short name T389
Test name
Test status
Simulation time 1227452004 ps
CPU time 5.15 seconds
Started Dec 31 12:48:55 PM PST 23
Finished Dec 31 12:49:01 PM PST 23
Peak memory 228936 kb
Host smart-14ad1279-3138-4078-a1ab-cbedb16f1914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928478319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.2928478319
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.1764480968
Short name T609
Test name
Test status
Simulation time 244820503 ps
CPU time 1.12 seconds
Started Dec 31 12:48:05 PM PST 23
Finished Dec 31 12:48:08 PM PST 23
Peak memory 216500 kb
Host smart-7b1c6ab7-34e1-4247-b018-1a22f9988293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764480968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.1764480968
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.3645768155
Short name T322
Test name
Test status
Simulation time 129485311 ps
CPU time 0.76 seconds
Started Dec 31 12:49:05 PM PST 23
Finished Dec 31 12:49:07 PM PST 23
Peak memory 199108 kb
Host smart-796de3e2-cee2-4831-82dd-a077bafaaf4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645768155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.3645768155
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.2121414191
Short name T494
Test name
Test status
Simulation time 1894212946 ps
CPU time 6.45 seconds
Started Dec 31 12:49:16 PM PST 23
Finished Dec 31 12:49:24 PM PST 23
Peak memory 199536 kb
Host smart-17ed1d50-b2db-4f53-a52d-f36d4fa43262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121414191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.2121414191
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.1074826516
Short name T270
Test name
Test status
Simulation time 147780054 ps
CPU time 1.05 seconds
Started Dec 31 12:48:28 PM PST 23
Finished Dec 31 12:48:31 PM PST 23
Peak memory 199208 kb
Host smart-67e5c686-3086-438a-a971-af6399e2fb39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074826516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.1074826516
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.2053079434
Short name T365
Test name
Test status
Simulation time 250124245 ps
CPU time 1.52 seconds
Started Dec 31 12:48:55 PM PST 23
Finished Dec 31 12:48:58 PM PST 23
Peak memory 199524 kb
Host smart-6797f2a1-f5fc-4863-8a36-6daf68411f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053079434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.2053079434
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.4232660813
Short name T69
Test name
Test status
Simulation time 2464599027 ps
CPU time 10.95 seconds
Started Dec 31 12:48:20 PM PST 23
Finished Dec 31 12:48:34 PM PST 23
Peak memory 199636 kb
Host smart-f9451e01-6d02-4765-9440-90e3de46aee5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232660813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.4232660813
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.937039519
Short name T283
Test name
Test status
Simulation time 311782564 ps
CPU time 2.02 seconds
Started Dec 31 12:49:00 PM PST 23
Finished Dec 31 12:49:02 PM PST 23
Peak memory 199336 kb
Host smart-63e0b008-ab06-4c65-b0d2-635dc3527f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937039519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.937039519
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.3203377047
Short name T560
Test name
Test status
Simulation time 257497178 ps
CPU time 1.46 seconds
Started Dec 31 12:49:14 PM PST 23
Finished Dec 31 12:49:17 PM PST 23
Peak memory 199364 kb
Host smart-54d323a3-138d-4fbe-a5d7-2867703cf2b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203377047 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.3203377047
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.1656170840
Short name T50
Test name
Test status
Simulation time 77114249 ps
CPU time 0.77 seconds
Started Dec 31 12:48:04 PM PST 23
Finished Dec 31 12:48:06 PM PST 23
Peak memory 199156 kb
Host smart-6bdcb9e9-3ebb-4cb5-a6f0-ee39ffd14538
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656170840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.1656170840
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.3162492013
Short name T519
Test name
Test status
Simulation time 2357507046 ps
CPU time 9.21 seconds
Started Dec 31 12:48:13 PM PST 23
Finished Dec 31 12:48:29 PM PST 23
Peak memory 218064 kb
Host smart-cb91a4ea-f63b-4810-90d7-d380cb3310b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162492013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.3162492013
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.753510412
Short name T353
Test name
Test status
Simulation time 244731491 ps
CPU time 1.05 seconds
Started Dec 31 12:48:39 PM PST 23
Finished Dec 31 12:48:41 PM PST 23
Peak memory 216412 kb
Host smart-09774ec6-07d2-4ed3-805e-e0b74a224b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753510412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.753510412
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.3086245709
Short name T273
Test name
Test status
Simulation time 169867937 ps
CPU time 0.82 seconds
Started Dec 31 12:48:13 PM PST 23
Finished Dec 31 12:48:16 PM PST 23
Peak memory 199192 kb
Host smart-fb3c9c86-598c-4e2a-91be-d5fa80834f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086245709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.3086245709
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.3782520145
Short name T367
Test name
Test status
Simulation time 947421168 ps
CPU time 4.62 seconds
Started Dec 31 12:48:00 PM PST 23
Finished Dec 31 12:48:07 PM PST 23
Peak memory 199448 kb
Host smart-f331e716-8b71-4c41-bb17-a12fe0aac215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782520145 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.3782520145
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.3254099421
Short name T437
Test name
Test status
Simulation time 144025136 ps
CPU time 1.07 seconds
Started Dec 31 12:48:22 PM PST 23
Finished Dec 31 12:48:28 PM PST 23
Peak memory 199324 kb
Host smart-bf740fde-a31e-495d-80d5-64e2a3182f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254099421 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.3254099421
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.1997667698
Short name T495
Test name
Test status
Simulation time 223997733 ps
CPU time 1.46 seconds
Started Dec 31 12:48:10 PM PST 23
Finished Dec 31 12:48:15 PM PST 23
Peak memory 199444 kb
Host smart-0d2bc7cf-fb99-4220-9dd9-91d247b2f0ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997667698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.1997667698
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.3850745068
Short name T517
Test name
Test status
Simulation time 2866345009 ps
CPU time 12.86 seconds
Started Dec 31 12:48:26 PM PST 23
Finished Dec 31 12:48:41 PM PST 23
Peak memory 199564 kb
Host smart-b24bd095-3779-4241-9fd7-4e10ceeeb281
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850745068 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.3850745068
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.2883639651
Short name T291
Test name
Test status
Simulation time 479960475 ps
CPU time 2.57 seconds
Started Dec 31 12:48:15 PM PST 23
Finished Dec 31 12:48:25 PM PST 23
Peak memory 199228 kb
Host smart-2353a266-187e-4ba5-8d61-04e85ac85db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883639651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.2883639651
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.356947753
Short name T274
Test name
Test status
Simulation time 215361701 ps
CPU time 1.24 seconds
Started Dec 31 12:48:12 PM PST 23
Finished Dec 31 12:48:16 PM PST 23
Peak memory 199336 kb
Host smart-05fe40fa-bce1-4046-84d2-2e1e179dcbe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356947753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.356947753
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.953494211
Short name T350
Test name
Test status
Simulation time 151116534 ps
CPU time 0.88 seconds
Started Dec 31 12:48:03 PM PST 23
Finished Dec 31 12:48:05 PM PST 23
Peak memory 199140 kb
Host smart-01140eac-fc7e-4322-9444-4fc9484aeb9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953494211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.953494211
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.2228806313
Short name T35
Test name
Test status
Simulation time 2355638580 ps
CPU time 9.31 seconds
Started Dec 31 12:48:08 PM PST 23
Finished Dec 31 12:48:19 PM PST 23
Peak memory 217372 kb
Host smart-75ef8fa6-b9ad-4a41-a376-1757243decf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228806313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.2228806313
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.3596109314
Short name T428
Test name
Test status
Simulation time 244703458 ps
CPU time 1.1 seconds
Started Dec 31 12:48:35 PM PST 23
Finished Dec 31 12:48:38 PM PST 23
Peak memory 216572 kb
Host smart-113bf183-05b5-403f-9c83-ac9cdfd1b42f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596109314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.3596109314
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.117473119
Short name T421
Test name
Test status
Simulation time 206984858 ps
CPU time 0.94 seconds
Started Dec 31 12:47:51 PM PST 23
Finished Dec 31 12:47:53 PM PST 23
Peak memory 199124 kb
Host smart-b3692cef-2816-4acf-a964-f3bef709a785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117473119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.117473119
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.3613362645
Short name T522
Test name
Test status
Simulation time 1731627408 ps
CPU time 6.11 seconds
Started Dec 31 12:48:52 PM PST 23
Finished Dec 31 12:48:59 PM PST 23
Peak memory 199408 kb
Host smart-9ed191ec-88b2-460b-a080-3df23b3ca6fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613362645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.3613362645
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.2890231465
Short name T563
Test name
Test status
Simulation time 164327427 ps
CPU time 1.08 seconds
Started Dec 31 12:48:18 PM PST 23
Finished Dec 31 12:48:23 PM PST 23
Peak memory 199392 kb
Host smart-31f26b28-f168-40d3-b6b1-35da5e49890e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890231465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.2890231465
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.723598649
Short name T461
Test name
Test status
Simulation time 249236005 ps
CPU time 1.47 seconds
Started Dec 31 12:48:07 PM PST 23
Finished Dec 31 12:48:10 PM PST 23
Peak memory 199476 kb
Host smart-581f03bd-0b3f-4da1-bcb9-6f6a24cbe64b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723598649 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.723598649
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.25919872
Short name T160
Test name
Test status
Simulation time 6383536002 ps
CPU time 24.05 seconds
Started Dec 31 12:48:55 PM PST 23
Finished Dec 31 12:49:19 PM PST 23
Peak memory 199532 kb
Host smart-ba42f4ef-d602-4b27-90ec-42668aba0867
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25919872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.25919872
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.4251063244
Short name T488
Test name
Test status
Simulation time 377667496 ps
CPU time 2.03 seconds
Started Dec 31 12:48:26 PM PST 23
Finished Dec 31 12:48:31 PM PST 23
Peak memory 199236 kb
Host smart-2d0b3035-cf30-46dd-8a25-aebfab643f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251063244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.4251063244
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.778098561
Short name T610
Test name
Test status
Simulation time 157664678 ps
CPU time 1.1 seconds
Started Dec 31 12:48:10 PM PST 23
Finished Dec 31 12:48:14 PM PST 23
Peak memory 199252 kb
Host smart-5f4b041f-e2cd-4e69-a73b-d093ddcaa99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778098561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.778098561
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.4061902184
Short name T440
Test name
Test status
Simulation time 63901159 ps
CPU time 0.7 seconds
Started Dec 31 12:47:28 PM PST 23
Finished Dec 31 12:47:35 PM PST 23
Peak memory 199144 kb
Host smart-22dbdd71-c5d9-4d6b-9ad2-82b560d2eaf9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061902184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.4061902184
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.1691745838
Short name T328
Test name
Test status
Simulation time 1225838021 ps
CPU time 5.8 seconds
Started Dec 31 12:47:28 PM PST 23
Finished Dec 31 12:47:42 PM PST 23
Peak memory 217164 kb
Host smart-f436dcb2-d347-4524-a6ec-4cca99bcbac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691745838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.1691745838
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.869414402
Short name T340
Test name
Test status
Simulation time 246537107 ps
CPU time 1.03 seconds
Started Dec 31 12:47:56 PM PST 23
Finished Dec 31 12:47:58 PM PST 23
Peak memory 216440 kb
Host smart-c642052c-bf95-40a4-9373-f8ea0147b2ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869414402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.869414402
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.2551342584
Short name T530
Test name
Test status
Simulation time 182528389 ps
CPU time 0.94 seconds
Started Dec 31 12:47:24 PM PST 23
Finished Dec 31 12:47:27 PM PST 23
Peak memory 199112 kb
Host smart-e1adfd32-c8cb-4395-888b-1b3725a8b86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551342584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.2551342584
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.527728254
Short name T352
Test name
Test status
Simulation time 923952112 ps
CPU time 4.03 seconds
Started Dec 31 12:47:34 PM PST 23
Finished Dec 31 12:47:44 PM PST 23
Peak memory 199440 kb
Host smart-bf74d332-fb53-4107-843f-e75f05ac2965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527728254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.527728254
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.3299288763
Short name T54
Test name
Test status
Simulation time 16694488070 ps
CPU time 24.55 seconds
Started Dec 31 12:47:24 PM PST 23
Finished Dec 31 12:47:51 PM PST 23
Peak memory 217300 kb
Host smart-f201317b-3292-422c-b9d5-4b6cb1ad6d47
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299288763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.3299288763
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.560670653
Short name T337
Test name
Test status
Simulation time 187404106 ps
CPU time 1.16 seconds
Started Dec 31 12:47:29 PM PST 23
Finished Dec 31 12:47:44 PM PST 23
Peak memory 199228 kb
Host smart-aad910b0-efa5-492b-a9f9-6ef6871b9cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560670653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.560670653
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.1683687096
Short name T600
Test name
Test status
Simulation time 262324886 ps
CPU time 1.57 seconds
Started Dec 31 12:47:40 PM PST 23
Finished Dec 31 12:47:45 PM PST 23
Peak memory 199472 kb
Host smart-18b22da1-7d59-4287-a9ff-7ef684e92fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683687096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.1683687096
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.1833650420
Short name T399
Test name
Test status
Simulation time 6023404861 ps
CPU time 24.89 seconds
Started Dec 31 12:47:36 PM PST 23
Finished Dec 31 12:48:07 PM PST 23
Peak memory 199604 kb
Host smart-c1c5b563-9e14-473a-8db7-cadd03c9b04b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833650420 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.1833650420
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.2123046133
Short name T571
Test name
Test status
Simulation time 339988525 ps
CPU time 2.12 seconds
Started Dec 31 12:47:59 PM PST 23
Finished Dec 31 12:48:04 PM PST 23
Peak memory 199200 kb
Host smart-e9426f69-8f94-4153-81e4-35a2ee152f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123046133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.2123046133
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.3229027607
Short name T250
Test name
Test status
Simulation time 236416558 ps
CPU time 1.44 seconds
Started Dec 31 12:47:21 PM PST 23
Finished Dec 31 12:47:23 PM PST 23
Peak memory 199316 kb
Host smart-058235db-cbab-4f43-893b-423ae734ea6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229027607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.3229027607
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.451012407
Short name T319
Test name
Test status
Simulation time 74827035 ps
CPU time 0.78 seconds
Started Dec 31 12:49:16 PM PST 23
Finished Dec 31 12:49:19 PM PST 23
Peak memory 199172 kb
Host smart-f5d0eca7-7daf-4a9b-a408-0331ff771852
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451012407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.451012407
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.1170757625
Short name T617
Test name
Test status
Simulation time 2190178719 ps
CPU time 7.87 seconds
Started Dec 31 12:47:50 PM PST 23
Finished Dec 31 12:48:00 PM PST 23
Peak memory 217260 kb
Host smart-debe07fc-ab3f-4fd4-9a9e-c11a1cf4556c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170757625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.1170757625
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.1071134277
Short name T463
Test name
Test status
Simulation time 244244671 ps
CPU time 1.14 seconds
Started Dec 31 12:48:07 PM PST 23
Finished Dec 31 12:48:11 PM PST 23
Peak memory 216772 kb
Host smart-ddc54619-66a4-4458-98b6-b7fd4b88fed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071134277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.1071134277
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.3974559367
Short name T507
Test name
Test status
Simulation time 195569243 ps
CPU time 0.87 seconds
Started Dec 31 12:48:06 PM PST 23
Finished Dec 31 12:48:08 PM PST 23
Peak memory 199072 kb
Host smart-7eb13ce9-cc98-4df6-a1f6-cd1f5f150b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974559367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.3974559367
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.1946310285
Short name T21
Test name
Test status
Simulation time 960286895 ps
CPU time 5.09 seconds
Started Dec 31 12:48:17 PM PST 23
Finished Dec 31 12:48:27 PM PST 23
Peak memory 199488 kb
Host smart-2147cc51-6898-4dc0-baf4-d405abdb38b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946310285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.1946310285
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.1233543817
Short name T578
Test name
Test status
Simulation time 173118637 ps
CPU time 1.18 seconds
Started Dec 31 12:48:08 PM PST 23
Finished Dec 31 12:48:12 PM PST 23
Peak memory 199228 kb
Host smart-287d2da2-818e-4e07-b61b-1028088cb36f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233543817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.1233543817
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.4152033054
Short name T582
Test name
Test status
Simulation time 187823560 ps
CPU time 1.47 seconds
Started Dec 31 12:48:42 PM PST 23
Finished Dec 31 12:48:45 PM PST 23
Peak memory 199408 kb
Host smart-01ba0585-afa1-4fff-8d0b-65399c84362a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152033054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.4152033054
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.399605995
Short name T100
Test name
Test status
Simulation time 12388921339 ps
CPU time 46.42 seconds
Started Dec 31 12:48:08 PM PST 23
Finished Dec 31 12:48:57 PM PST 23
Peak memory 199632 kb
Host smart-0297aedc-a7c7-47c7-81e1-5efc6287da2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399605995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.399605995
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.3990738661
Short name T151
Test name
Test status
Simulation time 128239083 ps
CPU time 1.49 seconds
Started Dec 31 12:48:09 PM PST 23
Finished Dec 31 12:48:13 PM PST 23
Peak memory 199380 kb
Host smart-f6aa0ade-1727-4204-a80c-fa05336acd2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990738661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.3990738661
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.2966932384
Short name T412
Test name
Test status
Simulation time 177356384 ps
CPU time 1.1 seconds
Started Dec 31 12:48:44 PM PST 23
Finished Dec 31 12:48:47 PM PST 23
Peak memory 199360 kb
Host smart-4e94ba57-7e43-43a8-9c7c-0adb02fc0479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966932384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.2966932384
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.2692355734
Short name T544
Test name
Test status
Simulation time 56832037 ps
CPU time 0.69 seconds
Started Dec 31 12:48:43 PM PST 23
Finished Dec 31 12:48:46 PM PST 23
Peak memory 199136 kb
Host smart-7e51be78-2acb-4150-a70e-90bafb39e82f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692355734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.2692355734
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.1738700962
Short name T598
Test name
Test status
Simulation time 1907664624 ps
CPU time 6.89 seconds
Started Dec 31 12:48:12 PM PST 23
Finished Dec 31 12:48:22 PM PST 23
Peak memory 216748 kb
Host smart-465779a4-2839-4c33-9b21-8f886d2e4d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738700962 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.1738700962
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.366249450
Short name T474
Test name
Test status
Simulation time 243820249 ps
CPU time 1.05 seconds
Started Dec 31 12:48:34 PM PST 23
Finished Dec 31 12:48:37 PM PST 23
Peak memory 216576 kb
Host smart-e43ae6b7-bec4-4dbc-bfb9-38cd87969066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366249450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.366249450
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.3986481003
Short name T5
Test name
Test status
Simulation time 153954729 ps
CPU time 0.78 seconds
Started Dec 31 12:47:53 PM PST 23
Finished Dec 31 12:47:55 PM PST 23
Peak memory 199152 kb
Host smart-7ec0c888-b588-48c5-913a-4282a3bc2d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986481003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.3986481003
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.1861433149
Short name T431
Test name
Test status
Simulation time 1884290751 ps
CPU time 7.52 seconds
Started Dec 31 12:48:21 PM PST 23
Finished Dec 31 12:48:34 PM PST 23
Peak memory 199524 kb
Host smart-3707e8a0-46e8-4d74-b729-95045713b147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861433149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.1861433149
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.2377285154
Short name T286
Test name
Test status
Simulation time 103233027 ps
CPU time 0.97 seconds
Started Dec 31 12:48:13 PM PST 23
Finished Dec 31 12:48:19 PM PST 23
Peak memory 199408 kb
Host smart-4e798109-b855-4b15-a783-67484a9e7193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377285154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.2377285154
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.2008129198
Short name T541
Test name
Test status
Simulation time 203242484 ps
CPU time 1.41 seconds
Started Dec 31 12:47:57 PM PST 23
Finished Dec 31 12:48:00 PM PST 23
Peak memory 199488 kb
Host smart-6f9fe9d1-b390-45cd-8c94-464c92303f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008129198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.2008129198
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.616315307
Short name T314
Test name
Test status
Simulation time 3050091655 ps
CPU time 12.15 seconds
Started Dec 31 12:48:18 PM PST 23
Finished Dec 31 12:48:34 PM PST 23
Peak memory 199620 kb
Host smart-1ce9fb51-7bfc-4a29-bded-562662ce9494
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616315307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.616315307
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.1219327728
Short name T357
Test name
Test status
Simulation time 141230742 ps
CPU time 1.73 seconds
Started Dec 31 12:48:55 PM PST 23
Finished Dec 31 12:48:58 PM PST 23
Peak memory 199336 kb
Host smart-f96d2a60-8c33-492f-9b34-9ade313596c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219327728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.1219327728
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.163331896
Short name T386
Test name
Test status
Simulation time 246499624 ps
CPU time 1.42 seconds
Started Dec 31 12:49:01 PM PST 23
Finished Dec 31 12:49:03 PM PST 23
Peak memory 199432 kb
Host smart-16e40d38-de9c-4935-847d-9da18443f436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163331896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.163331896
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.2234843783
Short name T558
Test name
Test status
Simulation time 84327301 ps
CPU time 0.76 seconds
Started Dec 31 12:48:16 PM PST 23
Finished Dec 31 12:48:23 PM PST 23
Peak memory 199156 kb
Host smart-6a7ec867-23c5-4884-8b25-194a34793237
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234843783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.2234843783
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.1189172195
Short name T581
Test name
Test status
Simulation time 2358919732 ps
CPU time 7.92 seconds
Started Dec 31 12:48:21 PM PST 23
Finished Dec 31 12:48:35 PM PST 23
Peak memory 217176 kb
Host smart-a8c9ce92-c9eb-48ac-915c-38345801a61d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189172195 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.1189172195
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.2779746410
Short name T485
Test name
Test status
Simulation time 244239877 ps
CPU time 1.03 seconds
Started Dec 31 12:48:30 PM PST 23
Finished Dec 31 12:48:32 PM PST 23
Peak memory 216536 kb
Host smart-83244990-2820-4775-9d31-fdc9364f96bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779746410 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.2779746410
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.1427246807
Short name T336
Test name
Test status
Simulation time 186452412 ps
CPU time 0.83 seconds
Started Dec 31 12:47:46 PM PST 23
Finished Dec 31 12:47:48 PM PST 23
Peak memory 199332 kb
Host smart-a12fc4a6-e479-4ec0-b272-ad10d54cb69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427246807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.1427246807
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.2987905810
Short name T441
Test name
Test status
Simulation time 854955130 ps
CPU time 3.84 seconds
Started Dec 31 12:48:16 PM PST 23
Finished Dec 31 12:48:26 PM PST 23
Peak memory 199416 kb
Host smart-1bf900b3-95e9-48ce-a5b5-9ec70aa69f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987905810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.2987905810
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.1505065238
Short name T133
Test name
Test status
Simulation time 188483823 ps
CPU time 1.19 seconds
Started Dec 31 12:48:28 PM PST 23
Finished Dec 31 12:48:31 PM PST 23
Peak memory 199296 kb
Host smart-38c2b600-076f-4551-9b5b-f7696f104f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505065238 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.1505065238
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.28063702
Short name T616
Test name
Test status
Simulation time 110705690 ps
CPU time 1.12 seconds
Started Dec 31 12:48:09 PM PST 23
Finished Dec 31 12:48:14 PM PST 23
Peak memory 199420 kb
Host smart-f1f4330f-81d9-4454-bd4f-6a157f265556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28063702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.28063702
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.715431449
Short name T429
Test name
Test status
Simulation time 6590001712 ps
CPU time 24.01 seconds
Started Dec 31 12:48:37 PM PST 23
Finished Dec 31 12:49:02 PM PST 23
Peak memory 199484 kb
Host smart-f7558039-c3c7-46b4-be35-d864aa53c45e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715431449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.715431449
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.422893551
Short name T523
Test name
Test status
Simulation time 151361999 ps
CPU time 1.78 seconds
Started Dec 31 12:47:52 PM PST 23
Finished Dec 31 12:47:55 PM PST 23
Peak memory 199272 kb
Host smart-bafdcab6-bf3a-4c68-9d41-00b945b70cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422893551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.422893551
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.1629210050
Short name T260
Test name
Test status
Simulation time 139989835 ps
CPU time 1.02 seconds
Started Dec 31 12:48:42 PM PST 23
Finished Dec 31 12:48:44 PM PST 23
Peak memory 199360 kb
Host smart-6dca3188-9d5a-4de6-b15a-6c2e13338b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629210050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.1629210050
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.3051269712
Short name T477
Test name
Test status
Simulation time 57954335 ps
CPU time 0.69 seconds
Started Dec 31 12:49:20 PM PST 23
Finished Dec 31 12:49:22 PM PST 23
Peak memory 199088 kb
Host smart-0e66c99f-9c6c-4997-b46a-656b88ccef1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051269712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.3051269712
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.912548848
Short name T30
Test name
Test status
Simulation time 1886796693 ps
CPU time 7.28 seconds
Started Dec 31 12:48:44 PM PST 23
Finished Dec 31 12:49:02 PM PST 23
Peak memory 217176 kb
Host smart-b65653d3-78d7-4e36-9492-7a29a786d1e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912548848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.912548848
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.3525565976
Short name T134
Test name
Test status
Simulation time 245375662 ps
CPU time 1.03 seconds
Started Dec 31 12:48:51 PM PST 23
Finished Dec 31 12:48:54 PM PST 23
Peak memory 216528 kb
Host smart-47507c8d-38b6-496d-b9c0-bc60fec0708a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525565976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.3525565976
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.2181640075
Short name T382
Test name
Test status
Simulation time 170152438 ps
CPU time 0.9 seconds
Started Dec 31 12:48:42 PM PST 23
Finished Dec 31 12:48:49 PM PST 23
Peak memory 199212 kb
Host smart-b0c99c92-6d7d-45d2-a8c7-c5b784586a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181640075 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.2181640075
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.4177209122
Short name T93
Test name
Test status
Simulation time 1619540298 ps
CPU time 6.37 seconds
Started Dec 31 12:48:49 PM PST 23
Finished Dec 31 12:48:57 PM PST 23
Peak memory 199572 kb
Host smart-eba585c4-54e4-4959-80dd-c8b704e97687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177209122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.4177209122
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.2196819009
Short name T332
Test name
Test status
Simulation time 108241462 ps
CPU time 0.97 seconds
Started Dec 31 12:49:20 PM PST 23
Finished Dec 31 12:49:22 PM PST 23
Peak memory 199364 kb
Host smart-b6156a17-5d59-48b6-b240-f2cce642235a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196819009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.2196819009
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.20215253
Short name T348
Test name
Test status
Simulation time 221953612 ps
CPU time 1.4 seconds
Started Dec 31 12:48:46 PM PST 23
Finished Dec 31 12:48:54 PM PST 23
Peak memory 199496 kb
Host smart-4fd8d260-a4bf-453c-a74d-227938ad010c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20215253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.20215253
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.1939530819
Short name T464
Test name
Test status
Simulation time 4758938918 ps
CPU time 20.6 seconds
Started Dec 31 12:48:22 PM PST 23
Finished Dec 31 12:48:47 PM PST 23
Peak memory 199564 kb
Host smart-4c399d9f-1115-429e-b4d7-0774892ae162
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939530819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.1939530819
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.2721881485
Short name T452
Test name
Test status
Simulation time 494115069 ps
CPU time 2.6 seconds
Started Dec 31 12:48:15 PM PST 23
Finished Dec 31 12:48:23 PM PST 23
Peak memory 199252 kb
Host smart-87add076-2b92-41ca-a12e-a289d89105a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721881485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.2721881485
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.2958227048
Short name T162
Test name
Test status
Simulation time 86202481 ps
CPU time 0.76 seconds
Started Dec 31 12:48:42 PM PST 23
Finished Dec 31 12:48:45 PM PST 23
Peak memory 199312 kb
Host smart-941cc5d2-197c-41f9-b1b4-a9ac01ed4969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958227048 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.2958227048
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.2067399348
Short name T418
Test name
Test status
Simulation time 76530240 ps
CPU time 0.74 seconds
Started Dec 31 12:47:51 PM PST 23
Finished Dec 31 12:47:53 PM PST 23
Peak memory 199088 kb
Host smart-1641c190-3b57-49b0-a903-9da6bdbee333
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067399348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.2067399348
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.86634363
Short name T28
Test name
Test status
Simulation time 1227299486 ps
CPU time 5.92 seconds
Started Dec 31 12:48:17 PM PST 23
Finished Dec 31 12:48:28 PM PST 23
Peak memory 220732 kb
Host smart-e8e43b9b-2435-43c7-b6ce-35796b3a07ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86634363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.86634363
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.3579214494
Short name T131
Test name
Test status
Simulation time 244365606 ps
CPU time 1.1 seconds
Started Dec 31 12:48:08 PM PST 23
Finished Dec 31 12:48:12 PM PST 23
Peak memory 216384 kb
Host smart-a76d1ea0-0b78-4976-817e-2035a4f14d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579214494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.3579214494
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.2615608687
Short name T521
Test name
Test status
Simulation time 161027196 ps
CPU time 0.79 seconds
Started Dec 31 12:49:15 PM PST 23
Finished Dec 31 12:49:17 PM PST 23
Peak memory 199212 kb
Host smart-3bd7d226-9910-4c74-91c6-470b6ef6f2ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615608687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.2615608687
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.2129764385
Short name T484
Test name
Test status
Simulation time 1373300883 ps
CPU time 5.06 seconds
Started Dec 31 12:48:34 PM PST 23
Finished Dec 31 12:48:42 PM PST 23
Peak memory 199408 kb
Host smart-bf8f2e15-36f8-4bce-ab1f-7d82a5602d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129764385 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.2129764385
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.4187552413
Short name T247
Test name
Test status
Simulation time 160914787 ps
CPU time 1.17 seconds
Started Dec 31 12:48:27 PM PST 23
Finished Dec 31 12:48:31 PM PST 23
Peak memory 199392 kb
Host smart-d91bda55-c237-4ff7-a0da-f3d1917186c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187552413 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.4187552413
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.211158313
Short name T254
Test name
Test status
Simulation time 120913573 ps
CPU time 1.15 seconds
Started Dec 31 12:48:54 PM PST 23
Finished Dec 31 12:48:56 PM PST 23
Peak memory 199524 kb
Host smart-85509aef-abfc-44ea-8218-643561f83432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211158313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.211158313
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.1764815797
Short name T593
Test name
Test status
Simulation time 2221293843 ps
CPU time 10.62 seconds
Started Dec 31 12:48:26 PM PST 23
Finished Dec 31 12:48:40 PM PST 23
Peak memory 199504 kb
Host smart-664ac452-e86c-40b3-a173-1a6a3fe3e57e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764815797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.1764815797
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.1702167855
Short name T614
Test name
Test status
Simulation time 261458885 ps
CPU time 1.47 seconds
Started Dec 31 12:48:01 PM PST 23
Finished Dec 31 12:48:06 PM PST 23
Peak memory 199280 kb
Host smart-91e952f3-e3ea-4cdc-9226-6d2936023267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702167855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.1702167855
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.2330160103
Short name T354
Test name
Test status
Simulation time 62903241 ps
CPU time 0.72 seconds
Started Dec 31 12:48:22 PM PST 23
Finished Dec 31 12:48:27 PM PST 23
Peak memory 199104 kb
Host smart-1f4e360f-0cb4-4326-8afc-edf90e74007d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330160103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.2330160103
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.457233524
Short name T374
Test name
Test status
Simulation time 2344961080 ps
CPU time 7.52 seconds
Started Dec 31 12:48:33 PM PST 23
Finished Dec 31 12:48:41 PM PST 23
Peak memory 221092 kb
Host smart-46b4208a-7014-442e-ab5c-6044ade4abf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457233524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.457233524
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.4058396720
Short name T435
Test name
Test status
Simulation time 244773117 ps
CPU time 1.04 seconds
Started Dec 31 12:48:09 PM PST 23
Finished Dec 31 12:48:12 PM PST 23
Peak memory 216372 kb
Host smart-649bda23-6043-42a8-b444-4bcbf1eaec9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058396720 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.4058396720
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.1167397295
Short name T587
Test name
Test status
Simulation time 158665159 ps
CPU time 0.84 seconds
Started Dec 31 12:48:08 PM PST 23
Finished Dec 31 12:48:11 PM PST 23
Peak memory 199160 kb
Host smart-f83dce34-5cb5-4745-a1eb-6862e4391a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167397295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.1167397295
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.181862423
Short name T101
Test name
Test status
Simulation time 1576714370 ps
CPU time 5.29 seconds
Started Dec 31 12:48:15 PM PST 23
Finished Dec 31 12:48:28 PM PST 23
Peak memory 199436 kb
Host smart-208496e2-ec2b-4b29-a6d0-c60636ba64fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181862423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.181862423
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.3606857986
Short name T369
Test name
Test status
Simulation time 151248718 ps
CPU time 1.1 seconds
Started Dec 31 12:48:31 PM PST 23
Finished Dec 31 12:48:34 PM PST 23
Peak memory 199360 kb
Host smart-f6c3f8fd-be1f-4397-b7be-092f74091d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606857986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.3606857986
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.2067780244
Short name T520
Test name
Test status
Simulation time 114482487 ps
CPU time 1.14 seconds
Started Dec 31 12:48:29 PM PST 23
Finished Dec 31 12:48:32 PM PST 23
Peak memory 199432 kb
Host smart-b6bf14db-a7e2-4bbf-859b-d716380e3754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067780244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.2067780244
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.874898499
Short name T586
Test name
Test status
Simulation time 1945801999 ps
CPU time 9.2 seconds
Started Dec 31 12:48:39 PM PST 23
Finished Dec 31 12:48:50 PM PST 23
Peak memory 199508 kb
Host smart-665136ff-7f7e-4923-a701-19f02580347e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874898499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.874898499
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.4162992994
Short name T235
Test name
Test status
Simulation time 497116117 ps
CPU time 2.44 seconds
Started Dec 31 12:48:19 PM PST 23
Finished Dec 31 12:48:26 PM PST 23
Peak memory 199280 kb
Host smart-908c26bd-34a7-4104-8406-54b9abfc7f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162992994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.4162992994
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.3306106734
Short name T499
Test name
Test status
Simulation time 104565102 ps
CPU time 0.89 seconds
Started Dec 31 12:48:18 PM PST 23
Finished Dec 31 12:48:23 PM PST 23
Peak memory 199296 kb
Host smart-0e06604d-d70a-4b9c-b81e-c843761bd9c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306106734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.3306106734
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.734858901
Short name T141
Test name
Test status
Simulation time 74456685 ps
CPU time 0.75 seconds
Started Dec 31 12:48:24 PM PST 23
Finished Dec 31 12:48:29 PM PST 23
Peak memory 199152 kb
Host smart-095967a8-55e2-440a-9bd0-82c6156b464a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734858901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.734858901
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.4046286860
Short name T289
Test name
Test status
Simulation time 1894345092 ps
CPU time 7.7 seconds
Started Dec 31 12:48:35 PM PST 23
Finished Dec 31 12:48:44 PM PST 23
Peak memory 216148 kb
Host smart-fe338ae9-609f-4583-ae95-37dd8fe77136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046286860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.4046286860
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.3613091475
Short name T531
Test name
Test status
Simulation time 244541746 ps
CPU time 1.04 seconds
Started Dec 31 12:48:18 PM PST 23
Finished Dec 31 12:48:23 PM PST 23
Peak memory 216584 kb
Host smart-1488dad6-9cb4-4ffd-81e9-bf1b647e07cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613091475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.3613091475
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.3456948883
Short name T331
Test name
Test status
Simulation time 192205675 ps
CPU time 0.82 seconds
Started Dec 31 12:48:10 PM PST 23
Finished Dec 31 12:48:14 PM PST 23
Peak memory 199132 kb
Host smart-5a17fa29-dbca-4647-bed0-a70c3602340b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456948883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.3456948883
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.1858874530
Short name T457
Test name
Test status
Simulation time 939492710 ps
CPU time 4.68 seconds
Started Dec 31 12:47:57 PM PST 23
Finished Dec 31 12:48:09 PM PST 23
Peak memory 199500 kb
Host smart-d1a1a37f-52c9-43bd-bfba-51987ed8c9a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858874530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.1858874530
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.3095529800
Short name T152
Test name
Test status
Simulation time 183197955 ps
CPU time 1.14 seconds
Started Dec 31 12:48:01 PM PST 23
Finished Dec 31 12:48:05 PM PST 23
Peak memory 199300 kb
Host smart-e334b594-94d6-4bb1-9b01-4e9b9a556e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095529800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.3095529800
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.3539822192
Short name T537
Test name
Test status
Simulation time 118690275 ps
CPU time 1.15 seconds
Started Dec 31 12:48:41 PM PST 23
Finished Dec 31 12:48:53 PM PST 23
Peak memory 199528 kb
Host smart-08346672-8b59-445b-93bf-5fdbbdc42bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539822192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.3539822192
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.1021842268
Short name T246
Test name
Test status
Simulation time 7367211239 ps
CPU time 30.34 seconds
Started Dec 31 12:48:07 PM PST 23
Finished Dec 31 12:48:40 PM PST 23
Peak memory 199588 kb
Host smart-3153fc34-ba2d-4315-9f9b-13f56b2755c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021842268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.1021842268
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.2085553207
Short name T303
Test name
Test status
Simulation time 344332858 ps
CPU time 2.2 seconds
Started Dec 31 12:48:34 PM PST 23
Finished Dec 31 12:48:39 PM PST 23
Peak memory 199196 kb
Host smart-48169413-f5bb-4d57-be34-ee657e078b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085553207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.2085553207
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.2116906463
Short name T62
Test name
Test status
Simulation time 172075372 ps
CPU time 1.09 seconds
Started Dec 31 12:48:18 PM PST 23
Finished Dec 31 12:48:24 PM PST 23
Peak memory 199324 kb
Host smart-c31ad4be-0a4f-4db4-872f-17c01120ce0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116906463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.2116906463
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.1515721479
Short name T509
Test name
Test status
Simulation time 66022049 ps
CPU time 0.75 seconds
Started Dec 31 12:47:58 PM PST 23
Finished Dec 31 12:48:01 PM PST 23
Peak memory 199080 kb
Host smart-c33212c2-f03c-4120-b043-972e3ace358f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515721479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.1515721479
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.390428765
Short name T355
Test name
Test status
Simulation time 1216916680 ps
CPU time 5.17 seconds
Started Dec 31 12:48:00 PM PST 23
Finished Dec 31 12:48:08 PM PST 23
Peak memory 216744 kb
Host smart-b9f4b020-c161-42af-897a-3a3b4962494a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390428765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.390428765
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.4200937464
Short name T379
Test name
Test status
Simulation time 245692569 ps
CPU time 1.03 seconds
Started Dec 31 12:48:22 PM PST 23
Finished Dec 31 12:48:28 PM PST 23
Peak memory 216364 kb
Host smart-59c7ed06-855b-4824-984d-30ace043c647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200937464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.4200937464
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.2212034733
Short name T17
Test name
Test status
Simulation time 177608985 ps
CPU time 0.82 seconds
Started Dec 31 12:48:10 PM PST 23
Finished Dec 31 12:48:14 PM PST 23
Peak memory 199080 kb
Host smart-a690f3a7-1c5f-48b5-a134-a971f6a24cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212034733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.2212034733
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.4115988866
Short name T57
Test name
Test status
Simulation time 1389373536 ps
CPU time 5.49 seconds
Started Dec 31 12:48:34 PM PST 23
Finished Dec 31 12:48:42 PM PST 23
Peak memory 199420 kb
Host smart-7ae5cf12-f749-4da0-bceb-ab733ed4d278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115988866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.4115988866
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.3071418467
Short name T293
Test name
Test status
Simulation time 137624741 ps
CPU time 1.13 seconds
Started Dec 31 12:48:11 PM PST 23
Finished Dec 31 12:48:16 PM PST 23
Peak memory 199360 kb
Host smart-c93d8a4d-a444-482d-9eb7-d602790b5289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071418467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.3071418467
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.922823207
Short name T306
Test name
Test status
Simulation time 197152226 ps
CPU time 1.34 seconds
Started Dec 31 12:48:08 PM PST 23
Finished Dec 31 12:48:11 PM PST 23
Peak memory 199436 kb
Host smart-82049b70-0433-4803-832e-5f66d3a0d7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922823207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.922823207
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.4051993115
Short name T295
Test name
Test status
Simulation time 5928042524 ps
CPU time 19.73 seconds
Started Dec 31 12:48:19 PM PST 23
Finished Dec 31 12:48:42 PM PST 23
Peak memory 199444 kb
Host smart-576e665c-7516-45a9-8102-e60965259f05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051993115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.4051993115
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.492574156
Short name T144
Test name
Test status
Simulation time 127323561 ps
CPU time 1.47 seconds
Started Dec 31 12:48:02 PM PST 23
Finished Dec 31 12:48:06 PM PST 23
Peak memory 199280 kb
Host smart-94cd0df1-8959-4713-8b56-f8953c302a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492574156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.492574156
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.1852592508
Short name T294
Test name
Test status
Simulation time 107901255 ps
CPU time 0.9 seconds
Started Dec 31 12:48:33 PM PST 23
Finished Dec 31 12:48:34 PM PST 23
Peak memory 199284 kb
Host smart-35fbdcd0-533b-4a27-a0d0-e95f5f84110a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852592508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.1852592508
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.3453689765
Short name T527
Test name
Test status
Simulation time 75982954 ps
CPU time 0.77 seconds
Started Dec 31 12:47:51 PM PST 23
Finished Dec 31 12:47:53 PM PST 23
Peak memory 199104 kb
Host smart-f25d45a8-35c4-4def-a015-453e83241758
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453689765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.3453689765
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.2704207693
Short name T404
Test name
Test status
Simulation time 1220832061 ps
CPU time 5.44 seconds
Started Dec 31 12:48:16 PM PST 23
Finished Dec 31 12:48:28 PM PST 23
Peak memory 217880 kb
Host smart-37c3593a-1197-4885-8e41-d8d05adbc356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704207693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.2704207693
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.3525521771
Short name T132
Test name
Test status
Simulation time 243942220 ps
CPU time 1.05 seconds
Started Dec 31 12:48:31 PM PST 23
Finished Dec 31 12:48:33 PM PST 23
Peak memory 216492 kb
Host smart-c557fc7f-f750-4c8c-88f5-7fa383d01557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525521771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.3525521771
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.942639563
Short name T542
Test name
Test status
Simulation time 170368706 ps
CPU time 0.83 seconds
Started Dec 31 12:48:35 PM PST 23
Finished Dec 31 12:48:37 PM PST 23
Peak memory 199144 kb
Host smart-2a8e86b6-de5a-4be2-9c92-de7ecf5ecc89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942639563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.942639563
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.1274834634
Short name T345
Test name
Test status
Simulation time 773411950 ps
CPU time 3.69 seconds
Started Dec 31 12:48:04 PM PST 23
Finished Dec 31 12:48:09 PM PST 23
Peak memory 199468 kb
Host smart-9fa19fdd-6a43-4f83-89fc-24934bd8b01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274834634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.1274834634
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.2280124634
Short name T448
Test name
Test status
Simulation time 92615911 ps
CPU time 0.94 seconds
Started Dec 31 12:48:18 PM PST 23
Finished Dec 31 12:48:23 PM PST 23
Peak memory 199328 kb
Host smart-9a92690f-51d7-4440-b1d2-16f11ee1b192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280124634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.2280124634
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.756864096
Short name T240
Test name
Test status
Simulation time 236995808 ps
CPU time 1.46 seconds
Started Dec 31 12:48:29 PM PST 23
Finished Dec 31 12:48:32 PM PST 23
Peak memory 199404 kb
Host smart-aefbd270-dbb2-40af-8337-ff1c1c85f5b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756864096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.756864096
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.2941599646
Short name T511
Test name
Test status
Simulation time 5066780479 ps
CPU time 23.5 seconds
Started Dec 31 12:48:11 PM PST 23
Finished Dec 31 12:48:38 PM PST 23
Peak memory 199496 kb
Host smart-d6aa0776-68a1-4b2c-b747-2c1537d195c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941599646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.2941599646
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.312094144
Short name T454
Test name
Test status
Simulation time 404001369 ps
CPU time 2.31 seconds
Started Dec 31 12:48:07 PM PST 23
Finished Dec 31 12:48:12 PM PST 23
Peak memory 199276 kb
Host smart-196d6ca8-cd01-401b-adc9-6870cf80f714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312094144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.312094144
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.3831444368
Short name T434
Test name
Test status
Simulation time 158540642 ps
CPU time 1.19 seconds
Started Dec 31 12:48:45 PM PST 23
Finished Dec 31 12:48:48 PM PST 23
Peak memory 199444 kb
Host smart-d25b9f46-55d1-4a62-9879-5d7760bc68a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831444368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.3831444368
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.506540481
Short name T447
Test name
Test status
Simulation time 63498952 ps
CPU time 0.72 seconds
Started Dec 31 12:49:04 PM PST 23
Finished Dec 31 12:49:06 PM PST 23
Peak memory 199192 kb
Host smart-9b99d95a-fbdf-4641-a60c-ca4ddacd444b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506540481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.506540481
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.1201635546
Short name T442
Test name
Test status
Simulation time 2161849460 ps
CPU time 7.54 seconds
Started Dec 31 12:48:17 PM PST 23
Finished Dec 31 12:48:30 PM PST 23
Peak memory 220456 kb
Host smart-30b7fdb3-d610-4b53-ac38-0bea9b50f5eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201635546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.1201635546
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.4115968103
Short name T61
Test name
Test status
Simulation time 243875207 ps
CPU time 1.07 seconds
Started Dec 31 12:48:23 PM PST 23
Finished Dec 31 12:48:28 PM PST 23
Peak memory 216456 kb
Host smart-9222ca3d-3bca-4e36-81b3-f3ddbee6df74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115968103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.4115968103
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.4136974851
Short name T577
Test name
Test status
Simulation time 115404222 ps
CPU time 0.75 seconds
Started Dec 31 12:48:18 PM PST 23
Finished Dec 31 12:48:23 PM PST 23
Peak memory 199188 kb
Host smart-3419ae85-5212-436a-92a4-69c03d963549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136974851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.4136974851
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.2338661694
Short name T459
Test name
Test status
Simulation time 1044743882 ps
CPU time 5.6 seconds
Started Dec 31 12:48:19 PM PST 23
Finished Dec 31 12:48:28 PM PST 23
Peak memory 199404 kb
Host smart-f21a446f-1e37-40ec-b689-f01eea845ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338661694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.2338661694
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.141229012
Short name T497
Test name
Test status
Simulation time 103315015 ps
CPU time 1 seconds
Started Dec 31 12:48:43 PM PST 23
Finished Dec 31 12:48:46 PM PST 23
Peak memory 199280 kb
Host smart-4520801d-434a-4e7f-97ce-bc437c7379db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141229012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.141229012
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.456954003
Short name T417
Test name
Test status
Simulation time 115457737 ps
CPU time 1.11 seconds
Started Dec 31 12:48:14 PM PST 23
Finished Dec 31 12:48:21 PM PST 23
Peak memory 199496 kb
Host smart-f3cbcd78-054f-4715-83f7-248c3fca4ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456954003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.456954003
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.581673792
Short name T300
Test name
Test status
Simulation time 8871010874 ps
CPU time 32.53 seconds
Started Dec 31 12:48:56 PM PST 23
Finished Dec 31 12:49:30 PM PST 23
Peak memory 199684 kb
Host smart-b6d12c96-ec90-460c-a50e-1d0b4e0be903
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581673792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.581673792
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.3807205064
Short name T566
Test name
Test status
Simulation time 265404566 ps
CPU time 1.78 seconds
Started Dec 31 12:48:28 PM PST 23
Finished Dec 31 12:48:32 PM PST 23
Peak memory 199320 kb
Host smart-445d52a5-87e7-4f3d-adad-1bba41bbfed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807205064 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.3807205064
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.1686919127
Short name T140
Test name
Test status
Simulation time 217245568 ps
CPU time 1.23 seconds
Started Dec 31 12:48:31 PM PST 23
Finished Dec 31 12:48:33 PM PST 23
Peak memory 199304 kb
Host smart-e10b8587-309a-4a66-bed2-2e985a1df8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686919127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.1686919127
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.844064971
Short name T51
Test name
Test status
Simulation time 78651729 ps
CPU time 0.74 seconds
Started Dec 31 12:47:25 PM PST 23
Finished Dec 31 12:47:29 PM PST 23
Peak memory 199100 kb
Host smart-9d3b0409-1e27-4997-9331-7b88cda4b11a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844064971 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.844064971
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.4240355558
Short name T32
Test name
Test status
Simulation time 2185711979 ps
CPU time 7.67 seconds
Started Dec 31 12:47:48 PM PST 23
Finished Dec 31 12:47:57 PM PST 23
Peak memory 217992 kb
Host smart-3e694eee-41af-47a1-a5c2-0cf396cdb1e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240355558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.4240355558
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.3823586581
Short name T583
Test name
Test status
Simulation time 243774411 ps
CPU time 1.09 seconds
Started Dec 31 12:47:30 PM PST 23
Finished Dec 31 12:47:39 PM PST 23
Peak memory 216480 kb
Host smart-a437f245-3f6f-4240-9c3d-f546ad463067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823586581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.3823586581
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.3533525413
Short name T333
Test name
Test status
Simulation time 132489286 ps
CPU time 0.8 seconds
Started Dec 31 12:47:50 PM PST 23
Finished Dec 31 12:47:52 PM PST 23
Peak memory 199072 kb
Host smart-ff5c9d6c-1a60-4b94-896a-175e670369b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533525413 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.3533525413
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.3133152608
Short name T422
Test name
Test status
Simulation time 2010130040 ps
CPU time 6.41 seconds
Started Dec 31 12:47:38 PM PST 23
Finished Dec 31 12:47:49 PM PST 23
Peak memory 199540 kb
Host smart-46fa429e-3bc0-49f2-9e33-9af7c1680117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133152608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.3133152608
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.1841908097
Short name T525
Test name
Test status
Simulation time 109198113 ps
CPU time 0.96 seconds
Started Dec 31 12:47:15 PM PST 23
Finished Dec 31 12:47:17 PM PST 23
Peak memory 199292 kb
Host smart-8bb0e761-c913-4435-bf10-085a6f0be30f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841908097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.1841908097
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.2127832668
Short name T481
Test name
Test status
Simulation time 107942509 ps
CPU time 1.1 seconds
Started Dec 31 12:47:35 PM PST 23
Finished Dec 31 12:47:43 PM PST 23
Peak memory 199520 kb
Host smart-14d2b48f-7cb3-4df6-8ab5-62a8dcd048c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127832668 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.2127832668
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.3187319067
Short name T438
Test name
Test status
Simulation time 3426423864 ps
CPU time 13.08 seconds
Started Dec 31 12:47:29 PM PST 23
Finished Dec 31 12:47:51 PM PST 23
Peak memory 199484 kb
Host smart-2077d228-0cbe-4b7e-b4a5-3893e0626c4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187319067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.3187319067
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.3798689416
Short name T380
Test name
Test status
Simulation time 132231260 ps
CPU time 1.55 seconds
Started Dec 31 12:47:33 PM PST 23
Finished Dec 31 12:47:39 PM PST 23
Peak memory 199196 kb
Host smart-f5e1b45a-133b-481e-97e8-81414783afe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798689416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.3798689416
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.657481509
Short name T142
Test name
Test status
Simulation time 143155434 ps
CPU time 1.21 seconds
Started Dec 31 12:47:29 PM PST 23
Finished Dec 31 12:47:39 PM PST 23
Peak memory 199332 kb
Host smart-3a1acd49-d890-448d-ba69-6f2c67ff5957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657481509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.657481509
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.3500272487
Short name T137
Test name
Test status
Simulation time 82526497 ps
CPU time 0.76 seconds
Started Dec 31 12:48:16 PM PST 23
Finished Dec 31 12:48:23 PM PST 23
Peak memory 199168 kb
Host smart-7fd935ca-0ddc-4fa9-9929-050c7f132d74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500272487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.3500272487
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.1599847343
Short name T34
Test name
Test status
Simulation time 1217339330 ps
CPU time 5.62 seconds
Started Dec 31 12:48:09 PM PST 23
Finished Dec 31 12:48:18 PM PST 23
Peak memory 216852 kb
Host smart-85478de4-f9e1-4da6-aa49-bac0d814a5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599847343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.1599847343
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.2246646226
Short name T605
Test name
Test status
Simulation time 243452225 ps
CPU time 1.15 seconds
Started Dec 31 12:48:33 PM PST 23
Finished Dec 31 12:48:35 PM PST 23
Peak memory 216548 kb
Host smart-c1a89e30-164c-49b0-b05a-4be426260c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246646226 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.2246646226
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.1905647674
Short name T591
Test name
Test status
Simulation time 135577265 ps
CPU time 0.8 seconds
Started Dec 31 12:48:24 PM PST 23
Finished Dec 31 12:48:28 PM PST 23
Peak memory 199080 kb
Host smart-81e0879a-b9d6-43b2-9365-cf58eba2f5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905647674 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.1905647674
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.2244429186
Short name T102
Test name
Test status
Simulation time 999212174 ps
CPU time 4.71 seconds
Started Dec 31 12:48:26 PM PST 23
Finished Dec 31 12:48:33 PM PST 23
Peak memory 199440 kb
Host smart-2ecf3c1c-ded5-4c0b-ae12-898ed19f01df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244429186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.2244429186
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.2980578672
Short name T3
Test name
Test status
Simulation time 158401195 ps
CPU time 1.13 seconds
Started Dec 31 12:49:07 PM PST 23
Finished Dec 31 12:49:09 PM PST 23
Peak memory 199304 kb
Host smart-03de8b91-a83f-4f4c-a189-52f00c3cb168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980578672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.2980578672
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.3458656909
Short name T346
Test name
Test status
Simulation time 192247018 ps
CPU time 1.3 seconds
Started Dec 31 12:48:01 PM PST 23
Finished Dec 31 12:48:05 PM PST 23
Peak memory 199468 kb
Host smart-0f799af1-1eec-412c-bb6a-c129a8555650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458656909 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.3458656909
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.1537395476
Short name T68
Test name
Test status
Simulation time 166153407 ps
CPU time 1.36 seconds
Started Dec 31 12:48:04 PM PST 23
Finished Dec 31 12:48:08 PM PST 23
Peak memory 199404 kb
Host smart-30567fac-8c42-4d41-bd74-49c67f446c1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537395476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.1537395476
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.2472737744
Short name T539
Test name
Test status
Simulation time 115120305 ps
CPU time 1.38 seconds
Started Dec 31 12:48:40 PM PST 23
Finished Dec 31 12:48:44 PM PST 23
Peak memory 199292 kb
Host smart-a0b4d54c-0de6-427f-9ced-5bde6f4f51e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472737744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.2472737744
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.3876651751
Short name T510
Test name
Test status
Simulation time 92164119 ps
CPU time 0.81 seconds
Started Dec 31 12:48:46 PM PST 23
Finished Dec 31 12:48:53 PM PST 23
Peak memory 199188 kb
Host smart-6aaba36b-1428-4bed-a01d-41dc26ac91ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876651751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.3876651751
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.1301976314
Short name T49
Test name
Test status
Simulation time 65072938 ps
CPU time 0.69 seconds
Started Dec 31 12:48:26 PM PST 23
Finished Dec 31 12:48:29 PM PST 23
Peak memory 199096 kb
Host smart-81839c8b-fbec-4826-bcfb-30337fe53c3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301976314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.1301976314
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.2447205640
Short name T320
Test name
Test status
Simulation time 1213160497 ps
CPU time 5.8 seconds
Started Dec 31 12:48:36 PM PST 23
Finished Dec 31 12:48:43 PM PST 23
Peak memory 221368 kb
Host smart-49f8564b-3839-4cf1-b60b-f52b989c641a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447205640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.2447205640
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.2006965476
Short name T121
Test name
Test status
Simulation time 244205227 ps
CPU time 1.04 seconds
Started Dec 31 12:48:09 PM PST 23
Finished Dec 31 12:48:14 PM PST 23
Peak memory 216384 kb
Host smart-458bebd3-26c0-48e0-bb3e-73f0732f3c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006965476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.2006965476
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.1542047856
Short name T596
Test name
Test status
Simulation time 104859232 ps
CPU time 0.75 seconds
Started Dec 31 12:48:33 PM PST 23
Finished Dec 31 12:48:35 PM PST 23
Peak memory 199092 kb
Host smart-df121a32-ceb7-48d6-b0a9-facadc50ae3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542047856 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.1542047856
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.2136783542
Short name T150
Test name
Test status
Simulation time 1635925967 ps
CPU time 7.08 seconds
Started Dec 31 12:48:09 PM PST 23
Finished Dec 31 12:48:19 PM PST 23
Peak memory 199476 kb
Host smart-27eee472-2b12-4a4a-a6c7-b461e7086d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136783542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.2136783542
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.2144044296
Short name T535
Test name
Test status
Simulation time 101249056 ps
CPU time 0.98 seconds
Started Dec 31 12:48:40 PM PST 23
Finished Dec 31 12:48:42 PM PST 23
Peak memory 199244 kb
Host smart-32dd2dcf-e07b-44cf-9f8a-dfeed525dade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144044296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.2144044296
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.182350652
Short name T414
Test name
Test status
Simulation time 262192898 ps
CPU time 1.48 seconds
Started Dec 31 12:48:36 PM PST 23
Finished Dec 31 12:48:38 PM PST 23
Peak memory 199484 kb
Host smart-4c0c1e02-da28-4f5e-a4ce-108cba28062f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182350652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.182350652
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.209090402
Short name T370
Test name
Test status
Simulation time 431912075 ps
CPU time 2.33 seconds
Started Dec 31 12:48:01 PM PST 23
Finished Dec 31 12:48:06 PM PST 23
Peak memory 199308 kb
Host smart-9a440b09-4702-4e30-b82a-c11f6764720e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209090402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.209090402
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.3252458336
Short name T376
Test name
Test status
Simulation time 132029964 ps
CPU time 0.93 seconds
Started Dec 31 12:48:07 PM PST 23
Finished Dec 31 12:48:15 PM PST 23
Peak memory 199332 kb
Host smart-6b317643-3b1a-43c6-b664-a3c34be6846f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252458336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.3252458336
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.2888768934
Short name T526
Test name
Test status
Simulation time 67033601 ps
CPU time 0.73 seconds
Started Dec 31 12:48:52 PM PST 23
Finished Dec 31 12:48:54 PM PST 23
Peak memory 199128 kb
Host smart-a1951ee6-f2e5-44ec-b4e6-b137b4d3fe89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888768934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.2888768934
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.2998613395
Short name T363
Test name
Test status
Simulation time 1889254040 ps
CPU time 6.69 seconds
Started Dec 31 12:49:09 PM PST 23
Finished Dec 31 12:49:17 PM PST 23
Peak memory 216652 kb
Host smart-5a2e2f78-ccba-42c3-ba46-2577470e714f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998613395 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.2998613395
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.3480553390
Short name T446
Test name
Test status
Simulation time 244860018 ps
CPU time 1.03 seconds
Started Dec 31 12:48:57 PM PST 23
Finished Dec 31 12:48:59 PM PST 23
Peak memory 216492 kb
Host smart-076bba01-2356-4f28-b5f1-65697871baa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480553390 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.3480553390
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.374094453
Short name T505
Test name
Test status
Simulation time 167078509 ps
CPU time 0.83 seconds
Started Dec 31 12:48:11 PM PST 23
Finished Dec 31 12:48:15 PM PST 23
Peak memory 199048 kb
Host smart-d0e44e32-c537-402e-b791-197f0d2d7fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374094453 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.374094453
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.845858356
Short name T59
Test name
Test status
Simulation time 2001414908 ps
CPU time 6.84 seconds
Started Dec 31 12:48:14 PM PST 23
Finished Dec 31 12:48:27 PM PST 23
Peak memory 199496 kb
Host smart-cd0ddac8-fd2b-47f9-81dc-72cfbb057537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845858356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.845858356
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.821578259
Short name T311
Test name
Test status
Simulation time 147328328 ps
CPU time 1.21 seconds
Started Dec 31 12:48:59 PM PST 23
Finished Dec 31 12:49:01 PM PST 23
Peak memory 199280 kb
Host smart-221301ea-5e4f-4ea6-b218-eadf824d9725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821578259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.821578259
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.997131244
Short name T567
Test name
Test status
Simulation time 113730483 ps
CPU time 1.1 seconds
Started Dec 31 12:48:29 PM PST 23
Finished Dec 31 12:48:31 PM PST 23
Peak memory 199520 kb
Host smart-7b2203dd-01ed-4f6e-acb5-27af5fd034b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997131244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.997131244
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.103521925
Short name T552
Test name
Test status
Simulation time 13251553907 ps
CPU time 47.19 seconds
Started Dec 31 12:48:45 PM PST 23
Finished Dec 31 12:49:34 PM PST 23
Peak memory 199524 kb
Host smart-1e5dd0cc-bfab-4776-b754-4bfdbf74e37d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103521925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.103521925
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.3470004954
Short name T304
Test name
Test status
Simulation time 142950113 ps
CPU time 1.72 seconds
Started Dec 31 12:48:38 PM PST 23
Finished Dec 31 12:48:41 PM PST 23
Peak memory 199412 kb
Host smart-43f6a807-7782-4d00-af37-a9b0afb726bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470004954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.3470004954
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.1327240071
Short name T308
Test name
Test status
Simulation time 102108883 ps
CPU time 0.84 seconds
Started Dec 31 12:49:48 PM PST 23
Finished Dec 31 12:49:49 PM PST 23
Peak memory 199304 kb
Host smart-7e18b923-41bf-4260-90b4-59939511a508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327240071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.1327240071
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.2414711117
Short name T257
Test name
Test status
Simulation time 62856514 ps
CPU time 0.7 seconds
Started Dec 31 12:48:40 PM PST 23
Finished Dec 31 12:48:43 PM PST 23
Peak memory 199196 kb
Host smart-31d25948-af4b-42dd-80ef-eb59c01ea4e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414711117 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.2414711117
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.3434953149
Short name T476
Test name
Test status
Simulation time 1894799640 ps
CPU time 7.33 seconds
Started Dec 31 12:49:00 PM PST 23
Finished Dec 31 12:49:08 PM PST 23
Peak memory 220816 kb
Host smart-2bb12764-734e-4997-aa85-666a7f2daad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434953149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.3434953149
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.474057669
Short name T243
Test name
Test status
Simulation time 243531711 ps
CPU time 1.02 seconds
Started Dec 31 12:49:05 PM PST 23
Finished Dec 31 12:49:07 PM PST 23
Peak memory 216600 kb
Host smart-916cdfd7-7b50-4ed9-97ce-b4c010c4bfb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474057669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.474057669
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.2602095560
Short name T493
Test name
Test status
Simulation time 72324257 ps
CPU time 0.67 seconds
Started Dec 31 12:49:12 PM PST 23
Finished Dec 31 12:49:13 PM PST 23
Peak memory 199220 kb
Host smart-84e79236-37de-4a50-8371-3f89334cfd63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602095560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.2602095560
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.249962747
Short name T252
Test name
Test status
Simulation time 1023445958 ps
CPU time 4.93 seconds
Started Dec 31 12:48:53 PM PST 23
Finished Dec 31 12:48:59 PM PST 23
Peak memory 199428 kb
Host smart-05db9675-ab44-461c-b1f9-3c9c83f92f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249962747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.249962747
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.1606854387
Short name T245
Test name
Test status
Simulation time 102233711 ps
CPU time 0.96 seconds
Started Dec 31 12:49:14 PM PST 23
Finished Dec 31 12:49:16 PM PST 23
Peak memory 199300 kb
Host smart-3439124e-b5bd-464a-a8cc-75350aa29c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606854387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.1606854387
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.719859478
Short name T572
Test name
Test status
Simulation time 194783048 ps
CPU time 1.28 seconds
Started Dec 31 12:48:46 PM PST 23
Finished Dec 31 12:48:53 PM PST 23
Peak memory 199496 kb
Host smart-51c4aaa3-9b54-45c7-91c7-2d5a807af0d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719859478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.719859478
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.4251122882
Short name T58
Test name
Test status
Simulation time 266152428 ps
CPU time 1.44 seconds
Started Dec 31 12:48:49 PM PST 23
Finished Dec 31 12:48:52 PM PST 23
Peak memory 199812 kb
Host smart-2e0bf998-9fa7-44cc-ae00-fdb82d4a1cb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251122882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.4251122882
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.4024694144
Short name T296
Test name
Test status
Simulation time 114649794 ps
CPU time 1.46 seconds
Started Dec 31 12:48:46 PM PST 23
Finished Dec 31 12:48:49 PM PST 23
Peak memory 199316 kb
Host smart-036fc44f-a862-4948-bf4d-78ba5d0aa7cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024694144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.4024694144
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.1148188441
Short name T125
Test name
Test status
Simulation time 240523533 ps
CPU time 1.39 seconds
Started Dec 31 12:49:06 PM PST 23
Finished Dec 31 12:49:09 PM PST 23
Peak memory 199360 kb
Host smart-8e460d8d-7985-4931-a638-f8ac120d94e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148188441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.1148188441
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.768336142
Short name T393
Test name
Test status
Simulation time 70661984 ps
CPU time 0.77 seconds
Started Dec 31 12:49:20 PM PST 23
Finished Dec 31 12:49:22 PM PST 23
Peak memory 199156 kb
Host smart-1b0baa62-a331-4595-9c7d-b61712747789
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768336142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.768336142
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.144140559
Short name T4
Test name
Test status
Simulation time 2362799472 ps
CPU time 9.16 seconds
Started Dec 31 12:49:25 PM PST 23
Finished Dec 31 12:49:36 PM PST 23
Peak memory 217024 kb
Host smart-7edb450a-1b33-4a65-b9b3-47bea1917147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144140559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.144140559
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.2409718518
Short name T612
Test name
Test status
Simulation time 244201081 ps
CPU time 1.07 seconds
Started Dec 31 12:49:01 PM PST 23
Finished Dec 31 12:49:03 PM PST 23
Peak memory 216372 kb
Host smart-f9b9817a-47db-47cc-aa1e-903240ed5e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409718518 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.2409718518
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.2204533960
Short name T550
Test name
Test status
Simulation time 119072964 ps
CPU time 0.77 seconds
Started Dec 31 12:49:22 PM PST 23
Finished Dec 31 12:49:24 PM PST 23
Peak memory 199228 kb
Host smart-5f5d1a7b-89b0-4dec-a4f5-e1360670b1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204533960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.2204533960
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.1434214735
Short name T453
Test name
Test status
Simulation time 1562878107 ps
CPU time 6.56 seconds
Started Dec 31 12:49:11 PM PST 23
Finished Dec 31 12:49:19 PM PST 23
Peak memory 199484 kb
Host smart-7d85d559-02db-4d8b-85ed-4510152683e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434214735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.1434214735
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.2991778543
Short name T479
Test name
Test status
Simulation time 100152419 ps
CPU time 0.94 seconds
Started Dec 31 12:48:42 PM PST 23
Finished Dec 31 12:48:45 PM PST 23
Peak memory 199380 kb
Host smart-4f491898-9b60-4161-a8fc-21cd1ed80b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991778543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.2991778543
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.1086114865
Short name T267
Test name
Test status
Simulation time 201488614 ps
CPU time 1.3 seconds
Started Dec 31 12:49:10 PM PST 23
Finished Dec 31 12:49:13 PM PST 23
Peak memory 199404 kb
Host smart-9fec9954-21b2-4fc2-a8fc-e28848dc72e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086114865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.1086114865
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.3089007299
Short name T456
Test name
Test status
Simulation time 5239236615 ps
CPU time 20.1 seconds
Started Dec 31 12:49:37 PM PST 23
Finished Dec 31 12:49:59 PM PST 23
Peak memory 199572 kb
Host smart-505e5c97-653b-45ac-94ec-c318ea39a297
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089007299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.3089007299
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.3889944715
Short name T554
Test name
Test status
Simulation time 116624922 ps
CPU time 1.43 seconds
Started Dec 31 12:49:13 PM PST 23
Finished Dec 31 12:49:16 PM PST 23
Peak memory 199272 kb
Host smart-65af57ac-a44b-4c4a-a7ce-64a108972b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889944715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.3889944715
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.1649032511
Short name T502
Test name
Test status
Simulation time 256569840 ps
CPU time 1.36 seconds
Started Dec 31 12:49:19 PM PST 23
Finished Dec 31 12:49:22 PM PST 23
Peak memory 199276 kb
Host smart-a5543e38-067b-4016-b6d7-72819ddac0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649032511 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.1649032511
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.2139042318
Short name T238
Test name
Test status
Simulation time 54907193 ps
CPU time 0.68 seconds
Started Dec 31 12:48:04 PM PST 23
Finished Dec 31 12:48:07 PM PST 23
Peak memory 199140 kb
Host smart-c55e7b68-4856-4481-a4e8-907395470409
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139042318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.2139042318
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.552221016
Short name T439
Test name
Test status
Simulation time 1884001988 ps
CPU time 7.14 seconds
Started Dec 31 12:49:15 PM PST 23
Finished Dec 31 12:49:24 PM PST 23
Peak memory 216816 kb
Host smart-ff10933b-bac7-45c9-a31e-12c80c1e0d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552221016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.552221016
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.1849051413
Short name T307
Test name
Test status
Simulation time 244733543 ps
CPU time 1.05 seconds
Started Dec 31 12:48:46 PM PST 23
Finished Dec 31 12:48:48 PM PST 23
Peak memory 216440 kb
Host smart-8b083702-9276-4b68-b842-42ca4200619b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849051413 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.1849051413
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.4104454899
Short name T489
Test name
Test status
Simulation time 122495634 ps
CPU time 0.75 seconds
Started Dec 31 12:49:03 PM PST 23
Finished Dec 31 12:49:05 PM PST 23
Peak memory 199156 kb
Host smart-364eb265-c66b-40a7-bc6e-7db57b072e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104454899 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.4104454899
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.2991056984
Short name T237
Test name
Test status
Simulation time 1091240157 ps
CPU time 4.91 seconds
Started Dec 31 12:49:02 PM PST 23
Finished Dec 31 12:49:08 PM PST 23
Peak memory 199420 kb
Host smart-7d6b8064-d41b-470f-8ee7-82a3fd63897c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991056984 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.2991056984
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.2043790185
Short name T309
Test name
Test status
Simulation time 170654055 ps
CPU time 1.1 seconds
Started Dec 31 12:49:02 PM PST 23
Finished Dec 31 12:49:09 PM PST 23
Peak memory 199272 kb
Host smart-698ed58a-b46e-4c78-9600-7b0a106de20a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043790185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.2043790185
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.2020878751
Short name T557
Test name
Test status
Simulation time 189702877 ps
CPU time 1.27 seconds
Started Dec 31 12:49:08 PM PST 23
Finished Dec 31 12:49:10 PM PST 23
Peak memory 199424 kb
Host smart-f4df1bcd-87a1-41b7-b14d-e45d62004fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020878751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.2020878751
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.3348112960
Short name T569
Test name
Test status
Simulation time 4952400491 ps
CPU time 17.75 seconds
Started Dec 31 12:48:48 PM PST 23
Finished Dec 31 12:49:06 PM PST 23
Peak memory 199520 kb
Host smart-db185185-de6d-4a88-84ed-285da8ed2c92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348112960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.3348112960
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.3924882085
Short name T6
Test name
Test status
Simulation time 557067759 ps
CPU time 2.62 seconds
Started Dec 31 12:49:22 PM PST 23
Finished Dec 31 12:49:26 PM PST 23
Peak memory 199312 kb
Host smart-6e365fcf-4b22-47be-8443-627c961ebab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924882085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.3924882085
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.2005062574
Short name T67
Test name
Test status
Simulation time 128572973 ps
CPU time 1.03 seconds
Started Dec 31 12:48:56 PM PST 23
Finished Dec 31 12:48:58 PM PST 23
Peak memory 199300 kb
Host smart-8168a707-a8e3-46dc-bdfa-a96ace85d36f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005062574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.2005062574
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.141102374
Short name T128
Test name
Test status
Simulation time 91896814 ps
CPU time 0.84 seconds
Started Dec 31 12:48:06 PM PST 23
Finished Dec 31 12:48:09 PM PST 23
Peak memory 199152 kb
Host smart-e59ed36e-5553-4d36-92da-79e271fcc9df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141102374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.141102374
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.1945273977
Short name T33
Test name
Test status
Simulation time 1226500501 ps
CPU time 6.48 seconds
Started Dec 31 12:48:21 PM PST 23
Finished Dec 31 12:48:33 PM PST 23
Peak memory 216764 kb
Host smart-81feab46-1677-42af-9869-81ad222a9d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945273977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.1945273977
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.2995970376
Short name T159
Test name
Test status
Simulation time 243706981 ps
CPU time 1.02 seconds
Started Dec 31 12:48:22 PM PST 23
Finished Dec 31 12:48:28 PM PST 23
Peak memory 216520 kb
Host smart-16714514-d1db-40ae-a9a4-8a8186dbcd80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995970376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.2995970376
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.184909554
Short name T19
Test name
Test status
Simulation time 78776349 ps
CPU time 0.7 seconds
Started Dec 31 12:48:06 PM PST 23
Finished Dec 31 12:48:08 PM PST 23
Peak memory 199076 kb
Host smart-c653fe20-1d9b-4725-868e-bf6b5d104aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184909554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.184909554
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.2280806888
Short name T292
Test name
Test status
Simulation time 839239327 ps
CPU time 4.16 seconds
Started Dec 31 12:48:40 PM PST 23
Finished Dec 31 12:48:46 PM PST 23
Peak memory 199380 kb
Host smart-780ea88d-6ef4-43dc-8e11-dcce1e337dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280806888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.2280806888
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.680735191
Short name T458
Test name
Test status
Simulation time 158068300 ps
CPU time 1.06 seconds
Started Dec 31 12:48:19 PM PST 23
Finished Dec 31 12:48:24 PM PST 23
Peak memory 199348 kb
Host smart-06afdb48-b4a9-4b2a-9896-d59b83412211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680735191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.680735191
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.1019796806
Short name T276
Test name
Test status
Simulation time 198162055 ps
CPU time 1.32 seconds
Started Dec 31 12:48:08 PM PST 23
Finished Dec 31 12:48:12 PM PST 23
Peak memory 199404 kb
Host smart-b9f15eec-f338-4b04-b260-f87efbda6bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019796806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.1019796806
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.1623307634
Short name T486
Test name
Test status
Simulation time 3585900791 ps
CPU time 15.73 seconds
Started Dec 31 12:48:32 PM PST 23
Finished Dec 31 12:48:49 PM PST 23
Peak memory 199664 kb
Host smart-10fff26b-3edd-4bcd-8ad6-07443e978eb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623307634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.1623307634
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.2394681756
Short name T543
Test name
Test status
Simulation time 330821924 ps
CPU time 2.17 seconds
Started Dec 31 12:48:02 PM PST 23
Finished Dec 31 12:48:07 PM PST 23
Peak memory 199364 kb
Host smart-139ae5aa-7c55-4a44-bc95-0a0d8bae7bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394681756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.2394681756
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.825086404
Short name T298
Test name
Test status
Simulation time 175023109 ps
CPU time 1.2 seconds
Started Dec 31 12:48:13 PM PST 23
Finished Dec 31 12:48:20 PM PST 23
Peak memory 199384 kb
Host smart-46bbf7ff-5988-427d-9736-c1e62e7f4a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825086404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.825086404
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.3929219681
Short name T99
Test name
Test status
Simulation time 71953955 ps
CPU time 0.73 seconds
Started Dec 31 12:48:38 PM PST 23
Finished Dec 31 12:48:40 PM PST 23
Peak memory 199196 kb
Host smart-6661d62f-a49a-48c1-9de6-878038cb5eaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929219681 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.3929219681
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.1160776903
Short name T607
Test name
Test status
Simulation time 2360090453 ps
CPU time 7.82 seconds
Started Dec 31 12:48:22 PM PST 23
Finished Dec 31 12:48:35 PM PST 23
Peak memory 216576 kb
Host smart-ebc4331d-c15b-4b23-8010-e3bf45c4bb14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160776903 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.1160776903
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.3396543418
Short name T265
Test name
Test status
Simulation time 243824947 ps
CPU time 1.07 seconds
Started Dec 31 12:48:29 PM PST 23
Finished Dec 31 12:48:32 PM PST 23
Peak memory 216396 kb
Host smart-19e29f98-4f6a-4f72-8e78-30e78ffebabf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396543418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.3396543418
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.949017587
Short name T342
Test name
Test status
Simulation time 101151221 ps
CPU time 0.76 seconds
Started Dec 31 12:48:14 PM PST 23
Finished Dec 31 12:48:20 PM PST 23
Peak memory 199076 kb
Host smart-56123ef3-2ea0-4a54-9981-eab297e2f049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949017587 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.949017587
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.4057308125
Short name T506
Test name
Test status
Simulation time 1014326928 ps
CPU time 5.13 seconds
Started Dec 31 12:48:37 PM PST 23
Finished Dec 31 12:48:43 PM PST 23
Peak memory 199512 kb
Host smart-b4dee99c-fe8f-44b4-a358-f7f2a7e0e97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057308125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.4057308125
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.3023172205
Short name T381
Test name
Test status
Simulation time 181285798 ps
CPU time 1.13 seconds
Started Dec 31 12:48:34 PM PST 23
Finished Dec 31 12:48:38 PM PST 23
Peak memory 199304 kb
Host smart-a10e4328-0d0c-4fb6-b87e-5d9778b2e4a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023172205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.3023172205
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.792260147
Short name T147
Test name
Test status
Simulation time 251662012 ps
CPU time 1.44 seconds
Started Dec 31 12:48:29 PM PST 23
Finished Dec 31 12:48:32 PM PST 23
Peak memory 199536 kb
Host smart-c84c2bf3-422a-4128-a0c5-95c34d6a36d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792260147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.792260147
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.2133137581
Short name T63
Test name
Test status
Simulation time 3401898334 ps
CPU time 14.77 seconds
Started Dec 31 12:48:18 PM PST 23
Finished Dec 31 12:48:37 PM PST 23
Peak memory 199612 kb
Host smart-6e235d87-fdf6-4c39-8810-b3dedf8f3f8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133137581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.2133137581
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.569312751
Short name T329
Test name
Test status
Simulation time 293035746 ps
CPU time 1.94 seconds
Started Dec 31 12:48:52 PM PST 23
Finished Dec 31 12:48:56 PM PST 23
Peak memory 199312 kb
Host smart-3152c62a-4eab-477a-abcd-ed9475ad33be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569312751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.569312751
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.1440244580
Short name T153
Test name
Test status
Simulation time 63322992 ps
CPU time 0.72 seconds
Started Dec 31 12:48:21 PM PST 23
Finished Dec 31 12:48:27 PM PST 23
Peak memory 199300 kb
Host smart-bcd40625-2680-4466-be64-8bba6220b506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440244580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.1440244580
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.1195948134
Short name T396
Test name
Test status
Simulation time 68747206 ps
CPU time 0.7 seconds
Started Dec 31 12:48:23 PM PST 23
Finished Dec 31 12:48:28 PM PST 23
Peak memory 199120 kb
Host smart-6a392d69-d8ad-4875-8ff5-6a72ee752c5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195948134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.1195948134
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.481302975
Short name T419
Test name
Test status
Simulation time 1224915779 ps
CPU time 5.9 seconds
Started Dec 31 12:48:37 PM PST 23
Finished Dec 31 12:48:44 PM PST 23
Peak memory 221328 kb
Host smart-d9e677f0-59cb-453b-ac5d-4345c7458eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481302975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.481302975
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.2420737339
Short name T364
Test name
Test status
Simulation time 244249422 ps
CPU time 1.11 seconds
Started Dec 31 12:48:02 PM PST 23
Finished Dec 31 12:48:08 PM PST 23
Peak memory 216476 kb
Host smart-87416a17-2a34-41ac-a9f9-00186b59cc6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420737339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.2420737339
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.2633589808
Short name T411
Test name
Test status
Simulation time 139315281 ps
CPU time 0.77 seconds
Started Dec 31 12:48:41 PM PST 23
Finished Dec 31 12:48:44 PM PST 23
Peak memory 199140 kb
Host smart-34572bef-3e0d-47e9-8f23-751e9f8b243d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633589808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.2633589808
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.4113774620
Short name T312
Test name
Test status
Simulation time 710415192 ps
CPU time 3.67 seconds
Started Dec 31 12:48:39 PM PST 23
Finished Dec 31 12:48:43 PM PST 23
Peak memory 199468 kb
Host smart-3dbb1b53-95fb-462b-b6a7-16909136b3a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113774620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.4113774620
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.3918725878
Short name T483
Test name
Test status
Simulation time 139282157 ps
CPU time 1.07 seconds
Started Dec 31 12:48:28 PM PST 23
Finished Dec 31 12:48:31 PM PST 23
Peak memory 199284 kb
Host smart-83280798-5dac-40db-9691-45e904df8c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918725878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.3918725878
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.1434698684
Short name T359
Test name
Test status
Simulation time 197152059 ps
CPU time 1.29 seconds
Started Dec 31 12:48:33 PM PST 23
Finished Dec 31 12:48:35 PM PST 23
Peak memory 199472 kb
Host smart-34fd609a-013c-4b4d-a29e-aaeb819ba9de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434698684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.1434698684
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.2193109484
Short name T423
Test name
Test status
Simulation time 8331304801 ps
CPU time 30.77 seconds
Started Dec 31 12:48:41 PM PST 23
Finished Dec 31 12:49:14 PM PST 23
Peak memory 199564 kb
Host smart-821d0a0d-12bc-4509-af43-ff6ff5319b72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193109484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.2193109484
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.117250735
Short name T579
Test name
Test status
Simulation time 388825419 ps
CPU time 2.28 seconds
Started Dec 31 12:48:42 PM PST 23
Finished Dec 31 12:48:46 PM PST 23
Peak memory 199328 kb
Host smart-b1893f4d-e764-478b-a1c1-6dbf9c1182bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117250735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.117250735
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.312574249
Short name T573
Test name
Test status
Simulation time 96573526 ps
CPU time 0.87 seconds
Started Dec 31 12:48:44 PM PST 23
Finished Dec 31 12:48:46 PM PST 23
Peak memory 199340 kb
Host smart-f03d1b3e-6207-4c9d-a106-2d60d7fb52e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312574249 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.312574249
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.2852466365
Short name T490
Test name
Test status
Simulation time 77818127 ps
CPU time 0.8 seconds
Started Dec 31 12:49:54 PM PST 23
Finished Dec 31 12:49:57 PM PST 23
Peak memory 199208 kb
Host smart-61da1d70-321e-4c4b-9b91-e5cf14c30048
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852466365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.2852466365
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.2902527302
Short name T615
Test name
Test status
Simulation time 1235331494 ps
CPU time 5.58 seconds
Started Dec 31 12:48:25 PM PST 23
Finished Dec 31 12:48:33 PM PST 23
Peak memory 220860 kb
Host smart-19e529ae-5111-409c-a5e3-8cf3eff0ca35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902527302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.2902527302
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.3411046445
Short name T480
Test name
Test status
Simulation time 244869131 ps
CPU time 1.02 seconds
Started Dec 31 12:49:05 PM PST 23
Finished Dec 31 12:49:07 PM PST 23
Peak memory 216540 kb
Host smart-1b28e6db-3c6c-472f-b3ca-76aa4067221b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411046445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.3411046445
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.1362263740
Short name T620
Test name
Test status
Simulation time 156240680 ps
CPU time 0.8 seconds
Started Dec 31 12:48:11 PM PST 23
Finished Dec 31 12:48:15 PM PST 23
Peak memory 199056 kb
Host smart-99d5d4fe-286b-4cd7-9028-45431e934dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362263740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.1362263740
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.3300885785
Short name T278
Test name
Test status
Simulation time 914288493 ps
CPU time 4.66 seconds
Started Dec 31 12:48:44 PM PST 23
Finished Dec 31 12:48:50 PM PST 23
Peak memory 199544 kb
Host smart-7e7421cd-f8bd-4cb6-bc10-b7c88664af72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300885785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.3300885785
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.1507477029
Short name T248
Test name
Test status
Simulation time 179499685 ps
CPU time 1.16 seconds
Started Dec 31 12:48:27 PM PST 23
Finished Dec 31 12:48:31 PM PST 23
Peak memory 199280 kb
Host smart-9a80b033-2947-46e8-94d1-c36ce670a926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507477029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.1507477029
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.3910336634
Short name T466
Test name
Test status
Simulation time 118074662 ps
CPU time 1.17 seconds
Started Dec 31 12:48:43 PM PST 23
Finished Dec 31 12:48:46 PM PST 23
Peak memory 199432 kb
Host smart-27c5db16-a003-4eda-8872-fe8907dcc34e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910336634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.3910336634
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.2358063924
Short name T388
Test name
Test status
Simulation time 7433919968 ps
CPU time 28 seconds
Started Dec 31 12:48:40 PM PST 23
Finished Dec 31 12:49:10 PM PST 23
Peak memory 199508 kb
Host smart-923c6eab-a132-4a7a-bcf0-2a10ce1ec77b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358063924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.2358063924
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.1919190413
Short name T545
Test name
Test status
Simulation time 124118941 ps
CPU time 1.56 seconds
Started Dec 31 12:48:20 PM PST 23
Finished Dec 31 12:48:28 PM PST 23
Peak memory 199300 kb
Host smart-6f6b0b03-fceb-4f1a-be5c-9144997e1770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919190413 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.1919190413
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.351503810
Short name T603
Test name
Test status
Simulation time 149080000 ps
CPU time 1.12 seconds
Started Dec 31 12:48:56 PM PST 23
Finished Dec 31 12:48:59 PM PST 23
Peak memory 199380 kb
Host smart-d01e64fa-c3a0-4694-9bf4-a308035c5ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351503810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.351503810
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.2397913463
Short name T368
Test name
Test status
Simulation time 58524042 ps
CPU time 0.68 seconds
Started Dec 31 12:47:31 PM PST 23
Finished Dec 31 12:47:38 PM PST 23
Peak memory 199172 kb
Host smart-1cbd6a80-e445-4d84-b519-57bfe60d473e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397913463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.2397913463
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.3214620392
Short name T20
Test name
Test status
Simulation time 2176674926 ps
CPU time 7.87 seconds
Started Dec 31 12:47:32 PM PST 23
Finished Dec 31 12:47:45 PM PST 23
Peak memory 217320 kb
Host smart-1f537266-a119-4410-b4c6-9a56b58dcafe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214620392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.3214620392
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.1191484130
Short name T613
Test name
Test status
Simulation time 245198898 ps
CPU time 1.07 seconds
Started Dec 31 12:47:32 PM PST 23
Finished Dec 31 12:47:39 PM PST 23
Peak memory 216372 kb
Host smart-4fdf8497-3cbc-49c5-9f5a-43895cf75e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191484130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.1191484130
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.4159798828
Short name T18
Test name
Test status
Simulation time 243704655 ps
CPU time 1.05 seconds
Started Dec 31 12:47:37 PM PST 23
Finished Dec 31 12:47:47 PM PST 23
Peak memory 199216 kb
Host smart-78156633-f7f4-4e22-8d82-243679aa48e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159798828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.4159798828
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.3158144454
Short name T347
Test name
Test status
Simulation time 1327339470 ps
CPU time 5.14 seconds
Started Dec 31 12:47:28 PM PST 23
Finished Dec 31 12:47:40 PM PST 23
Peak memory 199412 kb
Host smart-a9e94c48-e877-4cb1-be52-e2ae9d87a938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158144454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.3158144454
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.3621013283
Short name T343
Test name
Test status
Simulation time 143789317 ps
CPU time 1.08 seconds
Started Dec 31 12:47:45 PM PST 23
Finished Dec 31 12:47:48 PM PST 23
Peak memory 199256 kb
Host smart-6143db88-67ea-4fb4-8a45-a7d095f59d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621013283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.3621013283
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.593847742
Short name T580
Test name
Test status
Simulation time 244740889 ps
CPU time 1.44 seconds
Started Dec 31 12:47:33 PM PST 23
Finished Dec 31 12:47:39 PM PST 23
Peak memory 199416 kb
Host smart-4d87b3dd-d526-42bb-95d2-a9c12373faba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593847742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.593847742
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.559290887
Short name T449
Test name
Test status
Simulation time 377858293 ps
CPU time 1.8 seconds
Started Dec 31 12:47:45 PM PST 23
Finished Dec 31 12:47:49 PM PST 23
Peak memory 199476 kb
Host smart-2eea3cc7-bd50-4d27-9e70-480ab751a48f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559290887 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.559290887
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.3104815892
Short name T406
Test name
Test status
Simulation time 254332793 ps
CPU time 1.73 seconds
Started Dec 31 12:47:39 PM PST 23
Finished Dec 31 12:47:45 PM PST 23
Peak memory 199280 kb
Host smart-2784a07b-5b8a-40de-897c-3eccf23d4f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104815892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.3104815892
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.321431050
Short name T556
Test name
Test status
Simulation time 108325978 ps
CPU time 0.9 seconds
Started Dec 31 12:47:52 PM PST 23
Finished Dec 31 12:47:54 PM PST 23
Peak memory 199332 kb
Host smart-71b2eaa0-8bb8-4b86-adbe-fd95388d652f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321431050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.321431050
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.1324415015
Short name T318
Test name
Test status
Simulation time 74703097 ps
CPU time 0.8 seconds
Started Dec 31 12:47:58 PM PST 23
Finished Dec 31 12:48:01 PM PST 23
Peak memory 199092 kb
Host smart-17f325a8-9884-4cfe-a9a9-59a905ba5c1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324415015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.1324415015
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.1921529015
Short name T302
Test name
Test status
Simulation time 1231035849 ps
CPU time 5.51 seconds
Started Dec 31 12:47:44 PM PST 23
Finished Dec 31 12:47:52 PM PST 23
Peak memory 221364 kb
Host smart-f7f13a29-987c-4783-81b7-dfdd99c9357d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921529015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.1921529015
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.2353787054
Short name T546
Test name
Test status
Simulation time 244370415 ps
CPU time 1.07 seconds
Started Dec 31 12:48:05 PM PST 23
Finished Dec 31 12:48:08 PM PST 23
Peak memory 216520 kb
Host smart-80a834ce-f6c2-41e5-b596-91b2ab0ba6e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353787054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.2353787054
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.2716599350
Short name T277
Test name
Test status
Simulation time 160782075 ps
CPU time 0.8 seconds
Started Dec 31 12:47:21 PM PST 23
Finished Dec 31 12:47:23 PM PST 23
Peak memory 199132 kb
Host smart-92aaa70b-7080-41f6-b8f9-a0eea16df5a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716599350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.2716599350
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.2507092788
Short name T395
Test name
Test status
Simulation time 1616172061 ps
CPU time 6.13 seconds
Started Dec 31 12:47:31 PM PST 23
Finished Dec 31 12:47:44 PM PST 23
Peak memory 199484 kb
Host smart-fa53904a-7193-4319-bf58-5ccf37d6b8ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507092788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.2507092788
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.444385819
Short name T122
Test name
Test status
Simulation time 154531957 ps
CPU time 1.18 seconds
Started Dec 31 12:47:28 PM PST 23
Finished Dec 31 12:47:35 PM PST 23
Peak memory 199324 kb
Host smart-f3354f7e-d334-4ea6-a59d-142713e36841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444385819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.444385819
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.1312127178
Short name T498
Test name
Test status
Simulation time 228866839 ps
CPU time 1.42 seconds
Started Dec 31 12:47:42 PM PST 23
Finished Dec 31 12:47:45 PM PST 23
Peak memory 199404 kb
Host smart-e0d13d1a-a48b-421b-ae0f-95899ad7091f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312127178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.1312127178
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.1456968015
Short name T601
Test name
Test status
Simulation time 332867039 ps
CPU time 2.14 seconds
Started Dec 31 12:47:24 PM PST 23
Finished Dec 31 12:47:29 PM PST 23
Peak memory 199220 kb
Host smart-791912c5-4a72-436c-8eac-6ffb584d9812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456968015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.1456968015
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.1464810034
Short name T282
Test name
Test status
Simulation time 92526175 ps
CPU time 0.82 seconds
Started Dec 31 12:47:27 PM PST 23
Finished Dec 31 12:47:34 PM PST 23
Peak memory 199328 kb
Host smart-fbfb480a-a696-4267-b162-b0159e9c6c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464810034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.1464810034
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.316122667
Short name T403
Test name
Test status
Simulation time 64149576 ps
CPU time 0.69 seconds
Started Dec 31 12:47:48 PM PST 23
Finished Dec 31 12:47:53 PM PST 23
Peak memory 199160 kb
Host smart-3439b409-a8ee-47e3-937f-20e376db36cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316122667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.316122667
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.1148768794
Short name T29
Test name
Test status
Simulation time 1883928024 ps
CPU time 6.92 seconds
Started Dec 31 12:47:48 PM PST 23
Finished Dec 31 12:47:57 PM PST 23
Peak memory 220760 kb
Host smart-4f9069fc-06de-439a-95e1-ab5417bdf8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148768794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.1148768794
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.19404868
Short name T588
Test name
Test status
Simulation time 244375641 ps
CPU time 1.13 seconds
Started Dec 31 12:47:33 PM PST 23
Finished Dec 31 12:47:39 PM PST 23
Peak memory 216468 kb
Host smart-6be1468d-5981-4be8-a70a-ab9bd28b9db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19404868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.19404868
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.706229014
Short name T256
Test name
Test status
Simulation time 128699009 ps
CPU time 0.74 seconds
Started Dec 31 12:47:49 PM PST 23
Finished Dec 31 12:47:51 PM PST 23
Peak memory 199148 kb
Host smart-3bc7c541-34a6-4c95-9511-922d2b42ed9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706229014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.706229014
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.488137380
Short name T427
Test name
Test status
Simulation time 1649089832 ps
CPU time 6.41 seconds
Started Dec 31 12:47:32 PM PST 23
Finished Dec 31 12:47:49 PM PST 23
Peak memory 199520 kb
Host smart-c78fb3bb-47ec-4e4c-a597-161cd51a24c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488137380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.488137380
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.3751564993
Short name T508
Test name
Test status
Simulation time 100356845 ps
CPU time 0.93 seconds
Started Dec 31 12:47:46 PM PST 23
Finished Dec 31 12:47:49 PM PST 23
Peak memory 199180 kb
Host smart-61c49a6e-8bb0-476a-9038-541e085693b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751564993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.3751564993
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.4084979756
Short name T324
Test name
Test status
Simulation time 2163666103 ps
CPU time 8.25 seconds
Started Dec 31 12:48:09 PM PST 23
Finished Dec 31 12:48:21 PM PST 23
Peak memory 199544 kb
Host smart-b6e381eb-0639-4212-8cda-f61c44119e0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084979756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.4084979756
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.2563135516
Short name T72
Test name
Test status
Simulation time 135323413 ps
CPU time 1.56 seconds
Started Dec 31 12:47:59 PM PST 23
Finished Dec 31 12:48:03 PM PST 23
Peak memory 199376 kb
Host smart-67550d81-f929-45d7-ab9c-8e828fd0a92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563135516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.2563135516
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.3971114635
Short name T375
Test name
Test status
Simulation time 97563845 ps
CPU time 0.82 seconds
Started Dec 31 12:47:42 PM PST 23
Finished Dec 31 12:47:46 PM PST 23
Peak memory 199268 kb
Host smart-e2349ac8-b29f-494b-a3ec-7849c2ac3179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971114635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.3971114635
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.2908321270
Short name T129
Test name
Test status
Simulation time 72771596 ps
CPU time 0.76 seconds
Started Dec 31 12:48:05 PM PST 23
Finished Dec 31 12:48:07 PM PST 23
Peak memory 199092 kb
Host smart-3b3abd4f-72c9-4ae1-a6b5-f23ce7f7cfdf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908321270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.2908321270
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.4222255034
Short name T384
Test name
Test status
Simulation time 1235088157 ps
CPU time 5.76 seconds
Started Dec 31 12:47:41 PM PST 23
Finished Dec 31 12:47:50 PM PST 23
Peak memory 217704 kb
Host smart-eab500f1-7e41-4471-a27d-24db799a9179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222255034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.4222255034
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.3810202676
Short name T433
Test name
Test status
Simulation time 244785809 ps
CPU time 1.08 seconds
Started Dec 31 12:48:10 PM PST 23
Finished Dec 31 12:48:15 PM PST 23
Peak memory 216476 kb
Host smart-1aa8efcd-3f1b-4b72-8a0a-6109f748590f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810202676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.3810202676
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.486913215
Short name T595
Test name
Test status
Simulation time 126065016 ps
CPU time 0.78 seconds
Started Dec 31 12:47:40 PM PST 23
Finished Dec 31 12:47:44 PM PST 23
Peak memory 199076 kb
Host smart-fffcec77-f5c5-4302-8dd4-74748d4a583c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486913215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.486913215
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.3756658434
Short name T120
Test name
Test status
Simulation time 1703208215 ps
CPU time 6.88 seconds
Started Dec 31 12:47:31 PM PST 23
Finished Dec 31 12:47:44 PM PST 23
Peak memory 199432 kb
Host smart-0a29d65a-ec57-467e-9e24-0c8c952ec189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756658434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.3756658434
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.681808517
Short name T315
Test name
Test status
Simulation time 172773483 ps
CPU time 1.09 seconds
Started Dec 31 12:47:44 PM PST 23
Finished Dec 31 12:47:47 PM PST 23
Peak memory 199328 kb
Host smart-255fc762-31ff-4e1d-ae0c-84ea90b73103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681808517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.681808517
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.2117839210
Short name T266
Test name
Test status
Simulation time 114622032 ps
CPU time 1.21 seconds
Started Dec 31 12:47:42 PM PST 23
Finished Dec 31 12:47:55 PM PST 23
Peak memory 199404 kb
Host smart-a2ddb22a-81e9-4964-a572-62da7a0e6f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117839210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.2117839210
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.3528191151
Short name T561
Test name
Test status
Simulation time 5530791446 ps
CPU time 23.01 seconds
Started Dec 31 12:47:36 PM PST 23
Finished Dec 31 12:48:05 PM PST 23
Peak memory 199396 kb
Host smart-dc8c374b-2ce1-4c64-8461-7d5c3d050563
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528191151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.3528191151
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.1220265022
Short name T242
Test name
Test status
Simulation time 142194653 ps
CPU time 1.67 seconds
Started Dec 31 12:47:58 PM PST 23
Finished Dec 31 12:48:02 PM PST 23
Peak memory 199272 kb
Host smart-78ed349b-98b9-4888-b7c5-d752bebd6d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220265022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.1220265022
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.2218368759
Short name T156
Test name
Test status
Simulation time 91456161 ps
CPU time 0.87 seconds
Started Dec 31 12:48:02 PM PST 23
Finished Dec 31 12:48:05 PM PST 23
Peak memory 199332 kb
Host smart-e2821eb4-1bcc-41d6-9864-7d7d1f3ee02b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218368759 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.2218368759
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.2370665125
Short name T127
Test name
Test status
Simulation time 77955056 ps
CPU time 0.77 seconds
Started Dec 31 12:47:34 PM PST 23
Finished Dec 31 12:47:39 PM PST 23
Peak memory 199148 kb
Host smart-25df7671-bea6-446b-848d-e59fd296b9c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370665125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.2370665125
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.660998485
Short name T38
Test name
Test status
Simulation time 1232455640 ps
CPU time 5.67 seconds
Started Dec 31 12:47:48 PM PST 23
Finished Dec 31 12:47:55 PM PST 23
Peak memory 221328 kb
Host smart-3f3c5de6-d075-400d-a878-dc3fe1f21a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660998485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.660998485
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.3659097387
Short name T589
Test name
Test status
Simulation time 244745867 ps
CPU time 1.12 seconds
Started Dec 31 12:48:01 PM PST 23
Finished Dec 31 12:48:05 PM PST 23
Peak memory 216516 kb
Host smart-35ed12bb-3489-4a6b-b9b9-ea56e66e2a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659097387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.3659097387
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.83273626
Short name T15
Test name
Test status
Simulation time 134708263 ps
CPU time 0.82 seconds
Started Dec 31 12:47:39 PM PST 23
Finished Dec 31 12:47:44 PM PST 23
Peak memory 199084 kb
Host smart-54f5d7d8-65c1-42e7-a83e-b4cf372feaef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83273626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.83273626
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.824323893
Short name T514
Test name
Test status
Simulation time 1640245222 ps
CPU time 6.9 seconds
Started Dec 31 12:48:00 PM PST 23
Finished Dec 31 12:48:09 PM PST 23
Peak memory 199476 kb
Host smart-ef860c85-35d0-414c-bf35-88f0593f6a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824323893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.824323893
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.814743593
Short name T249
Test name
Test status
Simulation time 104443926 ps
CPU time 1 seconds
Started Dec 31 12:47:59 PM PST 23
Finished Dec 31 12:48:02 PM PST 23
Peak memory 199288 kb
Host smart-eab67f03-7412-47f8-a83c-7cd3c4aee0e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814743593 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.814743593
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.2292261610
Short name T547
Test name
Test status
Simulation time 195904726 ps
CPU time 1.35 seconds
Started Dec 31 12:48:16 PM PST 23
Finished Dec 31 12:48:23 PM PST 23
Peak memory 199504 kb
Host smart-ded0fee2-998b-4d47-9d70-7fc094137ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292261610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.2292261610
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.2143990633
Short name T154
Test name
Test status
Simulation time 3970527263 ps
CPU time 13.45 seconds
Started Dec 31 12:47:53 PM PST 23
Finished Dec 31 12:48:08 PM PST 23
Peak memory 199460 kb
Host smart-e21ec343-6e66-4239-98e1-513444e324b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143990633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.2143990633
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.1859962996
Short name T504
Test name
Test status
Simulation time 454917022 ps
CPU time 2.35 seconds
Started Dec 31 12:47:58 PM PST 23
Finished Dec 31 12:48:02 PM PST 23
Peak memory 199260 kb
Host smart-0be3ddf1-de29-47e5-90e8-2e5de2961d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859962996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.1859962996
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.1826513390
Short name T533
Test name
Test status
Simulation time 242874951 ps
CPU time 1.34 seconds
Started Dec 31 12:48:08 PM PST 23
Finished Dec 31 12:48:12 PM PST 23
Peak memory 199332 kb
Host smart-3276dde8-251b-44db-9eae-3691905c1b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826513390 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.1826513390
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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