Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6234

1

T4

212

T66

4

T68

1

auto[1]

8657

1

T3

4

T4

181

T6

4

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4579	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	5063	1			T1	1		T2	1		T3	2
reset_info_cp[2]	2321	1			T3	1		T4	63		T6	1
reset_info_cp[4]	2964	1			T3	1		T4	110		T6	1
reset_info_cp[8]	78	1			T4	1		T29	1		T32	2
reset_info_cp[16]	97	1			T4	4		T14	1		T27	1
reset_info_cp[32]	94	1			T4	1		T29	2		T130	1
reset_info_cp[64]	116	1			T4	4		T29	1		T41	1
reset_info_cp[128]	100	1			T4	2		T11	1		T14	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	2457	1			T4	58		T66	4		T68	1
reset_info_cp[1]	auto[1]	2085	1			T3	1		T4	50		T6	1
reset_info_cp[2]	auto[0]	685	1			T4	24		T11	9		T12	2
reset_info_cp[2]	auto[1]	1636	1			T3	1		T4	39		T6	1
reset_info_cp[4]	auto[0]	1058	1			T4	56		T11	7		T12	6
reset_info_cp[4]	auto[1]	1906	1			T3	1		T4	54		T6	1
reset_info_cp[8]	auto[0]	25	1			T83	1		T134	1		T136	1
reset_info_cp[8]	auto[1]	53	1			T4	1		T29	1		T32	2
reset_info_cp[16]	auto[0]	30	1			T4	1		T41	2		T83	1
reset_info_cp[16]	auto[1]	67	1			T4	3		T14	1		T27	1
reset_info_cp[32]	auto[0]	34	1			T4	1		T135	1		T137	1
reset_info_cp[32]	auto[1]	60	1			T29	2		T130	1		T53	1
reset_info_cp[64]	auto[0]	45	1			T4	2		T43	1		T130	1
reset_info_cp[64]	auto[1]	71	1			T4	2		T29	1		T41	1
reset_info_cp[128]	auto[0]	42	1			T4	1		T11	1		T29	1
reset_info_cp[128]	auto[1]	58	1			T4	1		T14	1		T29	1