Assertions
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Assertions by Category
ASSERTPROPERTIESSEQUENCES
Total733010
Category 0733010


Assertions by Severity
ASSERTPROPERTIESSEQUENCES
Total733010
Severity 0733010


Summary for Assertions
NUMBERPERCENT
Total Number733100.00
Uncovered40.55
Success72999.45
Failure00.00
Incomplete00.00
Without Attempts00.00


Summary for Cover Sequences
NUMBERPERCENT
Total Number10100.00
Uncovered00.00
All Matches10100.00
First Matches10100.00


Detail Report for Assertions

Assertions Uncovered:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorAonEnTracksRstPorAonActive_A 001223397000
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorEnTracksRstPorInactive_A 0040371236000
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoDiv4EnTracksRstPorIoDiv4Active_A 009688787000
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoEnTracksRstPorIoInactive_A 0038754767000

Assertions Success:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
tb.dut.AlertsKnownO_A 008576729499208500
tb.dut.FpvSecCmRegWeOnehotCheck_A 0085767295000
tb.dut.ParameterMatch_A 0040740700
tb.dut.PwrKnownO_A 008576729499208500
tb.dut.ResetsKnownO_A 008576729499208500
tb.dut.RstEnKnownO_A 008576729499208500
tb.dut.TlAReadyKnownO_A 008576729499208500
tb.dut.TlDValidKnownO_A 008576729499208500
tb.dut.gen_d0_i2c0_assert.FpvSecCmD0I2c0FsmCheck_A 0085767295000
tb.dut.gen_d0_i2c1_assert.FpvSecCmD0I2c1FsmCheck_A 0085767295000
tb.dut.gen_d0_i2c2_assert.FpvSecCmD0I2c2FsmCheck_A 0085767295000
tb.dut.gen_d0_lc_assert.FpvSecCmD0LcFsmCheck_A 0085767295000
tb.dut.gen_d0_lc_io_assert.FpvSecCmD0LcIoFsmCheck_A 0085767295000
tb.dut.gen_d0_lc_io_div2_assert.FpvSecCmD0LcIoDiv2FsmCheck_A 0085767295000
tb.dut.gen_d0_lc_shadowed_assert.FpvSecCmD0LcShadowedFsmCheck_A 0085767295000
tb.dut.gen_d0_lc_usb_assert.FpvSecCmD0LcUsbFsmCheck_A 0085767295000
tb.dut.gen_d0_spi_device_assert.FpvSecCmD0SpiDeviceFsmCheck_A 0085767295000
tb.dut.gen_d0_spi_host0_assert.FpvSecCmD0SpiHost0FsmCheck_A 0085767295000
tb.dut.gen_d0_spi_host1_assert.FpvSecCmD0SpiHost1FsmCheck_A 0085767295000
tb.dut.gen_d0_sys_assert.FpvSecCmD0SysFsmCheck_A 0085767295000
tb.dut.gen_d0_usb_aon_assert.FpvSecCmD0UsbAonFsmCheck_A 0085767295000
tb.dut.gen_d0_usb_assert.FpvSecCmD0UsbFsmCheck_A 0085767295000
tb.dut.gen_daon_lc_aon_assert.FpvSecCmDAonLcAonFsmCheck_A 0085767295000
tb.dut.gen_daon_lc_assert.FpvSecCmDAonLcFsmCheck_A 0085767295000
tb.dut.gen_daon_lc_io_assert.FpvSecCmDAonLcIoFsmCheck_A 0085767295000
tb.dut.gen_daon_lc_io_div2_assert.FpvSecCmDAonLcIoDiv2FsmCheck_A 0085767295000
tb.dut.gen_daon_lc_shadowed_assert.FpvSecCmDAonLcShadowedFsmCheck_A 0085767295000
tb.dut.gen_daon_lc_usb_assert.FpvSecCmDAonLcUsbFsmCheck_A 0085767295000
tb.dut.gen_daon_por_assert.FpvSecCmDAonPorFsmCheck_A 0085767295000
tb.dut.gen_daon_por_io_assert.FpvSecCmDAonPorIoFsmCheck_A 0085767295000
tb.dut.gen_daon_por_io_div2_assert.FpvSecCmDAonPorIoDiv2FsmCheck_A 0085767295000
tb.dut.gen_daon_por_io_div4_assert.FpvSecCmDAonPorIoDiv4FsmCheck_A 0085767295000
tb.dut.gen_daon_por_usb_assert.FpvSecCmDAonPorUsbFsmCheck_A 0085767295000
tb.dut.gen_daon_sys_io_div4_assert.FpvSecCmDAonSysIoDiv4FsmCheck_A 0085767295000
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_prim_mubi4_sender.OutputsKnown_A 00122339774422800
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic.selKnown0 006925651800
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic.selKnown1 002014160700
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic.selKnown0 006490608300
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic.selKnown1 002014160700
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic.selKnown0 005362495500
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic.selKnown1 002014160700
tb.dut.gen_rst_por_aon[0].u_por_scanmode_sync.NumCopiesMustBeGreaterZero_A 0040740700
tb.dut.gen_rst_por_aon[0].u_por_scanmode_sync.OutputsKnown_A 008576729499208500
tb.dut.gen_rst_por_aon[0].u_por_scanmode_sync.gen_no_flops.OutputDelay_A 008576729499208500
tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic.selKnown0 006490608300
tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic.selKnown1 002014160700
tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_prim_mubi4_sender.OutputsKnown_A 00122339773057300
tb.dut.gen_rst_por_aon[1].u_por_scanmode_sync.NumCopiesMustBeGreaterZero_A 0040740700
tb.dut.gen_rst_por_aon[1].u_por_scanmode_sync.OutputsKnown_A 008576729499208500
tb.dut.gen_rst_por_aon[1].u_por_scanmode_sync.gen_no_flops.OutputDelay_A 008576729499208500
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[0].LcHandshakeOff_A 0085767291013100
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[0].LcHandshakeOn_A 0085767299342700
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[0].SysHandshakeOff_A 008576729502229100
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[0].SysHandshakeOn_A 00857672914903800
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[1].LcHandshakeOff_A 0085767291013100
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[1].LcHandshakeOn_A 0085767299342700
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[1].SysHandshakeOff_A 008576729502229100
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[1].SysHandshakeOn_A 00857672914903800
tb.dut.rstmgr_attrs_sva_if.AlertInfoAttr_A 0040740700
tb.dut.rstmgr_attrs_sva_if.CpuInfoAttr_A 0040740700
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorAboveFall_A 0040371236649000
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorAboveRise_A 0040371236649000
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoAboveFall_A 0038754767649000
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoAboveRise_A 0038754767649000
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoDiv2AboveFall_A 0019377970649000
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoDiv2AboveRise_A 0019377970649000
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoDiv4AboveFall_A 009688787649000
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoDiv4AboveRise_A 009688787649000
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorUcbAboveFall_A 0019377952649000
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorUcbAboveRise_A 0019377952649000
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcAboveFall_A 00403712361662100
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcAboveRise_A 00403712361662100
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcAonAboveFall_A 0012233971662100
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcAonAboveRise_A 0012233971662100
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcShadowedAboveFall_A 00403712361662100
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcShadowedAboveRise_A 00403712361662100
tb.dut.rstmgr_cascading_sva_if.CascadePorToAonAboveFall_A 001223397536700
tb.dut.rstmgr_cascading_sva_if.CascadeSysToSysAboveFall_A 00403712361662100
tb.dut.rstmgr_cascading_sva_if.CascadeSysToSysAboveRise_A 00403712361662100
tb.dut.rstmgr_cascading_sva_if.ScanRstToAonRise_A 00122339715500
tb.dut.rstmgr_cascading_sva_if.StablePorToAonRise_A 001223397649000
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].CascadeLcToSysAboveFall_A 0085767291662100
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].CascadeLcToSysAboveRise_A 0085767291662100
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].CascadeLocalRstToLcAboveFall_A 0085767291662100
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].CascadeLocalRstToLcAboveRise_A 0085767291662100
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A 0096887871662100
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A 0096887871662100
tb.dut.rstmgr_cascading_sva_if.g_power_domains[1].CascadeLcToSysAboveFall_A 0085767291662100
tb.dut.rstmgr_cascading_sva_if.g_power_domains[1].CascadeLcToSysAboveRise_A 0085767291662100
tb.dut.rstmgr_cascading_sva_if.g_power_domains[1].CascadeLocalRstToLcAboveFall_A 0085767291662100
tb.dut.rstmgr_cascading_sva_if.g_power_domains[1].CascadeLocalRstToLcAboveRise_A 0085767291662100
tb.dut.rstmgr_csr_assert.TlulOOBAddrErr_A 009345780813100
tb.dut.rstmgr_csr_assert.alert_regwen_rd_A 009345780548400
tb.dut.rstmgr_csr_assert.cpu_regwen_rd_A 009345780553200
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_0_rd_A 009345780825200
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_1_rd_A 009345780834800
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_2_rd_A 009345780818500
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_3_rd_A 009345780810100
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_4_rd_A 009345780807500
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_5_rd_A 009345780831500
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_6_rd_A 009345780787700
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_7_rd_A 009345780819000
tb.dut.rstmgr_csr_assert.sw_rst_regwen_0_rd_A 009345780573900
tb.dut.rstmgr_csr_assert.sw_rst_regwen_1_rd_A 009345780590400
tb.dut.rstmgr_csr_assert.sw_rst_regwen_2_rd_A 009345780563700
tb.dut.rstmgr_csr_assert.sw_rst_regwen_3_rd_A 009345780592300
tb.dut.rstmgr_csr_assert.sw_rst_regwen_4_rd_A 009345780565100
tb.dut.rstmgr_csr_assert.sw_rst_regwen_5_rd_A 009345780588800
tb.dut.rstmgr_csr_assert.sw_rst_regwen_6_rd_A 009345780611500
tb.dut.rstmgr_csr_assert.sw_rst_regwen_7_rd_A 009345780575300
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c0EnTracksRstI2c0Active_A 0096887871098400
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c0EnTracksRstI2c0Inactive_A 0096887871738800
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c1EnTracksRstI2c1Active_A 0096887871105700
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c1EnTracksRstI2c1Inactive_A 0096887871745800
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c2EnTracksRstI2c2Active_A 0096887871107400
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c2EnTracksRstI2c2Inactive_A 0096887871747500
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoDiv2EnTracksRstLcIoDiv2Active_A 00193779701019700
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoDiv2EnTracksRstLcIoDiv2Inactive_A 00193779701662100
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoDiv4ShadowedEnTracksRstLcIoDiv4ShadowedActive_A 0096887871021100
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoDiv4ShadowedEnTracksRstLcIoDiv4ShadowedInactive_A 0096887871665900
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoEnTracksRstLcIoActive_A 00387547671019300
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoEnTracksRstLcIoInactive_A 00387547671662100
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcShadowedEnTracksRstLcShadowedActive_A 00403712361017300
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcShadowedEnTracksRstLcShadowedInactive_A 00403712361662100
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcUsbEnTracksRstLcUsbActive_A 00193779521019300
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcUsbEnTracksRstLcUsbInactive_A 00193779521662100
tb.dut.rstmgr_rst_en_track_sva_if.D0RstPorAonEnTracksRstPorAonActive_A 0012233974200
tb.dut.rstmgr_rst_en_track_sva_if.D0RstPorAonEnTracksRstPorAonInactive_A 001223397647300
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiDeviceEnTracksRstSpiDeviceActive_A 0096887871082000
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiDeviceEnTracksRstSpiDeviceInactive_A 0096887871721900
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiHost0EnTracksRstSpiHost0Active_A 00387547671084400
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiHost0EnTracksRstSpiHost0Inactive_A 00387547671725500
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiHost1EnTracksRstSpiHost1Active_A 00193779701087200
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiHost1EnTracksRstSpiHost1Inactive_A 00193779701727600
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSysEnTracksRstSysActive_A 00403712361019400
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSysEnTracksRstSysInactive_A 00403712361662100
tb.dut.rstmgr_rst_en_track_sva_if.D0RstUsbAonEnTracksRstUsbAonActive_A 0012233971041500
tb.dut.rstmgr_rst_en_track_sva_if.D0RstUsbAonEnTracksRstUsbAonInactive_A 0012233971650900
tb.dut.rstmgr_rst_en_track_sva_if.D0RstUsbEnTracksRstUsbActive_A 00193779521094300
tb.dut.rstmgr_rst_en_track_sva_if.D0RstUsbEnTracksRstUsbInactive_A 00193779521734400
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcAonEnTracksRstLcAonActive_A 0012233971014700
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcAonEnTracksRstLcAonInactive_A 0012233971660400
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoDiv2EnTracksRstLcIoDiv2Active_A 00193779701015700
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoDiv2EnTracksRstLcIoDiv2Inactive_A 00193779701662100
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoDiv4ShadowedEnTracksRstLcIoDiv4ShadowedActive_A 0096887871016900
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoDiv4ShadowedEnTracksRstLcIoDiv4ShadowedInactive_A 0096887871665900
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoEnTracksRstLcIoActive_A 00387547671015100
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoEnTracksRstLcIoInactive_A 00387547671662100
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcShadowedEnTracksRstLcShadowedActive_A 00403712361019100
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcShadowedEnTracksRstLcShadowedInactive_A 00403712361665900
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcUsbEnTracksRstLcUsbActive_A 00193779521014800
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcUsbEnTracksRstLcUsbInactive_A 00193779521662100
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorAonEnTracksRstPorAonInactive_A 001223397649000
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorEnTracksRstPorActive_A 00403712362100
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoDiv2EnTracksRstPorIoDiv2Active_A 00193779702500
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoDiv2EnTracksRstPorIoDiv2Inactive_A 0019377970155000
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoDiv4EnTracksRstPorIoDiv4Inactive_A 009688787649000
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoEnTracksRstPorIoActive_A 00387547672500
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorUsbEnTracksRstPorUsbActive_A 00193779522100
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorUsbEnTracksRstPorUsbInactive_A 0019377952155000
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstSysIoDiv4EnTracksRstSysIoDiv4Active_A 0096887871014900
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstSysIoDiv4EnTracksRstSysIoDiv4Inactive_A 0096887871662100
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[0].RstEnOff_A 0096887871072900
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[0].RstEnOn_A 00968878775100
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[0].RstNOff_A 0096887871072900
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[0].RstNOn_A 00968878775100
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[1].RstEnOff_A 0038754767975800
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[1].RstEnOn_A 003875476770900
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[1].RstNOff_A 0038754767975800
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[1].RstNOn_A 003875476770900
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[2].RstEnOff_A 0019377970977800
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[2].RstEnOn_A 001937797068600
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[2].RstNOff_A 0019377970977800
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[2].RstNOn_A 001937797068600
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[3].RstEnOff_A 0019377952984500
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[3].RstEnOn_A 001937795274800
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[3].RstNOff_A 0019377952984500
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[3].RstNOn_A 001937795274800
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[4].RstEnOff_A 0012233971615200
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[4].RstEnOn_A 00122339777500
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[4].RstNOff_A 0012233971615200
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[4].RstNOn_A 00122339777500
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tb.dut.tlul_assert_device.aKnown_A 00934578088030300
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tb.dut.tlul_assert_device.aReadyKnown_A 009345780548793800
tb.dut.tlul_assert_device.dKnown_A 009345780162042400
tb.dut.tlul_assert_device.dKnown_AKnownEnable 009345780548793800
tb.dut.tlul_assert_device.dReadyKnown_A 009345780548793800
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tb.dut.tlul_assert_device.gen_assert_final[4].noOutstandingReqsAtEndOfSim_A 0052152100
tb.dut.tlul_assert_device.gen_assert_final[50].noOutstandingReqsAtEndOfSim_A 0052152100
tb.dut.tlul_assert_device.gen_assert_final[51].noOutstandingReqsAtEndOfSim_A 0052152100
tb.dut.tlul_assert_device.gen_assert_final[52].noOutstandingReqsAtEndOfSim_A 0052152100
tb.dut.tlul_assert_device.gen_assert_final[53].noOutstandingReqsAtEndOfSim_A 0052152100
tb.dut.tlul_assert_device.gen_assert_final[54].noOutstandingReqsAtEndOfSim_A 0052152100
tb.dut.tlul_assert_device.gen_assert_final[55].noOutstandingReqsAtEndOfSim_A 0052152100
tb.dut.tlul_assert_device.gen_assert_final[56].noOutstandingReqsAtEndOfSim_A 0052152100
tb.dut.tlul_assert_device.gen_assert_final[57].noOutstandingReqsAtEndOfSim_A 0052152100
tb.dut.tlul_assert_device.gen_assert_final[58].noOutstandingReqsAtEndOfSim_A 0052152100
tb.dut.tlul_assert_device.gen_assert_final[59].noOutstandingReqsAtEndOfSim_A 0052152100
tb.dut.tlul_assert_device.gen_assert_final[5].noOutstandingReqsAtEndOfSim_A 0052152100
tb.dut.tlul_assert_device.gen_assert_final[60].noOutstandingReqsAtEndOfSim_A 0052152100
tb.dut.tlul_assert_device.gen_assert_final[61].noOutstandingReqsAtEndOfSim_A 0052152100
tb.dut.tlul_assert_device.gen_assert_final[62].noOutstandingReqsAtEndOfSim_A 0052152100
tb.dut.tlul_assert_device.gen_assert_final[63].noOutstandingReqsAtEndOfSim_A 0052152100
tb.dut.tlul_assert_device.gen_assert_final[64].noOutstandingReqsAtEndOfSim_A 0052152100
tb.dut.tlul_assert_device.gen_assert_final[65].noOutstandingReqsAtEndOfSim_A 0052152100
tb.dut.tlul_assert_device.gen_assert_final[66].noOutstandingReqsAtEndOfSim_A 0052152100
tb.dut.tlul_assert_device.gen_assert_final[67].noOutstandingReqsAtEndOfSim_A 0052152100
tb.dut.tlul_assert_device.gen_assert_final[68].noOutstandingReqsAtEndOfSim_A 0052152100
tb.dut.tlul_assert_device.gen_assert_final[69].noOutstandingReqsAtEndOfSim_A 0052152100
tb.dut.tlul_assert_device.gen_assert_final[6].noOutstandingReqsAtEndOfSim_A 0052152100
tb.dut.tlul_assert_device.gen_assert_final[70].noOutstandingReqsAtEndOfSim_A 0052152100
tb.dut.tlul_assert_device.gen_assert_final[71].noOutstandingReqsAtEndOfSim_A 0052152100
tb.dut.tlul_assert_device.gen_assert_final[72].noOutstandingReqsAtEndOfSim_A 0052152100
tb.dut.tlul_assert_device.gen_assert_final[73].noOutstandingReqsAtEndOfSim_A 0052152100
tb.dut.tlul_assert_device.gen_assert_final[74].noOutstandingReqsAtEndOfSim_A 0052152100
tb.dut.tlul_assert_device.gen_assert_final[75].noOutstandingReqsAtEndOfSim_A 0052152100
tb.dut.tlul_assert_device.gen_assert_final[76].noOutstandingReqsAtEndOfSim_A 0052152100
tb.dut.tlul_assert_device.gen_assert_final[77].noOutstandingReqsAtEndOfSim_A 0052152100
tb.dut.tlul_assert_device.gen_assert_final[78].noOutstandingReqsAtEndOfSim_A 0052152100
tb.dut.tlul_assert_device.gen_assert_final[79].noOutstandingReqsAtEndOfSim_A 0052152100
tb.dut.tlul_assert_device.gen_assert_final[7].noOutstandingReqsAtEndOfSim_A 0052152100
tb.dut.tlul_assert_device.gen_assert_final[80].noOutstandingReqsAtEndOfSim_A 0052152100
tb.dut.tlul_assert_device.gen_assert_final[81].noOutstandingReqsAtEndOfSim_A 0052152100
tb.dut.tlul_assert_device.gen_assert_final[82].noOutstandingReqsAtEndOfSim_A 0052152100
tb.dut.tlul_assert_device.gen_assert_final[83].noOutstandingReqsAtEndOfSim_A 0052152100
tb.dut.tlul_assert_device.gen_assert_final[84].noOutstandingReqsAtEndOfSim_A 0052152100
tb.dut.tlul_assert_device.gen_assert_final[85].noOutstandingReqsAtEndOfSim_A 0052152100
tb.dut.tlul_assert_device.gen_assert_final[86].noOutstandingReqsAtEndOfSim_A 0052152100
tb.dut.tlul_assert_device.gen_assert_final[87].noOutstandingReqsAtEndOfSim_A 0052152100
tb.dut.tlul_assert_device.gen_assert_final[88].noOutstandingReqsAtEndOfSim_A 0052152100
tb.dut.tlul_assert_device.gen_assert_final[89].noOutstandingReqsAtEndOfSim_A 0052152100
tb.dut.tlul_assert_device.gen_assert_final[8].noOutstandingReqsAtEndOfSim_A 0052152100
tb.dut.tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A 0052152100
tb.dut.tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A 0052152100
tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A 0052152100
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A 0052152100
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A 0052152100
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A 0052152100
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A 0052152100
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A 0052152100
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A 0052152100
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A 0052152100
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A 0052152100
tb.dut.tlul_assert_device.gen_device.aDataKnown_M 00934630139167300
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A 009345780554000
tb.dut.tlul_assert_device.gen_device.contigMask_M 00934630163616500
tb.dut.tlul_assert_device.gen_device.dDataKnown_A 00934630183329100
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A 009345780597500
tb.dut.tlul_assert_device.gen_device.legalAParam_M 00934630188042900
tb.dut.tlul_assert_device.gen_device.legalDParam_A 009346301162058100
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M 00934630188042900
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A 009346301162058100
tb.dut.tlul_assert_device.gen_device.respOpcode_A 009346301162058100
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A 009346301162058100
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A 009345780330200
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A 009345780282500
tb.dut.tlul_assert_device.p_dbw.TlDbw_A 0052152100
tb.dut.u_alert_info.CntStoreSlot_A 0040740700
tb.dut.u_alert_info.CntWidth_A 0040740700
tb.dut.u_cpu_info.CntStoreSlot_A 0040740700
tb.dut.u_cpu_info.CntWidth_A 0040740700
tb.dut.u_ctrl_scanmode_sync.NumCopiesMustBeGreaterZero_A 0040740700
tb.dut.u_ctrl_scanmode_sync.OutputsKnown_A 009688787583554100
tb.dut.u_ctrl_scanmode_sync.gen_no_flops.OutputDelay_A 009688787583554100
tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00166591625200
tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002014160700
tb.dut.u_d0_i2c0.u_prim_mubi4_sender.OutputsKnown_A 009688787493200100
tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00173881698100
tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002014160700
tb.dut.u_d0_i2c0.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0040740700
tb.dut.u_d0_i2c0.u_scanmode_sync.OutputsKnown_A 008576729499208500
tb.dut.u_d0_i2c0.u_scanmode_sync.gen_no_flops.OutputDelay_A 008576729499208500
tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00166591625200
tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002014160700
tb.dut.u_d0_i2c1.u_prim_mubi4_sender.OutputsKnown_A 009688787492168100
tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00174581705100
tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002014160700
tb.dut.u_d0_i2c1.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0040740700
tb.dut.u_d0_i2c1.u_scanmode_sync.OutputsKnown_A 008576729499208500
tb.dut.u_d0_i2c1.u_scanmode_sync.gen_no_flops.OutputDelay_A 008576729499208500
tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00166591625200
tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002014160700
tb.dut.u_d0_i2c2.u_prim_mubi4_sender.OutputsKnown_A 009688787493000900
tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00174741706700
tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002014160700
tb.dut.u_d0_i2c2.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0040740700
tb.dut.u_d0_i2c2.u_scanmode_sync.OutputsKnown_A 008576729499208500
tb.dut.u_d0_i2c2.u_scanmode_sync.gen_no_flops.OutputDelay_A 008576729499208500
tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00166591625200
tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002014160700
tb.dut.u_d0_lc.u_prim_mubi4_sender.OutputsKnown_A 00403712362100785400
tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00166211621400
tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002014160700
tb.dut.u_d0_lc.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0040740700
tb.dut.u_d0_lc.u_scanmode_sync.OutputsKnown_A 008576729499208500
tb.dut.u_d0_lc.u_scanmode_sync.gen_no_flops.OutputDelay_A 008576729499208500
tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00166591625200
tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002014160700
tb.dut.u_d0_lc_io.u_prim_mubi4_sender.OutputsKnown_A 00387547672016637000
tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00166211621400
tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002014160700
tb.dut.u_d0_lc_io.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0040740700
tb.dut.u_d0_lc_io.u_scanmode_sync.OutputsKnown_A 008576729499208500
tb.dut.u_d0_lc_io.u_scanmode_sync.gen_no_flops.OutputDelay_A 008576729499208500
tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00166591625200
tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002014160700
tb.dut.u_d0_lc_io_div2.u_prim_mubi4_sender.OutputsKnown_A 00193779701007555200
tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00166211621400
tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002014160700
tb.dut.u_d0_lc_io_div2.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0040740700
tb.dut.u_d0_lc_io_div2.u_scanmode_sync.OutputsKnown_A 008576729499208500
tb.dut.u_d0_lc_io_div2.u_scanmode_sync.gen_no_flops.OutputDelay_A 008576729499208500
tb.dut.u_d0_lc_io_div4.u_prim_mubi4_sender.OutputsKnown_A 009688787501681600
tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00166211621400
tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002014160700
tb.dut.u_d0_lc_io_div4.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0040740700
tb.dut.u_d0_lc_io_div4.u_scanmode_sync.OutputsKnown_A 008576729499208500
tb.dut.u_d0_lc_io_div4.u_scanmode_sync.gen_no_flops.OutputDelay_A 008576729499208500
tb.dut.u_d0_lc_io_div4_shadowed.u_prim_mubi4_sender.OutputsKnown_A 009688787501681600
tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00166211621400
tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002014160700
tb.dut.u_d0_lc_io_div4_shadowed.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0040740700
tb.dut.u_d0_lc_io_div4_shadowed.u_scanmode_sync.OutputsKnown_A 008576729499208500
tb.dut.u_d0_lc_io_div4_shadowed.u_scanmode_sync.gen_no_flops.OutputDelay_A 008576729499208500
tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00166591625200
tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002014160700
tb.dut.u_d0_lc_shadowed.u_prim_mubi4_sender.OutputsKnown_A 00403712362100939700
tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00166211621400
tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002014160700
tb.dut.u_d0_lc_shadowed.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0040740700
tb.dut.u_d0_lc_shadowed.u_scanmode_sync.OutputsKnown_A 008576729499208500
tb.dut.u_d0_lc_shadowed.u_scanmode_sync.gen_no_flops.OutputDelay_A 008576729499208500
tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00166591625200
tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002014160700
tb.dut.u_d0_lc_usb.u_prim_mubi4_sender.OutputsKnown_A 00193779521007549100
tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00166211621400
tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002014160700
tb.dut.u_d0_lc_usb.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0040740700
tb.dut.u_d0_lc_usb.u_scanmode_sync.OutputsKnown_A 008576729499208500
tb.dut.u_d0_lc_usb.u_scanmode_sync.gen_no_flops.OutputDelay_A 008576729499208500
tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00166591625200
tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002014160700
tb.dut.u_d0_spi_device.u_prim_mubi4_sender.OutputsKnown_A 009688787492717200
tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00172191681200
tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002014160700
tb.dut.u_d0_spi_device.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0040740700
tb.dut.u_d0_spi_device.u_scanmode_sync.OutputsKnown_A 008576729499208500
tb.dut.u_d0_spi_device.u_scanmode_sync.gen_no_flops.OutputDelay_A 008576729499208500
tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00166591625200
tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002014160700
tb.dut.u_d0_spi_host0.u_prim_mubi4_sender.OutputsKnown_A 00387547671981965400
tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00172551684800
tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002014160700
tb.dut.u_d0_spi_host0.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0040740700
tb.dut.u_d0_spi_host0.u_scanmode_sync.OutputsKnown_A 008576729499208500
tb.dut.u_d0_spi_host0.u_scanmode_sync.gen_no_flops.OutputDelay_A 008576729499208500
tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00166591625200
tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002014160700
tb.dut.u_d0_spi_host1.u_prim_mubi4_sender.OutputsKnown_A 0019377970989664800
tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00172751686800
tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002014160700
tb.dut.u_d0_spi_host1.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0040740700
tb.dut.u_d0_spi_host1.u_scanmode_sync.OutputsKnown_A 008576729499208500
tb.dut.u_d0_spi_host1.u_scanmode_sync.gen_no_flops.OutputDelay_A 008576729499208500
tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00166591625200
tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002014160700
tb.dut.u_d0_sys.u_prim_mubi4_sender.OutputsKnown_A 00403712362077654800
tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00166211621400
tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002014160700
tb.dut.u_d0_sys.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0040740700
tb.dut.u_d0_sys.u_scanmode_sync.OutputsKnown_A 008576729499208500
tb.dut.u_d0_sys.u_scanmode_sync.gen_no_flops.OutputDelay_A 008576729499208500
tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00166591625200
tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002014160700
tb.dut.u_d0_usb.u_prim_mubi4_sender.OutputsKnown_A 0019377952988294600
tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00173421693500
tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002014160700
tb.dut.u_d0_usb.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0040740700
tb.dut.u_d0_usb.u_scanmode_sync.OutputsKnown_A 008576729499208500
tb.dut.u_d0_usb.u_scanmode_sync.gen_no_flops.OutputDelay_A 008576729499208500
tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00165661615900
tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002014160700
tb.dut.u_d0_usb_aon.u_prim_mubi4_sender.OutputsKnown_A 00122339761080700
tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00173471694000
tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002014160700
tb.dut.u_d0_usb_aon.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0040740700
tb.dut.u_d0_usb_aon.u_scanmode_sync.OutputsKnown_A 008576729499208500
tb.dut.u_d0_usb_aon.u_scanmode_sync.gen_no_flops.OutputDelay_A 008576729499208500
tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00166591625200
tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002014160700
tb.dut.u_daon_lc.u_prim_mubi4_sender.OutputsKnown_A 00403712362154644800
tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00166211621400
tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002014160700
tb.dut.u_daon_lc.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0040740700
tb.dut.u_daon_lc.u_scanmode_sync.OutputsKnown_A 008576729499208500
tb.dut.u_daon_lc.u_scanmode_sync.gen_no_flops.OutputDelay_A 008576729499208500
tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00165661615900
tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002014160700
tb.dut.u_daon_lc_aon.u_prim_mubi4_sender.OutputsKnown_A 00122339763907700
tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00166211621400
tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002014160700
tb.dut.u_daon_lc_aon.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0040740700
tb.dut.u_daon_lc_aon.u_scanmode_sync.OutputsKnown_A 008576729499208500
tb.dut.u_daon_lc_aon.u_scanmode_sync.gen_no_flops.OutputDelay_A 008576729499208500
tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00166591625200
tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002014160700
tb.dut.u_daon_lc_io.u_prim_mubi4_sender.OutputsKnown_A 00387547672068451200
tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00166211621400
tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002014160700
tb.dut.u_daon_lc_io.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0040740700
tb.dut.u_daon_lc_io.u_scanmode_sync.OutputsKnown_A 008576729499208500
tb.dut.u_daon_lc_io.u_scanmode_sync.gen_no_flops.OutputDelay_A 008576729499208500
tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00166591625200
tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002014160700
tb.dut.u_daon_lc_io_div2.u_prim_mubi4_sender.OutputsKnown_A 00193779701033447100
tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00166211621400
tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002014160700
tb.dut.u_daon_lc_io_div2.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0040740700
tb.dut.u_daon_lc_io_div2.u_scanmode_sync.OutputsKnown_A 008576729499208500
tb.dut.u_daon_lc_io_div2.u_scanmode_sync.gen_no_flops.OutputDelay_A 008576729499208500
tb.dut.u_daon_lc_io_div4.u_prim_mubi4_sender.OutputsKnown_A 009688787514631600
tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00166211621400
tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002014160700
tb.dut.u_daon_lc_io_div4.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0040740700
tb.dut.u_daon_lc_io_div4.u_scanmode_sync.OutputsKnown_A 008576729499208500
tb.dut.u_daon_lc_io_div4.u_scanmode_sync.gen_no_flops.OutputDelay_A 008576729499208500
tb.dut.u_daon_lc_io_div4_shadowed.u_prim_mubi4_sender.OutputsKnown_A 009688787514631600
tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00166211621400
tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002014160700
tb.dut.u_daon_lc_io_div4_shadowed.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0040740700
tb.dut.u_daon_lc_io_div4_shadowed.u_scanmode_sync.OutputsKnown_A 008576729499208500
tb.dut.u_daon_lc_io_div4_shadowed.u_scanmode_sync.gen_no_flops.OutputDelay_A 008576729499208500
tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00166591625200
tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002014160700
tb.dut.u_daon_lc_shadowed.u_prim_mubi4_sender.OutputsKnown_A 00403712362154621900
tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00166211621400
tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002014160700
tb.dut.u_daon_lc_shadowed.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0040740700
tb.dut.u_daon_lc_shadowed.u_scanmode_sync.OutputsKnown_A 008576729499208500
tb.dut.u_daon_lc_shadowed.u_scanmode_sync.gen_no_flops.OutputDelay_A 008576729499208500
tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00166591625200
tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002014160700
tb.dut.u_daon_lc_usb.u_prim_mubi4_sender.OutputsKnown_A 00193779521033460600
tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00166211621400
tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002014160700
tb.dut.u_daon_lc_usb.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0040740700
tb.dut.u_daon_lc_usb.u_scanmode_sync.OutputsKnown_A 008576729499208500
tb.dut.u_daon_lc_usb.u_scanmode_sync.gen_no_flops.OutputDelay_A 008576729499208500
tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00166591625200
tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002014160700
tb.dut.u_daon_por.u_prim_mubi4_sender.OutputsKnown_A 00403712362433128400
tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic.selKnown0 006490608300
tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002014160700
tb.dut.u_daon_por.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0040740700
tb.dut.u_daon_por.u_scanmode_sync.OutputsKnown_A 008576729499208500
tb.dut.u_daon_por.u_scanmode_sync.gen_no_flops.OutputDelay_A 008576729499208500
tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00166591625200
tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002014160700
tb.dut.u_daon_por_io.u_prim_mubi4_sender.OutputsKnown_A 00387547672335671800
tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic.selKnown0 006490608300
tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002014160700
tb.dut.u_daon_por_io.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0040740700
tb.dut.u_daon_por_io.u_scanmode_sync.OutputsKnown_A 008576729499208500
tb.dut.u_daon_por_io.u_scanmode_sync.gen_no_flops.OutputDelay_A 008576729499208500
tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00166591625200
tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002014160700
tb.dut.u_daon_por_io_div2.u_prim_mubi4_sender.OutputsKnown_A 00193779701167573600
tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown0 006490608300
tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002014160700
tb.dut.u_daon_por_io_div2.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0040740700
tb.dut.u_daon_por_io_div2.u_scanmode_sync.OutputsKnown_A 008576729499208500
tb.dut.u_daon_por_io_div2.u_scanmode_sync.gen_no_flops.OutputDelay_A 008576729499208500
tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00166591625200
tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002014160700
tb.dut.u_daon_por_io_div4.u_prim_mubi4_sender.OutputsKnown_A 009688787583554100
tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown0 006490608300
tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002014160700
tb.dut.u_daon_por_io_div4.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0040740700
tb.dut.u_daon_por_io_div4.u_scanmode_sync.OutputsKnown_A 008576729499208500
tb.dut.u_daon_por_io_div4.u_scanmode_sync.gen_no_flops.OutputDelay_A 008576729499208500
tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00166591625200
tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002014160700
tb.dut.u_daon_por_usb.u_prim_mubi4_sender.OutputsKnown_A 00193779521167574900
tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown0 006490608300
tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002014160700
tb.dut.u_daon_por_usb.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0040740700
tb.dut.u_daon_por_usb.u_scanmode_sync.OutputsKnown_A 008576729499208500
tb.dut.u_daon_por_usb.u_scanmode_sync.gen_no_flops.OutputDelay_A 008576729499208500
tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00166591625200
tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002014160700
tb.dut.u_daon_sys_io_div4.u_prim_mubi4_sender.OutputsKnown_A 009688787509083600
tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00166211621400
tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002014160700
tb.dut.u_daon_sys_io_div4.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0040740700
tb.dut.u_daon_sys_io_div4.u_scanmode_sync.OutputsKnown_A 008576729499208500
tb.dut.u_daon_sys_io_div4.u_scanmode_sync.gen_no_flops.OutputDelay_A 008576729499208500
tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic.selKnown0 00166211621400
tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic.selKnown1 002014160700
tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic.selKnown0 00166211621400
tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic.selKnown1 002014160700
tb.dut.u_reg.en2addrHit 00934578074720400
tb.dut.u_reg.reAfterRv 00934578074708300
tb.dut.u_reg.rePulse 00934578039933000
tb.dut.u_reg.u_chk.PayLoadWidthCheck 0052152100
tb.dut.u_reg.u_reg_if.AllowedLatency_A 0052152100
tb.dut.u_reg.u_reg_if.MatchedWidthAssert 0052152100
tb.dut.u_reg.u_reg_if.u_err.dataWidthOnly32_A 0052152100
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A 0052152100
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck 0052152100
tb.dut.u_reg.u_rsp_intg_gen.DataWidthCheck_A 0052152100
tb.dut.u_reg.u_rsp_intg_gen.PayLoadWidthCheck 0052152100
tb.dut.u_reg.wePulse 00934578034775300
tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic.selKnown0 00166211621400
tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic.selKnown1 002014160700
tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic.selKnown0 00166211621400
tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic.selKnown1 002014160700


Detail Report for Cover Sequences

Cover Sequences All Matches:
COVER SEQUENCESCATEGORYSEVERITYATTEMPTSALL MATCHESFIRST MATCHESINCOMPLETESRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C 009346301496649660
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C 009346301209820981
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C 009346301210521051
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C 009346301147014701
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C 00934630198981
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C 009346301116411641
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C 0093463019619611
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C 009346301383338330
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C 00934630137289372890
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C 009346301366880366880377

Cover Sequences First Matches:
COVER SEQUENCESCATEGORYSEVERITYATTEMPTSALL MATCHESFIRST MATCHESINCOMPLETESRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C 009346301496649660
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C 009346301209820981
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C 009346301210521051
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C 009346301147014701
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C 00934630198981
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C 009346301116411641
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C 0093463019619611
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C 009346301383338330
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C 00934630137289372890
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C 009346301366880366880377

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