---

Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorAonEnTracksRstPorAonActive_A	0	0	1223397	0	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorEnTracksRstPorInactive_A	0	0	40371236	0	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoDiv4EnTracksRstPorIoDiv4Active_A	0	0	9688787	0	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoEnTracksRstPorIoInactive_A	0	0	38754767	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AlertsKnownO_A	0	0	8576729	4992085	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	8576729	50	0	0
tb.dut.ParameterMatch_A	0	0	407	407	0	0
tb.dut.PwrKnownO_A	0	0	8576729	4992085	0	0
tb.dut.ResetsKnownO_A	0	0	8576729	4992085	0	0
tb.dut.RstEnKnownO_A	0	0	8576729	4992085	0	0
tb.dut.TlAReadyKnownO_A	0	0	8576729	4992085	0	0
tb.dut.TlDValidKnownO_A	0	0	8576729	4992085	0	0
tb.dut.gen_d0_i2c0_assert.FpvSecCmD0I2c0FsmCheck_A	0	0	8576729	50	0	0
tb.dut.gen_d0_i2c1_assert.FpvSecCmD0I2c1FsmCheck_A	0	0	8576729	50	0	0
tb.dut.gen_d0_i2c2_assert.FpvSecCmD0I2c2FsmCheck_A	0	0	8576729	50	0	0
tb.dut.gen_d0_lc_assert.FpvSecCmD0LcFsmCheck_A	0	0	8576729	50	0	0
tb.dut.gen_d0_lc_io_assert.FpvSecCmD0LcIoFsmCheck_A	0	0	8576729	50	0	0
tb.dut.gen_d0_lc_io_div2_assert.FpvSecCmD0LcIoDiv2FsmCheck_A	0	0	8576729	50	0	0
tb.dut.gen_d0_lc_shadowed_assert.FpvSecCmD0LcShadowedFsmCheck_A	0	0	8576729	50	0	0
tb.dut.gen_d0_lc_usb_assert.FpvSecCmD0LcUsbFsmCheck_A	0	0	8576729	50	0	0
tb.dut.gen_d0_spi_device_assert.FpvSecCmD0SpiDeviceFsmCheck_A	0	0	8576729	50	0	0
tb.dut.gen_d0_spi_host0_assert.FpvSecCmD0SpiHost0FsmCheck_A	0	0	8576729	50	0	0
tb.dut.gen_d0_spi_host1_assert.FpvSecCmD0SpiHost1FsmCheck_A	0	0	8576729	50	0	0
tb.dut.gen_d0_sys_assert.FpvSecCmD0SysFsmCheck_A	0	0	8576729	50	0	0
tb.dut.gen_d0_usb_aon_assert.FpvSecCmD0UsbAonFsmCheck_A	0	0	8576729	50	0	0
tb.dut.gen_d0_usb_assert.FpvSecCmD0UsbFsmCheck_A	0	0	8576729	50	0	0
tb.dut.gen_daon_lc_aon_assert.FpvSecCmDAonLcAonFsmCheck_A	0	0	8576729	50	0	0
tb.dut.gen_daon_lc_assert.FpvSecCmDAonLcFsmCheck_A	0	0	8576729	50	0	0
tb.dut.gen_daon_lc_io_assert.FpvSecCmDAonLcIoFsmCheck_A	0	0	8576729	50	0	0
tb.dut.gen_daon_lc_io_div2_assert.FpvSecCmDAonLcIoDiv2FsmCheck_A	0	0	8576729	50	0	0
tb.dut.gen_daon_lc_shadowed_assert.FpvSecCmDAonLcShadowedFsmCheck_A	0	0	8576729	50	0	0
tb.dut.gen_daon_lc_usb_assert.FpvSecCmDAonLcUsbFsmCheck_A	0	0	8576729	50	0	0
tb.dut.gen_daon_por_assert.FpvSecCmDAonPorFsmCheck_A	0	0	8576729	50	0	0
tb.dut.gen_daon_por_io_assert.FpvSecCmDAonPorIoFsmCheck_A	0	0	8576729	50	0	0
tb.dut.gen_daon_por_io_div2_assert.FpvSecCmDAonPorIoDiv2FsmCheck_A	0	0	8576729	50	0	0
tb.dut.gen_daon_por_io_div4_assert.FpvSecCmDAonPorIoDiv4FsmCheck_A	0	0	8576729	50	0	0
tb.dut.gen_daon_por_usb_assert.FpvSecCmDAonPorUsbFsmCheck_A	0	0	8576729	50	0	0
tb.dut.gen_daon_sys_io_div4_assert.FpvSecCmDAonSysIoDiv4FsmCheck_A	0	0	8576729	50	0	0
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_prim_mubi4_sender.OutputsKnown_A	0	0	1223397	744228	0	0
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic.selKnown0	0	0	6925	6518	0	0
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic.selKnown1	0	0	2014	1607	0	0
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic.selKnown0	0	0	6490	6083	0	0
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic.selKnown1	0	0	2014	1607	0	0
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic.selKnown0	0	0	5362	4955	0	0
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic.selKnown1	0	0	2014	1607	0	0
tb.dut.gen_rst_por_aon[0].u_por_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	407	407	0	0
tb.dut.gen_rst_por_aon[0].u_por_scanmode_sync.OutputsKnown_A	0	0	8576729	4992085	0	0
tb.dut.gen_rst_por_aon[0].u_por_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	8576729	4992085	0	0
tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic.selKnown0	0	0	6490	6083	0	0
tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic.selKnown1	0	0	2014	1607	0	0
tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_prim_mubi4_sender.OutputsKnown_A	0	0	1223397	730573	0	0
tb.dut.gen_rst_por_aon[1].u_por_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	407	407	0	0
tb.dut.gen_rst_por_aon[1].u_por_scanmode_sync.OutputsKnown_A	0	0	8576729	4992085	0	0
tb.dut.gen_rst_por_aon[1].u_por_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	8576729	4992085	0	0
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[0].LcHandshakeOff_A	0	0	8576729	10131	0	0
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[0].LcHandshakeOn_A	0	0	8576729	93427	0	0
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[0].SysHandshakeOff_A	0	0	8576729	5022291	0	0
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[0].SysHandshakeOn_A	0	0	8576729	149038	0	0
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[1].LcHandshakeOff_A	0	0	8576729	10131	0	0
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[1].LcHandshakeOn_A	0	0	8576729	93427	0	0
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[1].SysHandshakeOff_A	0	0	8576729	5022291	0	0
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[1].SysHandshakeOn_A	0	0	8576729	149038	0	0
tb.dut.rstmgr_attrs_sva_if.AlertInfoAttr_A	0	0	407	407	0	0
tb.dut.rstmgr_attrs_sva_if.CpuInfoAttr_A	0	0	407	407	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorAboveFall_A	0	0	40371236	6490	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorAboveRise_A	0	0	40371236	6490	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoAboveFall_A	0	0	38754767	6490	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoAboveRise_A	0	0	38754767	6490	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoDiv2AboveFall_A	0	0	19377970	6490	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoDiv2AboveRise_A	0	0	19377970	6490	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoDiv4AboveFall_A	0	0	9688787	6490	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoDiv4AboveRise_A	0	0	9688787	6490	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorUcbAboveFall_A	0	0	19377952	6490	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorUcbAboveRise_A	0	0	19377952	6490	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcAboveFall_A	0	0	40371236	16621	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcAboveRise_A	0	0	40371236	16621	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcAonAboveFall_A	0	0	1223397	16621	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcAonAboveRise_A	0	0	1223397	16621	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcShadowedAboveFall_A	0	0	40371236	16621	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcShadowedAboveRise_A	0	0	40371236	16621	0	0
tb.dut.rstmgr_cascading_sva_if.CascadePorToAonAboveFall_A	0	0	1223397	5367	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeSysToSysAboveFall_A	0	0	40371236	16621	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeSysToSysAboveRise_A	0	0	40371236	16621	0	0
tb.dut.rstmgr_cascading_sva_if.ScanRstToAonRise_A	0	0	1223397	155	0	0
tb.dut.rstmgr_cascading_sva_if.StablePorToAonRise_A	0	0	1223397	6490	0	0
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].CascadeLcToSysAboveFall_A	0	0	8576729	16621	0	0
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].CascadeLcToSysAboveRise_A	0	0	8576729	16621	0	0
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].CascadeLocalRstToLcAboveFall_A	0	0	8576729	16621	0	0
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].CascadeLocalRstToLcAboveRise_A	0	0	8576729	16621	0	0
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	0	0	9688787	16621	0	0
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	0	0	9688787	16621	0	0
tb.dut.rstmgr_cascading_sva_if.g_power_domains[1].CascadeLcToSysAboveFall_A	0	0	8576729	16621	0	0
tb.dut.rstmgr_cascading_sva_if.g_power_domains[1].CascadeLcToSysAboveRise_A	0	0	8576729	16621	0	0
tb.dut.rstmgr_cascading_sva_if.g_power_domains[1].CascadeLocalRstToLcAboveFall_A	0	0	8576729	16621	0	0
tb.dut.rstmgr_cascading_sva_if.g_power_domains[1].CascadeLocalRstToLcAboveRise_A	0	0	8576729	16621	0	0
tb.dut.rstmgr_csr_assert.TlulOOBAddrErr_A	0	0	9345780	8131	0	0
tb.dut.rstmgr_csr_assert.alert_regwen_rd_A	0	0	9345780	5484	0	0
tb.dut.rstmgr_csr_assert.cpu_regwen_rd_A	0	0	9345780	5532	0	0
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_0_rd_A	0	0	9345780	8252	0	0
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_1_rd_A	0	0	9345780	8348	0	0
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_2_rd_A	0	0	9345780	8185	0	0
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_3_rd_A	0	0	9345780	8101	0	0
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_4_rd_A	0	0	9345780	8075	0	0
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_5_rd_A	0	0	9345780	8315	0	0
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_6_rd_A	0	0	9345780	7877	0	0
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_7_rd_A	0	0	9345780	8190	0	0
tb.dut.rstmgr_csr_assert.sw_rst_regwen_0_rd_A	0	0	9345780	5739	0	0
tb.dut.rstmgr_csr_assert.sw_rst_regwen_1_rd_A	0	0	9345780	5904	0	0
tb.dut.rstmgr_csr_assert.sw_rst_regwen_2_rd_A	0	0	9345780	5637	0	0
tb.dut.rstmgr_csr_assert.sw_rst_regwen_3_rd_A	0	0	9345780	5923	0	0
tb.dut.rstmgr_csr_assert.sw_rst_regwen_4_rd_A	0	0	9345780	5651	0	0
tb.dut.rstmgr_csr_assert.sw_rst_regwen_5_rd_A	0	0	9345780	5888	0	0
tb.dut.rstmgr_csr_assert.sw_rst_regwen_6_rd_A	0	0	9345780	6115	0	0
tb.dut.rstmgr_csr_assert.sw_rst_regwen_7_rd_A	0	0	9345780	5753	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c0EnTracksRstI2c0Active_A	0	0	9688787	10984	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c0EnTracksRstI2c0Inactive_A	0	0	9688787	17388	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c1EnTracksRstI2c1Active_A	0	0	9688787	11057	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c1EnTracksRstI2c1Inactive_A	0	0	9688787	17458	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c2EnTracksRstI2c2Active_A	0	0	9688787	11074	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c2EnTracksRstI2c2Inactive_A	0	0	9688787	17475	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoDiv2EnTracksRstLcIoDiv2Active_A	0	0	19377970	10197	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoDiv2EnTracksRstLcIoDiv2Inactive_A	0	0	19377970	16621	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoDiv4ShadowedEnTracksRstLcIoDiv4ShadowedActive_A	0	0	9688787	10211	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoDiv4ShadowedEnTracksRstLcIoDiv4ShadowedInactive_A	0	0	9688787	16659	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoEnTracksRstLcIoActive_A	0	0	38754767	10193	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoEnTracksRstLcIoInactive_A	0	0	38754767	16621	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcShadowedEnTracksRstLcShadowedActive_A	0	0	40371236	10173	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcShadowedEnTracksRstLcShadowedInactive_A	0	0	40371236	16621	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcUsbEnTracksRstLcUsbActive_A	0	0	19377952	10193	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcUsbEnTracksRstLcUsbInactive_A	0	0	19377952	16621	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstPorAonEnTracksRstPorAonActive_A	0	0	1223397	42	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstPorAonEnTracksRstPorAonInactive_A	0	0	1223397	6473	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiDeviceEnTracksRstSpiDeviceActive_A	0	0	9688787	10820	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiDeviceEnTracksRstSpiDeviceInactive_A	0	0	9688787	17219	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiHost0EnTracksRstSpiHost0Active_A	0	0	38754767	10844	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiHost0EnTracksRstSpiHost0Inactive_A	0	0	38754767	17255	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiHost1EnTracksRstSpiHost1Active_A	0	0	19377970	10872	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiHost1EnTracksRstSpiHost1Inactive_A	0	0	19377970	17276	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSysEnTracksRstSysActive_A	0	0	40371236	10194	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSysEnTracksRstSysInactive_A	0	0	40371236	16621	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstUsbAonEnTracksRstUsbAonActive_A	0	0	1223397	10415	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstUsbAonEnTracksRstUsbAonInactive_A	0	0	1223397	16509	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstUsbEnTracksRstUsbActive_A	0	0	19377952	10943	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstUsbEnTracksRstUsbInactive_A	0	0	19377952	17344	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcAonEnTracksRstLcAonActive_A	0	0	1223397	10147	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcAonEnTracksRstLcAonInactive_A	0	0	1223397	16604	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoDiv2EnTracksRstLcIoDiv2Active_A	0	0	19377970	10157	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoDiv2EnTracksRstLcIoDiv2Inactive_A	0	0	19377970	16621	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoDiv4ShadowedEnTracksRstLcIoDiv4ShadowedActive_A	0	0	9688787	10169	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoDiv4ShadowedEnTracksRstLcIoDiv4ShadowedInactive_A	0	0	9688787	16659	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoEnTracksRstLcIoActive_A	0	0	38754767	10151	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoEnTracksRstLcIoInactive_A	0	0	38754767	16621	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcShadowedEnTracksRstLcShadowedActive_A	0	0	40371236	10191	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcShadowedEnTracksRstLcShadowedInactive_A	0	0	40371236	16659	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcUsbEnTracksRstLcUsbActive_A	0	0	19377952	10148	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcUsbEnTracksRstLcUsbInactive_A	0	0	19377952	16621	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorAonEnTracksRstPorAonInactive_A	0	0	1223397	6490	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorEnTracksRstPorActive_A	0	0	40371236	21	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoDiv2EnTracksRstPorIoDiv2Active_A	0	0	19377970	25	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoDiv2EnTracksRstPorIoDiv2Inactive_A	0	0	19377970	1550	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoDiv4EnTracksRstPorIoDiv4Inactive_A	0	0	9688787	6490	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoEnTracksRstPorIoActive_A	0	0	38754767	25	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorUsbEnTracksRstPorUsbActive_A	0	0	19377952	21	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorUsbEnTracksRstPorUsbInactive_A	0	0	19377952	1550	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstSysIoDiv4EnTracksRstSysIoDiv4Active_A	0	0	9688787	10149	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstSysIoDiv4EnTracksRstSysIoDiv4Inactive_A	0	0	9688787	16621	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[0].RstEnOff_A	0	0	9688787	10729	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[0].RstEnOn_A	0	0	9688787	751	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[0].RstNOff_A	0	0	9688787	10729	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[0].RstNOn_A	0	0	9688787	751	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[1].RstEnOff_A	0	0	38754767	9758	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[1].RstEnOn_A	0	0	38754767	709	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[1].RstNOff_A	0	0	38754767	9758	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[1].RstNOn_A	0	0	38754767	709	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[2].RstEnOff_A	0	0	19377970	9778	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[2].RstEnOn_A	0	0	19377970	686	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[2].RstNOff_A	0	0	19377970	9778	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[2].RstNOn_A	0	0	19377970	686	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[3].RstEnOff_A	0	0	19377952	9845	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[3].RstEnOn_A	0	0	19377952	748	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[3].RstNOff_A	0	0	19377952	9845	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[3].RstNOn_A	0	0	19377952	748	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[4].RstEnOff_A	0	0	1223397	16152	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[4].RstEnOn_A	0	0	1223397	775	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[4].RstNOff_A	0	0	1223397	16152	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[4].RstNOn_A	0	0	1223397	775	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[5].RstEnOff_A	0	0	9688787	10898	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[5].RstEnOn_A	0	0	9688787	791	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[5].RstNOff_A	0	0	9688787	10898	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[5].RstNOn_A	0	0	9688787	791	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[6].RstEnOff_A	0	0	9688787	10968	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[6].RstEnOn_A	0	0	9688787	867	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[6].RstNOff_A	0	0	9688787	10968	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[6].RstNOn_A	0	0	9688787	867	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[7].RstEnOff_A	0	0	9688787	10984	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[7].RstEnOn_A	0	0	9688787	878	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[7].RstNOff_A	0	0	9688787	10984	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[7].RstNOn_A	0	0	9688787	878	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	9345780	880303	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	9345780	5487938	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	9345780	5487938	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	9345780	1620424	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	9345780	5487938	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	9345780	5487938	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[119].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[11].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[120].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[121].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[122].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[123].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[124].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[125].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[126].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[127].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[128].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[129].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[12].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[130].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[131].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[132].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[133].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[134].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[135].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[136].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[137].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[138].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[139].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[13].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[140].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[141].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[142].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[143].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[144].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[145].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[146].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[147].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[148].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[149].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[14].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[150].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[151].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[152].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[153].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[154].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[155].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[156].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[157].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[158].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[159].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[15].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[160].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[161].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[162].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[163].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[164].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[165].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[166].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[167].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[168].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[169].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[16].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[170].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[171].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[172].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[173].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[174].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[175].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[176].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[177].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[178].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[179].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[17].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[180].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[181].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
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tb.dut.tlul_assert_device.gen_assert_final[184].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
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tb.dut.tlul_assert_device.gen_assert_final[189].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
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tb.dut.tlul_assert_device.gen_assert_final[192].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
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tb.dut.tlul_assert_device.gen_assert_final[197].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
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tb.dut.tlul_assert_device.gen_assert_final[200].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[201].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
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tb.dut.tlul_assert_device.gen_assert_final[206].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[207].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
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tb.dut.tlul_assert_device.gen_assert_final[210].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
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tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
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tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
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tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A	0	0	521	521	0	0
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tb.dut.tlul_assert_device.gen_device.aDataKnown_M	0	0	9346301	391673	0	0
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A	0	0	9345780	5540	0	0
tb.dut.tlul_assert_device.gen_device.contigMask_M	0	0	9346301	636165	0	0
tb.dut.tlul_assert_device.gen_device.dDataKnown_A	0	0	9346301	833291	0	0
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A	0	0	9345780	5975	0	0
tb.dut.tlul_assert_device.gen_device.legalAParam_M	0	0	9346301	880429	0	0
tb.dut.tlul_assert_device.gen_device.legalDParam_A	0	0	9346301	1620581	0	0
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M	0	0	9346301	880429	0	0
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A	0	0	9346301	1620581	0	0
tb.dut.tlul_assert_device.gen_device.respOpcode_A	0	0	9346301	1620581	0	0
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A	0	0	9346301	1620581	0	0
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A	0	0	9345780	3302	0	0
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A	0	0	9345780	2825	0	0
tb.dut.tlul_assert_device.p_dbw.TlDbw_A	0	0	521	521	0	0
tb.dut.u_alert_info.CntStoreSlot_A	0	0	407	407	0	0
tb.dut.u_alert_info.CntWidth_A	0	0	407	407	0	0
tb.dut.u_cpu_info.CntStoreSlot_A	0	0	407	407	0	0
tb.dut.u_cpu_info.CntWidth_A	0	0	407	407	0	0
tb.dut.u_ctrl_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	407	407	0	0
tb.dut.u_ctrl_scanmode_sync.OutputsKnown_A	0	0	9688787	5835541	0	0
tb.dut.u_ctrl_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	9688787	5835541	0	0
tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	16659	16252	0	0
tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2014	1607	0	0
tb.dut.u_d0_i2c0.u_prim_mubi4_sender.OutputsKnown_A	0	0	9688787	4932001	0	0
tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	17388	16981	0	0
tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2014	1607	0	0
tb.dut.u_d0_i2c0.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	407	407	0	0
tb.dut.u_d0_i2c0.u_scanmode_sync.OutputsKnown_A	0	0	8576729	4992085	0	0
tb.dut.u_d0_i2c0.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	8576729	4992085	0	0
tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	16659	16252	0	0
tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2014	1607	0	0
tb.dut.u_d0_i2c1.u_prim_mubi4_sender.OutputsKnown_A	0	0	9688787	4921681	0	0
tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	17458	17051	0	0
tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2014	1607	0	0
tb.dut.u_d0_i2c1.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	407	407	0	0
tb.dut.u_d0_i2c1.u_scanmode_sync.OutputsKnown_A	0	0	8576729	4992085	0	0
tb.dut.u_d0_i2c1.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	8576729	4992085	0	0
tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	16659	16252	0	0
tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2014	1607	0	0
tb.dut.u_d0_i2c2.u_prim_mubi4_sender.OutputsKnown_A	0	0	9688787	4930009	0	0
tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	17474	17067	0	0
tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2014	1607	0	0
tb.dut.u_d0_i2c2.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	407	407	0	0
tb.dut.u_d0_i2c2.u_scanmode_sync.OutputsKnown_A	0	0	8576729	4992085	0	0
tb.dut.u_d0_i2c2.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	8576729	4992085	0	0
tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	16659	16252	0	0
tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2014	1607	0	0
tb.dut.u_d0_lc.u_prim_mubi4_sender.OutputsKnown_A	0	0	40371236	21007854	0	0
tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	16621	16214	0	0
tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2014	1607	0	0
tb.dut.u_d0_lc.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	407	407	0	0
tb.dut.u_d0_lc.u_scanmode_sync.OutputsKnown_A	0	0	8576729	4992085	0	0
tb.dut.u_d0_lc.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	8576729	4992085	0	0
tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	16659	16252	0	0
tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2014	1607	0	0
tb.dut.u_d0_lc_io.u_prim_mubi4_sender.OutputsKnown_A	0	0	38754767	20166370	0	0
tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	16621	16214	0	0
tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2014	1607	0	0
tb.dut.u_d0_lc_io.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	407	407	0	0
tb.dut.u_d0_lc_io.u_scanmode_sync.OutputsKnown_A	0	0	8576729	4992085	0	0
tb.dut.u_d0_lc_io.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	8576729	4992085	0	0
tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	16659	16252	0	0
tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2014	1607	0	0
tb.dut.u_d0_lc_io_div2.u_prim_mubi4_sender.OutputsKnown_A	0	0	19377970	10075552	0	0
tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	16621	16214	0	0
tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2014	1607	0	0
tb.dut.u_d0_lc_io_div2.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	407	407	0	0
tb.dut.u_d0_lc_io_div2.u_scanmode_sync.OutputsKnown_A	0	0	8576729	4992085	0	0
tb.dut.u_d0_lc_io_div2.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	8576729	4992085	0	0
tb.dut.u_d0_lc_io_div4.u_prim_mubi4_sender.OutputsKnown_A	0	0	9688787	5016816	0	0
tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	16621	16214	0	0
tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2014	1607	0	0
tb.dut.u_d0_lc_io_div4.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	407	407	0	0
tb.dut.u_d0_lc_io_div4.u_scanmode_sync.OutputsKnown_A	0	0	8576729	4992085	0	0
tb.dut.u_d0_lc_io_div4.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	8576729	4992085	0	0
tb.dut.u_d0_lc_io_div4_shadowed.u_prim_mubi4_sender.OutputsKnown_A	0	0	9688787	5016816	0	0
tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	16621	16214	0	0
tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2014	1607	0	0
tb.dut.u_d0_lc_io_div4_shadowed.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	407	407	0	0
tb.dut.u_d0_lc_io_div4_shadowed.u_scanmode_sync.OutputsKnown_A	0	0	8576729	4992085	0	0
tb.dut.u_d0_lc_io_div4_shadowed.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	8576729	4992085	0	0
tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	16659	16252	0	0
tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2014	1607	0	0
tb.dut.u_d0_lc_shadowed.u_prim_mubi4_sender.OutputsKnown_A	0	0	40371236	21009397	0	0
tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	16621	16214	0	0
tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2014	1607	0	0
tb.dut.u_d0_lc_shadowed.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	407	407	0	0
tb.dut.u_d0_lc_shadowed.u_scanmode_sync.OutputsKnown_A	0	0	8576729	4992085	0	0
tb.dut.u_d0_lc_shadowed.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	8576729	4992085	0	0
tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	16659	16252	0	0
tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2014	1607	0	0
tb.dut.u_d0_lc_usb.u_prim_mubi4_sender.OutputsKnown_A	0	0	19377952	10075491	0	0
tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	16621	16214	0	0
tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2014	1607	0	0
tb.dut.u_d0_lc_usb.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	407	407	0	0
tb.dut.u_d0_lc_usb.u_scanmode_sync.OutputsKnown_A	0	0	8576729	4992085	0	0
tb.dut.u_d0_lc_usb.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	8576729	4992085	0	0
tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	16659	16252	0	0
tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2014	1607	0	0
tb.dut.u_d0_spi_device.u_prim_mubi4_sender.OutputsKnown_A	0	0	9688787	4927172	0	0
tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	17219	16812	0	0
tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2014	1607	0	0
tb.dut.u_d0_spi_device.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	407	407	0	0
tb.dut.u_d0_spi_device.u_scanmode_sync.OutputsKnown_A	0	0	8576729	4992085	0	0
tb.dut.u_d0_spi_device.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	8576729	4992085	0	0
tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	16659	16252	0	0
tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2014	1607	0	0
tb.dut.u_d0_spi_host0.u_prim_mubi4_sender.OutputsKnown_A	0	0	38754767	19819654	0	0
tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	17255	16848	0	0
tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2014	1607	0	0
tb.dut.u_d0_spi_host0.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	407	407	0	0
tb.dut.u_d0_spi_host0.u_scanmode_sync.OutputsKnown_A	0	0	8576729	4992085	0	0
tb.dut.u_d0_spi_host0.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	8576729	4992085	0	0
tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	16659	16252	0	0
tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2014	1607	0	0
tb.dut.u_d0_spi_host1.u_prim_mubi4_sender.OutputsKnown_A	0	0	19377970	9896648	0	0
tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	17275	16868	0	0
tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2014	1607	0	0
tb.dut.u_d0_spi_host1.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	407	407	0	0
tb.dut.u_d0_spi_host1.u_scanmode_sync.OutputsKnown_A	0	0	8576729	4992085	0	0
tb.dut.u_d0_spi_host1.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	8576729	4992085	0	0
tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	16659	16252	0	0
tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2014	1607	0	0
tb.dut.u_d0_sys.u_prim_mubi4_sender.OutputsKnown_A	0	0	40371236	20776548	0	0
tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	16621	16214	0	0
tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2014	1607	0	0
tb.dut.u_d0_sys.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	407	407	0	0
tb.dut.u_d0_sys.u_scanmode_sync.OutputsKnown_A	0	0	8576729	4992085	0	0
tb.dut.u_d0_sys.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	8576729	4992085	0	0
tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	16659	16252	0	0
tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2014	1607	0	0
tb.dut.u_d0_usb.u_prim_mubi4_sender.OutputsKnown_A	0	0	19377952	9882946	0	0
tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	17342	16935	0	0
tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2014	1607	0	0
tb.dut.u_d0_usb.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	407	407	0	0
tb.dut.u_d0_usb.u_scanmode_sync.OutputsKnown_A	0	0	8576729	4992085	0	0
tb.dut.u_d0_usb.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	8576729	4992085	0	0
tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	16566	16159	0	0
tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2014	1607	0	0
tb.dut.u_d0_usb_aon.u_prim_mubi4_sender.OutputsKnown_A	0	0	1223397	610807	0	0
tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	17347	16940	0	0
tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2014	1607	0	0
tb.dut.u_d0_usb_aon.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	407	407	0	0
tb.dut.u_d0_usb_aon.u_scanmode_sync.OutputsKnown_A	0	0	8576729	4992085	0	0
tb.dut.u_d0_usb_aon.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	8576729	4992085	0	0
tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	16659	16252	0	0
tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2014	1607	0	0
tb.dut.u_daon_lc.u_prim_mubi4_sender.OutputsKnown_A	0	0	40371236	21546448	0	0
tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	16621	16214	0	0
tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2014	1607	0	0
tb.dut.u_daon_lc.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	407	407	0	0
tb.dut.u_daon_lc.u_scanmode_sync.OutputsKnown_A	0	0	8576729	4992085	0	0
tb.dut.u_daon_lc.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	8576729	4992085	0	0
tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	16566	16159	0	0
tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2014	1607	0	0
tb.dut.u_daon_lc_aon.u_prim_mubi4_sender.OutputsKnown_A	0	0	1223397	639077	0	0
tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	16621	16214	0	0
tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2014	1607	0	0
tb.dut.u_daon_lc_aon.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	407	407	0	0
tb.dut.u_daon_lc_aon.u_scanmode_sync.OutputsKnown_A	0	0	8576729	4992085	0	0
tb.dut.u_daon_lc_aon.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	8576729	4992085	0	0
tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	16659	16252	0	0
tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2014	1607	0	0
tb.dut.u_daon_lc_io.u_prim_mubi4_sender.OutputsKnown_A	0	0	38754767	20684512	0	0
tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	16621	16214	0	0
tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2014	1607	0	0
tb.dut.u_daon_lc_io.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	407	407	0	0
tb.dut.u_daon_lc_io.u_scanmode_sync.OutputsKnown_A	0	0	8576729	4992085	0	0
tb.dut.u_daon_lc_io.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	8576729	4992085	0	0
tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	16659	16252	0	0
tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2014	1607	0	0
tb.dut.u_daon_lc_io_div2.u_prim_mubi4_sender.OutputsKnown_A	0	0	19377970	10334471	0	0
tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	16621	16214	0	0
tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2014	1607	0	0
tb.dut.u_daon_lc_io_div2.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	407	407	0	0
tb.dut.u_daon_lc_io_div2.u_scanmode_sync.OutputsKnown_A	0	0	8576729	4992085	0	0
tb.dut.u_daon_lc_io_div2.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	8576729	4992085	0	0
tb.dut.u_daon_lc_io_div4.u_prim_mubi4_sender.OutputsKnown_A	0	0	9688787	5146316	0	0
tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	16621	16214	0	0
tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2014	1607	0	0
tb.dut.u_daon_lc_io_div4.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	407	407	0	0
tb.dut.u_daon_lc_io_div4.u_scanmode_sync.OutputsKnown_A	0	0	8576729	4992085	0	0
tb.dut.u_daon_lc_io_div4.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	8576729	4992085	0	0
tb.dut.u_daon_lc_io_div4_shadowed.u_prim_mubi4_sender.OutputsKnown_A	0	0	9688787	5146316	0	0
tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	16621	16214	0	0
tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2014	1607	0	0
tb.dut.u_daon_lc_io_div4_shadowed.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	407	407	0	0
tb.dut.u_daon_lc_io_div4_shadowed.u_scanmode_sync.OutputsKnown_A	0	0	8576729	4992085	0	0
tb.dut.u_daon_lc_io_div4_shadowed.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	8576729	4992085	0	0
tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	16659	16252	0	0
tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2014	1607	0	0
tb.dut.u_daon_lc_shadowed.u_prim_mubi4_sender.OutputsKnown_A	0	0	40371236	21546219	0	0
tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	16621	16214	0	0
tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2014	1607	0	0
tb.dut.u_daon_lc_shadowed.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	407	407	0	0
tb.dut.u_daon_lc_shadowed.u_scanmode_sync.OutputsKnown_A	0	0	8576729	4992085	0	0
tb.dut.u_daon_lc_shadowed.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	8576729	4992085	0	0
tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	16659	16252	0	0
tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2014	1607	0	0
tb.dut.u_daon_lc_usb.u_prim_mubi4_sender.OutputsKnown_A	0	0	19377952	10334606	0	0
tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	16621	16214	0	0
tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2014	1607	0	0
tb.dut.u_daon_lc_usb.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	407	407	0	0
tb.dut.u_daon_lc_usb.u_scanmode_sync.OutputsKnown_A	0	0	8576729	4992085	0	0
tb.dut.u_daon_lc_usb.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	8576729	4992085	0	0
tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	16659	16252	0	0
tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2014	1607	0	0
tb.dut.u_daon_por.u_prim_mubi4_sender.OutputsKnown_A	0	0	40371236	24331284	0	0
tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	6490	6083	0	0
tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2014	1607	0	0
tb.dut.u_daon_por.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	407	407	0	0
tb.dut.u_daon_por.u_scanmode_sync.OutputsKnown_A	0	0	8576729	4992085	0	0
tb.dut.u_daon_por.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	8576729	4992085	0	0
tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	16659	16252	0	0
tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2014	1607	0	0
tb.dut.u_daon_por_io.u_prim_mubi4_sender.OutputsKnown_A	0	0	38754767	23356718	0	0
tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	6490	6083	0	0
tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2014	1607	0	0
tb.dut.u_daon_por_io.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	407	407	0	0
tb.dut.u_daon_por_io.u_scanmode_sync.OutputsKnown_A	0	0	8576729	4992085	0	0
tb.dut.u_daon_por_io.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	8576729	4992085	0	0
tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	16659	16252	0	0
tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2014	1607	0	0
tb.dut.u_daon_por_io_div2.u_prim_mubi4_sender.OutputsKnown_A	0	0	19377970	11675736	0	0
tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	6490	6083	0	0
tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2014	1607	0	0
tb.dut.u_daon_por_io_div2.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	407	407	0	0
tb.dut.u_daon_por_io_div2.u_scanmode_sync.OutputsKnown_A	0	0	8576729	4992085	0	0
tb.dut.u_daon_por_io_div2.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	8576729	4992085	0	0
tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	16659	16252	0	0
tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2014	1607	0	0
tb.dut.u_daon_por_io_div4.u_prim_mubi4_sender.OutputsKnown_A	0	0	9688787	5835541	0	0
tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	6490	6083	0	0
tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2014	1607	0	0
tb.dut.u_daon_por_io_div4.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	407	407	0	0
tb.dut.u_daon_por_io_div4.u_scanmode_sync.OutputsKnown_A	0	0	8576729	4992085	0	0
tb.dut.u_daon_por_io_div4.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	8576729	4992085	0	0
tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	16659	16252	0	0
tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2014	1607	0	0
tb.dut.u_daon_por_usb.u_prim_mubi4_sender.OutputsKnown_A	0	0	19377952	11675749	0	0
tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	6490	6083	0	0
tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2014	1607	0	0
tb.dut.u_daon_por_usb.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	407	407	0	0
tb.dut.u_daon_por_usb.u_scanmode_sync.OutputsKnown_A	0	0	8576729	4992085	0	0
tb.dut.u_daon_por_usb.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	8576729	4992085	0	0
tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	16659	16252	0	0
tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2014	1607	0	0
tb.dut.u_daon_sys_io_div4.u_prim_mubi4_sender.OutputsKnown_A	0	0	9688787	5090836	0	0
tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	16621	16214	0	0
tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2014	1607	0	0
tb.dut.u_daon_sys_io_div4.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	407	407	0	0
tb.dut.u_daon_sys_io_div4.u_scanmode_sync.OutputsKnown_A	0	0	8576729	4992085	0	0
tb.dut.u_daon_sys_io_div4.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	8576729	4992085	0	0
tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic.selKnown0	0	0	16621	16214	0	0
tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic.selKnown1	0	0	2014	1607	0	0
tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic.selKnown0	0	0	16621	16214	0	0
tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic.selKnown1	0	0	2014	1607	0	0
tb.dut.u_reg.en2addrHit	0	0	9345780	747204	0	0
tb.dut.u_reg.reAfterRv	0	0	9345780	747083	0	0
tb.dut.u_reg.rePulse	0	0	9345780	399330	0	0
tb.dut.u_reg.u_chk.PayLoadWidthCheck	0	0	521	521	0	0
tb.dut.u_reg.u_reg_if.AllowedLatency_A	0	0	521	521	0	0
tb.dut.u_reg.u_reg_if.MatchedWidthAssert	0	0	521	521	0	0
tb.dut.u_reg.u_reg_if.u_err.dataWidthOnly32_A	0	0	521	521	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A	0	0	521	521	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck	0	0	521	521	0	0
tb.dut.u_reg.u_rsp_intg_gen.DataWidthCheck_A	0	0	521	521	0	0
tb.dut.u_reg.u_rsp_intg_gen.PayLoadWidthCheck	0	0	521	521	0	0
tb.dut.u_reg.wePulse	0	0	9345780	347753	0	0
tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic.selKnown0	0	0	16621	16214	0	0
tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic.selKnown1	0	0	2014	1607	0	0
tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic.selKnown0	0	0	16621	16214	0	0
tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic.selKnown1	0	0	2014	1607	0	0

---

Detail Report for Cover Sequences

Cover Sequences All Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	9346301	4966	4966	0
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	9346301	2098	2098	1
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	9346301	2105	2105	1
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	9346301	1470	1470	1
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	9346301	98	98	1
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	9346301	1164	1164	1
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	9346301	961	961	1
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	9346301	3833	3833	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	9346301	37289	37289	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	9346301	366880	366880	377

Cover Sequences First Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	9346301	4966	4966	0
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	9346301	2098	2098	1
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	9346301	2105	2105	1
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	9346301	1470	1470	1
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	9346301	98	98	1
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	9346301	1164	1164	1
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	9346301	961	961	1
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	9346301	3833	3833	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	9346301	37289	37289	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	9346301	366880	366880	377