Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::reset_stretcher_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::reset_stretcher_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

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Summary for Group rstmgr_env_pkg::rstmgr_env_cov::reset_stretcher_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::reset_stretcher_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
count_cp	4	0	4	100.00	100	1	1	0
length_cp	8	0	8	100.00	100	1	1	0

Summary for Variable count_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for count_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6826	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
cb[0]	1075	1			T1	3		T2	3		T3	1
cb[1]	965	1			T1	4		T2	4		T4	4
cb[2]	911	1			T1	4		T2	4		T4	4
cb[3]	862	1			T1	4		T2	4		T4	4

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Summary for Variable length_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for length_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8554	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lb[0]	322	1			T1	2		T2	2		T4	3
lb[1]	263	1			T4	1		T74	1		T94	1
lb[2]	280	1			T4	1		T66	1		T68	1
lb[3]	244	1			T74	1		T94	1		T117	1
lb[4]	246	1			T4	2		T74	1		T117	2
lb[5]	279	1			T4	3		T66	1		T68	2
lb[6]	272	1			T4	3		T74	2		T131	1
lb[7]	179	1			T4	2		T68	1		T120	1