Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6167 |
1 |
|
|
T4 |
201 |
|
T66 |
3 |
|
T68 |
3 |
auto[1] |
8724 |
1 |
|
|
T3 |
4 |
|
T4 |
192 |
|
T6 |
4 |
Summary for Variable reset_info_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for reset_info_cp
Excluded/Illegal bins
NAME | COUNT | STATUS |
others |
4579 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
reset_info_cp[1] |
5063 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
2 |
reset_info_cp[2] |
2321 |
1 |
|
|
T3 |
1 |
|
T4 |
63 |
|
T6 |
1 |
reset_info_cp[4] |
2964 |
1 |
|
|
T3 |
1 |
|
T4 |
110 |
|
T6 |
1 |
reset_info_cp[8] |
78 |
1 |
|
|
T4 |
1 |
|
T29 |
1 |
|
T32 |
2 |
reset_info_cp[16] |
97 |
1 |
|
|
T4 |
4 |
|
T14 |
1 |
|
T27 |
1 |
reset_info_cp[32] |
94 |
1 |
|
|
T4 |
1 |
|
T29 |
2 |
|
T130 |
1 |
reset_info_cp[64] |
116 |
1 |
|
|
T4 |
4 |
|
T29 |
1 |
|
T41 |
1 |
reset_info_cp[128] |
100 |
1 |
|
|
T4 |
2 |
|
T11 |
1 |
|
T14 |
1 |
Summary for Cross capture_cross
Samples crossed: reset_info_cp enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
16 |
0 |
16 |
100.00 |
|
Automatically Generated Cross Bins for capture_cross
Bins
reset_info_cp | enable_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
reset_info_cp[1] |
auto[0] |
2406 |
1 |
|
|
T4 |
49 |
|
T66 |
3 |
|
T68 |
3 |
reset_info_cp[1] |
auto[1] |
2136 |
1 |
|
|
T3 |
1 |
|
T4 |
59 |
|
T6 |
1 |
reset_info_cp[2] |
auto[0] |
703 |
1 |
|
|
T4 |
35 |
|
T11 |
10 |
|
T12 |
2 |
reset_info_cp[2] |
auto[1] |
1618 |
1 |
|
|
T3 |
1 |
|
T4 |
28 |
|
T6 |
1 |
reset_info_cp[4] |
auto[0] |
1055 |
1 |
|
|
T4 |
50 |
|
T11 |
5 |
|
T12 |
5 |
reset_info_cp[4] |
auto[1] |
1909 |
1 |
|
|
T3 |
1 |
|
T4 |
60 |
|
T6 |
1 |
reset_info_cp[8] |
auto[0] |
24 |
1 |
|
|
T29 |
1 |
|
T83 |
1 |
|
T134 |
1 |
reset_info_cp[8] |
auto[1] |
54 |
1 |
|
|
T4 |
1 |
|
T32 |
2 |
|
T53 |
1 |
reset_info_cp[16] |
auto[0] |
35 |
1 |
|
|
T14 |
1 |
|
T41 |
1 |
|
T83 |
1 |
reset_info_cp[16] |
auto[1] |
62 |
1 |
|
|
T4 |
4 |
|
T27 |
1 |
|
T29 |
2 |
reset_info_cp[32] |
auto[0] |
38 |
1 |
|
|
T4 |
1 |
|
T29 |
2 |
|
T135 |
1 |
reset_info_cp[32] |
auto[1] |
56 |
1 |
|
|
T130 |
1 |
|
T53 |
1 |
|
T33 |
2 |
reset_info_cp[64] |
auto[0] |
48 |
1 |
|
|
T4 |
1 |
|
T41 |
1 |
|
T43 |
1 |
reset_info_cp[64] |
auto[1] |
68 |
1 |
|
|
T4 |
3 |
|
T29 |
1 |
|
T32 |
1 |
reset_info_cp[128] |
auto[0] |
47 |
1 |
|
|
T4 |
2 |
|
T14 |
1 |
|
T29 |
1 |
reset_info_cp[128] |
auto[1] |
53 |
1 |
|
|
T11 |
1 |
|
T29 |
1 |
|
T32 |
1 |