Group : rstmgr_env_pkg::rstmgr_sw_rst_cg_wrap::sw_rst_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : rstmgr_env_pkg::rstmgr_sw_rst_cg_wrap::sw_rst_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

8 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
sw_rst_ctrl_n[0] 100.00 1 100 1 64 64
sw_rst_ctrl_n[1] 100.00 1 100 1 64 64
sw_rst_ctrl_n[2] 100.00 1 100 1 64 64
sw_rst_ctrl_n[3] 100.00 1 100 1 64 64
sw_rst_ctrl_n[4] 100.00 1 100 1 64 64
sw_rst_ctrl_n[5] 100.00 1 100 1 64 64
sw_rst_ctrl_n[6] 100.00 1 100 1 64 64
sw_rst_ctrl_n[7] 100.00 1 100 1 64 64




Group Instance : sw_rst_ctrl_n[0]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sw_rst_ctrl_n[0]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 4 0 4 100.00


Variables for Group Instance sw_rst_ctrl_n[0]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
enable 2 0 2 100.00 100 1 1 2
enable_cp 2 0 2 100.00 100 1 1 2
rst_n 2 0 2 100.00 100 1 1 2
rst_n_cp 2 0 2 100.00 100 1 1 2


Crosses for Group Instance sw_rst_ctrl_n[0]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
sw_rst_cross 4 0 4 100.00 100 1 1 0



Group Instance : sw_rst_ctrl_n[1]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sw_rst_ctrl_n[1]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 4 0 4 100.00


Variables for Group Instance sw_rst_ctrl_n[1]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
enable 2 0 2 100.00 100 1 1 2
enable_cp 2 0 2 100.00 100 1 1 2
rst_n 2 0 2 100.00 100 1 1 2
rst_n_cp 2 0 2 100.00 100 1 1 2


Crosses for Group Instance sw_rst_ctrl_n[1]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
sw_rst_cross 4 0 4 100.00 100 1 1 0



Group Instance : sw_rst_ctrl_n[2]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sw_rst_ctrl_n[2]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 4 0 4 100.00


Variables for Group Instance sw_rst_ctrl_n[2]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
enable 2 0 2 100.00 100 1 1 2
enable_cp 2 0 2 100.00 100 1 1 2
rst_n 2 0 2 100.00 100 1 1 2
rst_n_cp 2 0 2 100.00 100 1 1 2


Crosses for Group Instance sw_rst_ctrl_n[2]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
sw_rst_cross 4 0 4 100.00 100 1 1 0



Group Instance : sw_rst_ctrl_n[3]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sw_rst_ctrl_n[3]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 4 0 4 100.00


Variables for Group Instance sw_rst_ctrl_n[3]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
enable 2 0 2 100.00 100 1 1 2
enable_cp 2 0 2 100.00 100 1 1 2
rst_n 2 0 2 100.00 100 1 1 2
rst_n_cp 2 0 2 100.00 100 1 1 2


Crosses for Group Instance sw_rst_ctrl_n[3]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
sw_rst_cross 4 0 4 100.00 100 1 1 0



Group Instance : sw_rst_ctrl_n[4]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sw_rst_ctrl_n[4]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 4 0 4 100.00


Variables for Group Instance sw_rst_ctrl_n[4]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
enable 2 0 2 100.00 100 1 1 2
enable_cp 2 0 2 100.00 100 1 1 2
rst_n 2 0 2 100.00 100 1 1 2
rst_n_cp 2 0 2 100.00 100 1 1 2


Crosses for Group Instance sw_rst_ctrl_n[4]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
sw_rst_cross 4 0 4 100.00 100 1 1 0



Group Instance : sw_rst_ctrl_n[5]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sw_rst_ctrl_n[5]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 4 0 4 100.00


Variables for Group Instance sw_rst_ctrl_n[5]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
enable 2 0 2 100.00 100 1 1 2
enable_cp 2 0 2 100.00 100 1 1 2
rst_n 2 0 2 100.00 100 1 1 2
rst_n_cp 2 0 2 100.00 100 1 1 2


Crosses for Group Instance sw_rst_ctrl_n[5]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
sw_rst_cross 4 0 4 100.00 100 1 1 0



Group Instance : sw_rst_ctrl_n[6]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sw_rst_ctrl_n[6]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 4 0 4 100.00


Variables for Group Instance sw_rst_ctrl_n[6]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
enable 2 0 2 100.00 100 1 1 2
enable_cp 2 0 2 100.00 100 1 1 2
rst_n 2 0 2 100.00 100 1 1 2
rst_n_cp 2 0 2 100.00 100 1 1 2


Crosses for Group Instance sw_rst_ctrl_n[6]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
sw_rst_cross 4 0 4 100.00 100 1 1 0



Group Instance : sw_rst_ctrl_n[7]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sw_rst_ctrl_n[7]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 4 0 4 100.00


Variables for Group Instance sw_rst_ctrl_n[7]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
enable 2 0 2 100.00 100 1 1 2
enable_cp 2 0 2 100.00 100 1 1 2
rst_n 2 0 2 100.00 100 1 1 2
rst_n_cp 2 0 2 100.00 100 1 1 2


Crosses for Group Instance sw_rst_ctrl_n[7]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
sw_rst_cross 4 0 4 100.00 100 1 1 0


Summary for Variable enable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1568 1 T4 32 T8 32 T10 32
auto[1] 3687 1 T2 3 T4 16 T6 3



Summary for Variable enable_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1568 1 T4 32 T8 32 T10 32
auto[1] 3687 1 T2 3 T4 16 T6 3



Summary for Variable rst_n

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for rst_n

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1492 1 T4 13 T6 1 T7 9
auto[1] 3763 1 T2 3 T4 35 T6 2



Summary for Variable rst_n_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for rst_n_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1492 1 T4 13 T6 1 T7 9
auto[1] 3763 1 T2 3 T4 35 T6 2



Summary for Cross sw_rst_cross

Samples crossed: enable rst_n
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for sw_rst_cross

Bins
enablerst_nCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 392 1 T4 8 T8 8 T10 8
auto[0] auto[1] 1176 1 T4 24 T8 24 T10 24
auto[1] auto[0] 1100 1 T4 5 T6 1 T7 9
auto[1] auto[1] 2587 1 T2 3 T4 11 T6 2


Summary for Variable enable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1447 1 T4 28 T8 28 T10 28
auto[1] 3585 1 T2 3 T4 20 T6 3



Summary for Variable enable_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1447 1 T4 28 T8 28 T10 28
auto[1] 3585 1 T2 3 T4 20 T6 3



Summary for Variable rst_n

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for rst_n

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1381 1 T2 1 T4 16 T6 1
auto[1] 3651 1 T2 2 T4 32 T6 2



Summary for Variable rst_n_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for rst_n_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1381 1 T2 1 T4 16 T6 1
auto[1] 3651 1 T2 2 T4 32 T6 2



Summary for Cross sw_rst_cross

Samples crossed: enable rst_n
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for sw_rst_cross

Bins
enablerst_nCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 380 1 T4 7 T8 7 T10 7
auto[0] auto[1] 1067 1 T4 21 T8 21 T10 21
auto[1] auto[0] 1001 1 T2 1 T4 9 T6 1
auto[1] auto[1] 2584 1 T2 2 T4 11 T6 2


Summary for Variable enable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1230 1 T4 24 T8 24 T10 24
auto[1] 3722 1 T2 3 T4 24 T6 3



Summary for Variable enable_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1230 1 T4 24 T8 24 T10 24
auto[1] 3722 1 T2 3 T4 24 T6 3



Summary for Variable rst_n

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for rst_n

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1292 1 T4 14 T6 1 T8 9
auto[1] 3660 1 T2 3 T4 34 T6 2



Summary for Variable rst_n_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for rst_n_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1292 1 T4 14 T6 1 T8 9
auto[1] 3660 1 T2 3 T4 34 T6 2



Summary for Cross sw_rst_cross

Samples crossed: enable rst_n
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for sw_rst_cross

Bins
enablerst_nCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 321 1 T4 6 T8 6 T10 6
auto[0] auto[1] 909 1 T4 18 T8 18 T10 18
auto[1] auto[0] 971 1 T4 8 T6 1 T8 3
auto[1] auto[1] 2751 1 T2 3 T4 16 T6 2


Summary for Variable enable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1049 1 T4 20 T8 20 T10 20
auto[1] 3895 1 T2 3 T4 28 T6 3



Summary for Variable enable_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1049 1 T4 20 T8 20 T10 20
auto[1] 3895 1 T2 3 T4 28 T6 3



Summary for Variable rst_n

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for rst_n

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1349 1 T2 1 T4 14 T6 1
auto[1] 3595 1 T2 2 T4 34 T6 2



Summary for Variable rst_n_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for rst_n_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1349 1 T2 1 T4 14 T6 1
auto[1] 3595 1 T2 2 T4 34 T6 2



Summary for Cross sw_rst_cross

Samples crossed: enable rst_n
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for sw_rst_cross

Bins
enablerst_nCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 273 1 T4 5 T8 5 T10 5
auto[0] auto[1] 776 1 T4 15 T8 15 T10 15
auto[1] auto[0] 1076 1 T2 1 T4 9 T6 1
auto[1] auto[1] 2819 1 T2 2 T4 19 T6 2


Summary for Variable enable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 847 1 T2 3 T4 16 T8 16
auto[1] 4097 1 T4 32 T6 3 T7 15



Summary for Variable enable_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 847 1 T2 3 T4 16 T8 16
auto[1] 4097 1 T4 32 T6 3 T7 15



Summary for Variable rst_n

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for rst_n

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1390 1 T2 1 T4 13 T6 1
auto[1] 3554 1 T2 2 T4 35 T6 2



Summary for Variable rst_n_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for rst_n_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1390 1 T2 1 T4 13 T6 1
auto[1] 3554 1 T2 2 T4 35 T6 2



Summary for Cross sw_rst_cross

Samples crossed: enable rst_n
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for sw_rst_cross

Bins
enablerst_nCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 227 1 T2 1 T4 4 T8 4
auto[0] auto[1] 620 1 T2 2 T4 12 T8 12
auto[1] auto[0] 1163 1 T4 9 T6 1 T8 5
auto[1] auto[1] 2934 1 T4 23 T6 2 T7 15


Summary for Variable enable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 672 1 T2 3 T4 12 T6 3
auto[1] 4272 1 T4 36 T7 15 T8 22



Summary for Variable enable_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 672 1 T2 3 T4 12 T6 3
auto[1] 4272 1 T4 36 T7 15 T8 22



Summary for Variable rst_n

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for rst_n

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1366 1 T2 1 T4 14 T6 1
auto[1] 3578 1 T2 2 T4 34 T6 2



Summary for Variable rst_n_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for rst_n_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1366 1 T2 1 T4 14 T6 1
auto[1] 3578 1 T2 2 T4 34 T6 2



Summary for Cross sw_rst_cross

Samples crossed: enable rst_n
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for sw_rst_cross

Bins
enablerst_nCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 189 1 T2 1 T4 3 T6 1
auto[0] auto[1] 483 1 T2 2 T4 9 T6 2
auto[1] auto[0] 1177 1 T4 11 T8 6 T9 6
auto[1] auto[1] 3095 1 T4 25 T7 15 T8 16


Summary for Variable enable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 485 1 T2 3 T4 8 T8 8
auto[1] 4459 1 T4 40 T6 3 T7 15



Summary for Variable enable_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 485 1 T2 3 T4 8 T8 8
auto[1] 4459 1 T4 40 T6 3 T7 15



Summary for Variable rst_n

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for rst_n

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1390 1 T2 1 T4 12 T6 1
auto[1] 3554 1 T2 2 T4 36 T6 2



Summary for Variable rst_n_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for rst_n_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1390 1 T2 1 T4 12 T6 1
auto[1] 3554 1 T2 2 T4 36 T6 2



Summary for Cross sw_rst_cross

Samples crossed: enable rst_n
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for sw_rst_cross

Bins
enablerst_nCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 144 1 T2 1 T4 2 T8 2
auto[0] auto[1] 341 1 T2 2 T4 6 T8 6
auto[1] auto[0] 1246 1 T4 10 T6 1 T8 7
auto[1] auto[1] 3213 1 T4 30 T6 2 T7 15


Summary for Variable enable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 256 1 T4 4 T8 4 T10 4
auto[1] 4688 1 T2 3 T4 44 T6 3



Summary for Variable enable_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 256 1 T4 4 T8 4 T10 4
auto[1] 4688 1 T2 3 T4 44 T6 3



Summary for Variable rst_n

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for rst_n

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1334 1 T4 11 T6 1 T8 9
auto[1] 3610 1 T2 3 T4 37 T6 2



Summary for Variable rst_n_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for rst_n_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1334 1 T4 11 T6 1 T8 9
auto[1] 3610 1 T2 3 T4 37 T6 2



Summary for Cross sw_rst_cross

Samples crossed: enable rst_n
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for sw_rst_cross

Bins
enablerst_nCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 77 1 T4 1 T8 1 T10 1
auto[0] auto[1] 179 1 T4 3 T8 3 T10 3
auto[1] auto[0] 1257 1 T4 10 T6 1 T8 8
auto[1] auto[1] 3431 1 T2 3 T4 34 T6 2

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%