Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	516936	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

309325

1

T1

5

T2

128

T3

73

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	437918	1			T2	186		T3	99		T4	467
values[0x0]	194098	1			T1	8		T2	105		T3	54
values[0x1]	194245	1			T1	13		T2	88		T3	59

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	434200	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

392061

1

T1

9

T2

161

T3

99

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4517	1			T3	1		T5	17		T8	3
valid_sources[0x01]	2969	1			T5	7		T6	7		T8	2
valid_sources[0x02]	2717	1			T3	1		T5	24		T6	8
valid_sources[0x03]	3239	1			T5	36		T8	1		T9	49
valid_sources[0x04]	2106	1			T3	5		T5	9		T6	3
valid_sources[0x05]	3890	1			T5	13		T6	2		T8	1
valid_sources[0x06]	3872	1			T3	3		T5	1		T6	2
valid_sources[0x07]	2850	1			T1	1		T5	1		T7	1
valid_sources[0x08]	2520	1			T3	1		T5	29		T7	2
valid_sources[0x09]	3043	1			T3	1		T5	19		T9	55
valid_sources[0x0a]	3257	1			T3	1		T5	28		T6	2
valid_sources[0x0b]	2626	1			T3	1		T5	9		T7	2
valid_sources[0x0c]	2469	1			T3	3		T5	6		T8	4
valid_sources[0x0d]	3053	1			T5	17		T6	1		T7	6
valid_sources[0x0e]	3073	1			T5	11		T8	5		T9	57
valid_sources[0x0f]	3274	1			T5	3		T6	1		T7	1
valid_sources[0x10]	3014	1			T3	1		T5	15		T6	1
valid_sources[0x11]	3844	1			T3	1		T7	9		T8	7
valid_sources[0x12]	3384	1			T3	3		T5	14		T7	2
valid_sources[0x13]	3466	1			T3	2		T5	8		T8	2
valid_sources[0x14]	3050	1			T5	23		T8	11		T9	61
valid_sources[0x15]	3510	1			T3	3		T8	1		T9	79
valid_sources[0x16]	2361	1			T3	1		T5	12		T6	3
valid_sources[0x17]	2821	1			T3	4		T5	6		T7	1
valid_sources[0x18]	4224	1			T2	379		T3	1		T5	1
valid_sources[0x19]	2809	1			T3	2		T5	1		T6	4
valid_sources[0x1a]	3771	1			T3	1		T5	8		T9	68
valid_sources[0x1b]	6734	1			T5	1		T8	8		T9	73
valid_sources[0x1c]	3653	1			T9	64		T10	5		T11	2
valid_sources[0x1d]	3623	1			T3	1		T7	4		T8	1
valid_sources[0x1e]	5814	1			T5	9		T6	9		T8	1
valid_sources[0x1f]	2774	1			T1	1		T7	2		T8	1
valid_sources[0x20]	3035	1			T7	1		T9	62		T10	1
valid_sources[0x21]	2879	1			T5	28		T6	4		T7	4
valid_sources[0x22]	2682	1			T3	1		T5	7		T6	2
valid_sources[0x23]	4049	1			T3	1		T5	27		T6	2
valid_sources[0x24]	3048	1			T5	34		T6	1		T8	2
valid_sources[0x25]	2859	1			T5	16		T8	2		T9	70
valid_sources[0x26]	3038	1			T1	1		T3	5		T5	11
valid_sources[0x27]	2813	1			T3	1		T5	7		T7	2
valid_sources[0x28]	5633	1			T5	15		T6	1		T8	2
valid_sources[0x29]	2596	1			T5	20		T9	79		T10	2
valid_sources[0x2a]	2305	1			T3	3		T5	2		T9	63
valid_sources[0x2b]	2890	1			T1	1		T3	1		T5	8
valid_sources[0x2c]	3078	1			T3	1		T5	11		T6	2
valid_sources[0x2d]	2345	1			T3	1		T5	7		T6	2
valid_sources[0x2e]	2987	1			T5	30		T6	1		T7	5
valid_sources[0x2f]	2962	1			T3	3		T5	7		T8	4
valid_sources[0x30]	3264	1			T3	1		T5	29		T6	1
valid_sources[0x31]	3070	1			T3	1		T5	19		T7	7
valid_sources[0x32]	4284	1			T5	14		T8	5		T9	60
valid_sources[0x33]	5700	1			T3	1		T5	35		T6	2
valid_sources[0x34]	2522	1			T5	25		T6	1		T8	6
valid_sources[0x35]	2427	1			T3	1		T5	4		T6	2
valid_sources[0x36]	2575	1			T3	1		T5	2		T8	1
valid_sources[0x37]	2747	1			T5	12		T6	2		T9	42
valid_sources[0x38]	3469	1			T5	26		T9	54		T10	1
valid_sources[0x39]	2395	1			T5	17		T6	4		T8	2
valid_sources[0x3a]	3467	1			T1	1		T3	2		T5	2
valid_sources[0x3b]	3109	1			T5	2		T7	2		T9	47
valid_sources[0x3c]	2786	1			T5	15		T6	1		T9	57
valid_sources[0x3d]	2611	1			T5	3		T8	2		T9	62
valid_sources[0x3e]	2887	1			T3	3		T7	3		T8	2
valid_sources[0x3f]	4192	1			T3	1		T5	42		T7	2
valid_sources[0x40]	3513	1			T5	4		T7	2		T8	5
valid_sources[0x41]	3210	1			T3	2		T5	12		T7	7
valid_sources[0x42]	3026	1			T5	13		T6	1		T9	62
valid_sources[0x43]	2229	1			T3	1		T5	6		T8	9
valid_sources[0x44]	2474	1			T3	2		T5	17		T9	61
valid_sources[0x45]	2146	1			T3	1		T5	23		T6	8
valid_sources[0x46]	2769	1			T3	1		T5	8		T7	1
valid_sources[0x47]	2597	1			T3	1		T5	15		T8	1
valid_sources[0x48]	3469	1			T3	1		T5	9		T8	2
valid_sources[0x49]	2619	1			T3	1		T5	5		T9	57
valid_sources[0x4a]	2603	1			T5	10		T8	3		T9	67
valid_sources[0x4b]	2407	1			T3	1		T5	25		T8	4
valid_sources[0x4c]	3186	1			T3	1		T5	19		T7	6
valid_sources[0x4d]	3031	1			T7	1		T8	4		T9	56
valid_sources[0x4e]	2464	1			T5	21		T8	3		T9	77
valid_sources[0x4f]	3289	1			T5	5		T7	3		T8	4
valid_sources[0x50]	2348	1			T1	1		T3	2		T5	49
valid_sources[0x51]	3057	1			T5	7		T6	4		T7	1
valid_sources[0x52]	2574	1			T5	21		T6	2		T8	7
valid_sources[0x53]	4161	1			T5	4		T7	2		T8	4
valid_sources[0x54]	2965	1			T5	7		T7	4		T8	3
valid_sources[0x55]	4504	1			T3	2		T5	8		T6	1
valid_sources[0x56]	2432	1			T3	1		T5	14		T7	3
valid_sources[0x57]	2819	1			T5	1		T8	1		T9	71
valid_sources[0x58]	5062	1			T3	1		T6	6		T8	6
valid_sources[0x59]	6517	1			T1	1		T5	10		T9	48
valid_sources[0x5a]	2571	1			T5	23		T7	3		T8	2
valid_sources[0x5b]	3131	1			T5	10		T6	4		T7	4
valid_sources[0x5c]	2883	1			T3	1		T5	13		T6	1
valid_sources[0x5d]	2669	1			T3	1		T5	5		T6	2
valid_sources[0x5e]	2706	1			T5	13		T8	2		T9	46
valid_sources[0x5f]	2530	1			T1	1		T5	4		T8	2
valid_sources[0x60]	2956	1			T3	2		T5	5		T6	3
valid_sources[0x61]	3125	1			T5	34		T6	1		T8	3
valid_sources[0x62]	2502	1			T1	1		T3	1		T5	12
valid_sources[0x63]	3137	1			T3	1		T5	4		T7	1
valid_sources[0x64]	5399	1			T1	1		T3	1		T5	19
valid_sources[0x65]	3875	1			T3	5		T5	3		T7	2
valid_sources[0x66]	2705	1			T5	14		T7	4		T9	66
valid_sources[0x67]	3648	1			T5	12		T6	7		T8	2
valid_sources[0x68]	3234	1			T1	1		T5	15		T7	1
valid_sources[0x69]	2670	1			T5	1		T6	6		T7	2
valid_sources[0x6a]	2826	1			T3	3		T5	24		T6	2
valid_sources[0x6b]	2910	1			T5	1		T6	2		T8	2
valid_sources[0x6c]	2382	1			T3	1		T6	2		T9	59
valid_sources[0x6d]	2900	1			T3	2		T5	13		T8	7
valid_sources[0x6e]	2809	1			T5	37		T6	5		T9	45
valid_sources[0x6f]	2613	1			T3	1		T5	26		T6	6
valid_sources[0x70]	2453	1			T5	6		T8	3		T9	72
valid_sources[0x71]	2871	1			T5	12		T6	1		T8	2
valid_sources[0x72]	2704	1			T5	1		T7	5		T8	2
valid_sources[0x73]	2454	1			T5	9		T7	1		T8	6
valid_sources[0x74]	2888	1			T5	14		T8	3		T9	54
valid_sources[0x75]	3528	1			T1	1		T3	2		T5	18
valid_sources[0x76]	2963	1			T3	1		T5	11		T6	3
valid_sources[0x77]	2578	1			T5	5		T7	1		T8	1
valid_sources[0x78]	2754	1			T1	1		T8	4		T9	46
valid_sources[0x79]	2604	1			T3	1		T5	11		T6	6
valid_sources[0x7a]	3931	1			T5	14		T7	3		T8	11
valid_sources[0x7b]	3152	1			T5	40		T7	4		T8	4
valid_sources[0x7c]	3074	1			T5	25		T8	2		T9	63
valid_sources[0x7d]	3417	1			T3	1		T5	24		T8	6
valid_sources[0x7e]	2478	1			T5	11		T7	6		T8	1
valid_sources[0x7f]	2593	1			T3	2		T5	3		T7	3
valid_sources[0x80]	3285	1			T3	1		T5	1		T8	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

204969

1

T2

75

T3

46

T4

244

values[0x0]

all_enables

biggest_size

67891

1

T1

3

T2

32

T3

21

values[0x1]

all_enables

biggest_size

36465

1

T1

2

T2

21

T3

6