SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 58.33 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_rstmgr_reg_block.reset_req.val | 16.67 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_scanmode_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
16.67 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 5 | 1 | 16.67 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 5 | 1 | 16.67 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 5 | 1 | 16.67 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
others[0] | 0 | 1 | 1 | |
others[1] | 0 | 1 | 1 | |
others[2] | 0 | 1 | 1 | |
others[3] | 0 | 1 | 1 | |
false | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
true | 4442 | 1 | T2 | 1 | T3 | 1 | T5 | 18 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 595 | 1 | T3 | 27 | T67 | 15 | T29 | 18 | ||||
others[1] | 586 | 1 | T3 | 21 | T67 | 20 | T29 | 15 | ||||
others[2] | 613 | 1 | T3 | 26 | T67 | 24 | T29 | 20 | ||||
others[3] | 933 | 1 | T3 | 28 | T67 | 37 | T29 | 29 | ||||
false | 19892 | 1 | T1 | 1 | T2 | 6 | T3 | 23 | ||||
true | 1809 | 1 | T2 | 1 | T3 | 1 | T5 | 10 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |