SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.55 | 100.00 | 98.21 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_por |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_por_io |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_por_io_div2 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_por_io_div4 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_por_usb |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_lc |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc_shadowed |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_lc_shadowed |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc_aon |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc_io |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_lc_io |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc_io_div2 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_lc_io_div2 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_daon_lc_io_div4 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_d0_lc_io_div4 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_daon_lc_io_div4_shadowed |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_d0_lc_io_div4_shadowed |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc_usb |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_lc_usb |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_sys |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_sys_io_div4 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_spi_device |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_spi_host0 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_spi_host1 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_usb |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | u_d0_usb_aon |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_i2c0 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_i2c1 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_i2c2 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.55 | 100.00 | 98.21 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.55 | 100.00 | 98.21 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 15147 | 15147 | 0 | 0 |
OutputsKnown_A | 329280029 | 185802453 | 0 | 0 |
gen_no_flops.OutputDelay_A | 329280029 | 185802453 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 15147 | 15147 | 0 | 0 |
T1 | 33 | 33 | 0 | 0 |
T2 | 33 | 33 | 0 | 0 |
T3 | 33 | 33 | 0 | 0 |
T4 | 33 | 33 | 0 | 0 |
T5 | 33 | 33 | 0 | 0 |
T6 | 33 | 33 | 0 | 0 |
T7 | 33 | 33 | 0 | 0 |
T8 | 33 | 33 | 0 | 0 |
T9 | 33 | 33 | 0 | 0 |
T10 | 33 | 33 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 329280029 | 185802453 | 0 | 0 |
T1 | 53048 | 31897 | 0 | 0 |
T2 | 88452 | 55247 | 0 | 0 |
T3 | 125158 | 94251 | 0 | 0 |
T4 | 356984 | 337939 | 0 | 0 |
T5 | 690600 | 269401 | 0 | 0 |
T6 | 81139 | 48281 | 0 | 0 |
T7 | 75395 | 47454 | 0 | 0 |
T8 | 189619 | 169771 | 0 | 0 |
T9 | 7386562 | 5786332 | 0 | 0 |
T10 | 200278 | 180529 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 329280029 | 185802453 | 0 | 0 |
T1 | 53048 | 31897 | 0 | 0 |
T2 | 88452 | 55247 | 0 | 0 |
T3 | 125158 | 94251 | 0 | 0 |
T4 | 356984 | 337939 | 0 | 0 |
T5 | 690600 | 269401 | 0 | 0 |
T6 | 81139 | 48281 | 0 | 0 |
T7 | 75395 | 47454 | 0 | 0 |
T8 | 189619 | 169771 | 0 | 0 |
T9 | 7386562 | 5786332 | 0 | 0 |
T10 | 200278 | 180529 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 459 | 459 | 0 | 0 |
OutputsKnown_A | 11216477 | 6546037 | 0 | 0 |
gen_no_flops.OutputDelay_A | 11216477 | 6546037 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 459 | 459 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11216477 | 6546037 | 0 | 0 |
T1 | 1624 | 985 | 0 | 0 |
T2 | 2820 | 1871 | 0 | 0 |
T3 | 4166 | 3147 | 0 | 0 |
T4 | 10904 | 10259 | 0 | 0 |
T5 | 25320 | 11129 | 0 | 0 |
T6 | 2739 | 1753 | 0 | 0 |
T7 | 3139 | 2494 | 0 | 0 |
T8 | 5811 | 5163 | 0 | 0 |
T9 | 247746 | 192956 | 0 | 0 |
T10 | 6134 | 5489 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11216477 | 6546037 | 0 | 0 |
T1 | 1624 | 985 | 0 | 0 |
T2 | 2820 | 1871 | 0 | 0 |
T3 | 4166 | 3147 | 0 | 0 |
T4 | 10904 | 10259 | 0 | 0 |
T5 | 25320 | 11129 | 0 | 0 |
T6 | 2739 | 1753 | 0 | 0 |
T7 | 3139 | 2494 | 0 | 0 |
T8 | 5811 | 5163 | 0 | 0 |
T9 | 247746 | 192956 | 0 | 0 |
T10 | 6134 | 5489 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 459 | 459 | 0 | 0 |
OutputsKnown_A | 9939486 | 5601763 | 0 | 0 |
gen_no_flops.OutputDelay_A | 9939486 | 5601763 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 459 | 459 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9939486 | 5601763 | 0 | 0 |
T1 | 1607 | 966 | 0 | 0 |
T2 | 2676 | 1668 | 0 | 0 |
T3 | 3781 | 2847 | 0 | 0 |
T4 | 10815 | 10240 | 0 | 0 |
T5 | 20790 | 8071 | 0 | 0 |
T6 | 2450 | 1454 | 0 | 0 |
T7 | 2258 | 1405 | 0 | 0 |
T8 | 5744 | 5144 | 0 | 0 |
T9 | 223088 | 174793 | 0 | 0 |
T10 | 6067 | 5470 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9939486 | 5601763 | 0 | 0 |
T1 | 1607 | 966 | 0 | 0 |
T2 | 2676 | 1668 | 0 | 0 |
T3 | 3781 | 2847 | 0 | 0 |
T4 | 10815 | 10240 | 0 | 0 |
T5 | 20790 | 8071 | 0 | 0 |
T6 | 2450 | 1454 | 0 | 0 |
T7 | 2258 | 1405 | 0 | 0 |
T8 | 5744 | 5144 | 0 | 0 |
T9 | 223088 | 174793 | 0 | 0 |
T10 | 6067 | 5470 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 459 | 459 | 0 | 0 |
OutputsKnown_A | 9939486 | 5601763 | 0 | 0 |
gen_no_flops.OutputDelay_A | 9939486 | 5601763 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 459 | 459 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9939486 | 5601763 | 0 | 0 |
T1 | 1607 | 966 | 0 | 0 |
T2 | 2676 | 1668 | 0 | 0 |
T3 | 3781 | 2847 | 0 | 0 |
T4 | 10815 | 10240 | 0 | 0 |
T5 | 20790 | 8071 | 0 | 0 |
T6 | 2450 | 1454 | 0 | 0 |
T7 | 2258 | 1405 | 0 | 0 |
T8 | 5744 | 5144 | 0 | 0 |
T9 | 223088 | 174793 | 0 | 0 |
T10 | 6067 | 5470 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9939486 | 5601763 | 0 | 0 |
T1 | 1607 | 966 | 0 | 0 |
T2 | 2676 | 1668 | 0 | 0 |
T3 | 3781 | 2847 | 0 | 0 |
T4 | 10815 | 10240 | 0 | 0 |
T5 | 20790 | 8071 | 0 | 0 |
T6 | 2450 | 1454 | 0 | 0 |
T7 | 2258 | 1405 | 0 | 0 |
T8 | 5744 | 5144 | 0 | 0 |
T9 | 223088 | 174793 | 0 | 0 |
T10 | 6067 | 5470 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 459 | 459 | 0 | 0 |
OutputsKnown_A | 9939486 | 5601763 | 0 | 0 |
gen_no_flops.OutputDelay_A | 9939486 | 5601763 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 459 | 459 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9939486 | 5601763 | 0 | 0 |
T1 | 1607 | 966 | 0 | 0 |
T2 | 2676 | 1668 | 0 | 0 |
T3 | 3781 | 2847 | 0 | 0 |
T4 | 10815 | 10240 | 0 | 0 |
T5 | 20790 | 8071 | 0 | 0 |
T6 | 2450 | 1454 | 0 | 0 |
T7 | 2258 | 1405 | 0 | 0 |
T8 | 5744 | 5144 | 0 | 0 |
T9 | 223088 | 174793 | 0 | 0 |
T10 | 6067 | 5470 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9939486 | 5601763 | 0 | 0 |
T1 | 1607 | 966 | 0 | 0 |
T2 | 2676 | 1668 | 0 | 0 |
T3 | 3781 | 2847 | 0 | 0 |
T4 | 10815 | 10240 | 0 | 0 |
T5 | 20790 | 8071 | 0 | 0 |
T6 | 2450 | 1454 | 0 | 0 |
T7 | 2258 | 1405 | 0 | 0 |
T8 | 5744 | 5144 | 0 | 0 |
T9 | 223088 | 174793 | 0 | 0 |
T10 | 6067 | 5470 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 459 | 459 | 0 | 0 |
OutputsKnown_A | 9939486 | 5601763 | 0 | 0 |
gen_no_flops.OutputDelay_A | 9939486 | 5601763 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 459 | 459 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9939486 | 5601763 | 0 | 0 |
T1 | 1607 | 966 | 0 | 0 |
T2 | 2676 | 1668 | 0 | 0 |
T3 | 3781 | 2847 | 0 | 0 |
T4 | 10815 | 10240 | 0 | 0 |
T5 | 20790 | 8071 | 0 | 0 |
T6 | 2450 | 1454 | 0 | 0 |
T7 | 2258 | 1405 | 0 | 0 |
T8 | 5744 | 5144 | 0 | 0 |
T9 | 223088 | 174793 | 0 | 0 |
T10 | 6067 | 5470 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9939486 | 5601763 | 0 | 0 |
T1 | 1607 | 966 | 0 | 0 |
T2 | 2676 | 1668 | 0 | 0 |
T3 | 3781 | 2847 | 0 | 0 |
T4 | 10815 | 10240 | 0 | 0 |
T5 | 20790 | 8071 | 0 | 0 |
T6 | 2450 | 1454 | 0 | 0 |
T7 | 2258 | 1405 | 0 | 0 |
T8 | 5744 | 5144 | 0 | 0 |
T9 | 223088 | 174793 | 0 | 0 |
T10 | 6067 | 5470 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 459 | 459 | 0 | 0 |
OutputsKnown_A | 9939486 | 5601763 | 0 | 0 |
gen_no_flops.OutputDelay_A | 9939486 | 5601763 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 459 | 459 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9939486 | 5601763 | 0 | 0 |
T1 | 1607 | 966 | 0 | 0 |
T2 | 2676 | 1668 | 0 | 0 |
T3 | 3781 | 2847 | 0 | 0 |
T4 | 10815 | 10240 | 0 | 0 |
T5 | 20790 | 8071 | 0 | 0 |
T6 | 2450 | 1454 | 0 | 0 |
T7 | 2258 | 1405 | 0 | 0 |
T8 | 5744 | 5144 | 0 | 0 |
T9 | 223088 | 174793 | 0 | 0 |
T10 | 6067 | 5470 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9939486 | 5601763 | 0 | 0 |
T1 | 1607 | 966 | 0 | 0 |
T2 | 2676 | 1668 | 0 | 0 |
T3 | 3781 | 2847 | 0 | 0 |
T4 | 10815 | 10240 | 0 | 0 |
T5 | 20790 | 8071 | 0 | 0 |
T6 | 2450 | 1454 | 0 | 0 |
T7 | 2258 | 1405 | 0 | 0 |
T8 | 5744 | 5144 | 0 | 0 |
T9 | 223088 | 174793 | 0 | 0 |
T10 | 6067 | 5470 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 459 | 459 | 0 | 0 |
OutputsKnown_A | 9939486 | 5601763 | 0 | 0 |
gen_no_flops.OutputDelay_A | 9939486 | 5601763 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 459 | 459 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9939486 | 5601763 | 0 | 0 |
T1 | 1607 | 966 | 0 | 0 |
T2 | 2676 | 1668 | 0 | 0 |
T3 | 3781 | 2847 | 0 | 0 |
T4 | 10815 | 10240 | 0 | 0 |
T5 | 20790 | 8071 | 0 | 0 |
T6 | 2450 | 1454 | 0 | 0 |
T7 | 2258 | 1405 | 0 | 0 |
T8 | 5744 | 5144 | 0 | 0 |
T9 | 223088 | 174793 | 0 | 0 |
T10 | 6067 | 5470 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9939486 | 5601763 | 0 | 0 |
T1 | 1607 | 966 | 0 | 0 |
T2 | 2676 | 1668 | 0 | 0 |
T3 | 3781 | 2847 | 0 | 0 |
T4 | 10815 | 10240 | 0 | 0 |
T5 | 20790 | 8071 | 0 | 0 |
T6 | 2450 | 1454 | 0 | 0 |
T7 | 2258 | 1405 | 0 | 0 |
T8 | 5744 | 5144 | 0 | 0 |
T9 | 223088 | 174793 | 0 | 0 |
T10 | 6067 | 5470 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 459 | 459 | 0 | 0 |
OutputsKnown_A | 9939486 | 5601763 | 0 | 0 |
gen_no_flops.OutputDelay_A | 9939486 | 5601763 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 459 | 459 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9939486 | 5601763 | 0 | 0 |
T1 | 1607 | 966 | 0 | 0 |
T2 | 2676 | 1668 | 0 | 0 |
T3 | 3781 | 2847 | 0 | 0 |
T4 | 10815 | 10240 | 0 | 0 |
T5 | 20790 | 8071 | 0 | 0 |
T6 | 2450 | 1454 | 0 | 0 |
T7 | 2258 | 1405 | 0 | 0 |
T8 | 5744 | 5144 | 0 | 0 |
T9 | 223088 | 174793 | 0 | 0 |
T10 | 6067 | 5470 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9939486 | 5601763 | 0 | 0 |
T1 | 1607 | 966 | 0 | 0 |
T2 | 2676 | 1668 | 0 | 0 |
T3 | 3781 | 2847 | 0 | 0 |
T4 | 10815 | 10240 | 0 | 0 |
T5 | 20790 | 8071 | 0 | 0 |
T6 | 2450 | 1454 | 0 | 0 |
T7 | 2258 | 1405 | 0 | 0 |
T8 | 5744 | 5144 | 0 | 0 |
T9 | 223088 | 174793 | 0 | 0 |
T10 | 6067 | 5470 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 459 | 459 | 0 | 0 |
OutputsKnown_A | 9939486 | 5601763 | 0 | 0 |
gen_no_flops.OutputDelay_A | 9939486 | 5601763 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 459 | 459 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9939486 | 5601763 | 0 | 0 |
T1 | 1607 | 966 | 0 | 0 |
T2 | 2676 | 1668 | 0 | 0 |
T3 | 3781 | 2847 | 0 | 0 |
T4 | 10815 | 10240 | 0 | 0 |
T5 | 20790 | 8071 | 0 | 0 |
T6 | 2450 | 1454 | 0 | 0 |
T7 | 2258 | 1405 | 0 | 0 |
T8 | 5744 | 5144 | 0 | 0 |
T9 | 223088 | 174793 | 0 | 0 |
T10 | 6067 | 5470 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9939486 | 5601763 | 0 | 0 |
T1 | 1607 | 966 | 0 | 0 |
T2 | 2676 | 1668 | 0 | 0 |
T3 | 3781 | 2847 | 0 | 0 |
T4 | 10815 | 10240 | 0 | 0 |
T5 | 20790 | 8071 | 0 | 0 |
T6 | 2450 | 1454 | 0 | 0 |
T7 | 2258 | 1405 | 0 | 0 |
T8 | 5744 | 5144 | 0 | 0 |
T9 | 223088 | 174793 | 0 | 0 |
T10 | 6067 | 5470 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 459 | 459 | 0 | 0 |
OutputsKnown_A | 9939486 | 5601763 | 0 | 0 |
gen_no_flops.OutputDelay_A | 9939486 | 5601763 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 459 | 459 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9939486 | 5601763 | 0 | 0 |
T1 | 1607 | 966 | 0 | 0 |
T2 | 2676 | 1668 | 0 | 0 |
T3 | 3781 | 2847 | 0 | 0 |
T4 | 10815 | 10240 | 0 | 0 |
T5 | 20790 | 8071 | 0 | 0 |
T6 | 2450 | 1454 | 0 | 0 |
T7 | 2258 | 1405 | 0 | 0 |
T8 | 5744 | 5144 | 0 | 0 |
T9 | 223088 | 174793 | 0 | 0 |
T10 | 6067 | 5470 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9939486 | 5601763 | 0 | 0 |
T1 | 1607 | 966 | 0 | 0 |
T2 | 2676 | 1668 | 0 | 0 |
T3 | 3781 | 2847 | 0 | 0 |
T4 | 10815 | 10240 | 0 | 0 |
T5 | 20790 | 8071 | 0 | 0 |
T6 | 2450 | 1454 | 0 | 0 |
T7 | 2258 | 1405 | 0 | 0 |
T8 | 5744 | 5144 | 0 | 0 |
T9 | 223088 | 174793 | 0 | 0 |
T10 | 6067 | 5470 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 459 | 459 | 0 | 0 |
OutputsKnown_A | 9939486 | 5601763 | 0 | 0 |
gen_no_flops.OutputDelay_A | 9939486 | 5601763 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 459 | 459 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9939486 | 5601763 | 0 | 0 |
T1 | 1607 | 966 | 0 | 0 |
T2 | 2676 | 1668 | 0 | 0 |
T3 | 3781 | 2847 | 0 | 0 |
T4 | 10815 | 10240 | 0 | 0 |
T5 | 20790 | 8071 | 0 | 0 |
T6 | 2450 | 1454 | 0 | 0 |
T7 | 2258 | 1405 | 0 | 0 |
T8 | 5744 | 5144 | 0 | 0 |
T9 | 223088 | 174793 | 0 | 0 |
T10 | 6067 | 5470 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9939486 | 5601763 | 0 | 0 |
T1 | 1607 | 966 | 0 | 0 |
T2 | 2676 | 1668 | 0 | 0 |
T3 | 3781 | 2847 | 0 | 0 |
T4 | 10815 | 10240 | 0 | 0 |
T5 | 20790 | 8071 | 0 | 0 |
T6 | 2450 | 1454 | 0 | 0 |
T7 | 2258 | 1405 | 0 | 0 |
T8 | 5744 | 5144 | 0 | 0 |
T9 | 223088 | 174793 | 0 | 0 |
T10 | 6067 | 5470 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 459 | 459 | 0 | 0 |
OutputsKnown_A | 9939486 | 5601763 | 0 | 0 |
gen_no_flops.OutputDelay_A | 9939486 | 5601763 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 459 | 459 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9939486 | 5601763 | 0 | 0 |
T1 | 1607 | 966 | 0 | 0 |
T2 | 2676 | 1668 | 0 | 0 |
T3 | 3781 | 2847 | 0 | 0 |
T4 | 10815 | 10240 | 0 | 0 |
T5 | 20790 | 8071 | 0 | 0 |
T6 | 2450 | 1454 | 0 | 0 |
T7 | 2258 | 1405 | 0 | 0 |
T8 | 5744 | 5144 | 0 | 0 |
T9 | 223088 | 174793 | 0 | 0 |
T10 | 6067 | 5470 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9939486 | 5601763 | 0 | 0 |
T1 | 1607 | 966 | 0 | 0 |
T2 | 2676 | 1668 | 0 | 0 |
T3 | 3781 | 2847 | 0 | 0 |
T4 | 10815 | 10240 | 0 | 0 |
T5 | 20790 | 8071 | 0 | 0 |
T6 | 2450 | 1454 | 0 | 0 |
T7 | 2258 | 1405 | 0 | 0 |
T8 | 5744 | 5144 | 0 | 0 |
T9 | 223088 | 174793 | 0 | 0 |
T10 | 6067 | 5470 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 459 | 459 | 0 | 0 |
OutputsKnown_A | 9939486 | 5601763 | 0 | 0 |
gen_no_flops.OutputDelay_A | 9939486 | 5601763 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 459 | 459 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9939486 | 5601763 | 0 | 0 |
T1 | 1607 | 966 | 0 | 0 |
T2 | 2676 | 1668 | 0 | 0 |
T3 | 3781 | 2847 | 0 | 0 |
T4 | 10815 | 10240 | 0 | 0 |
T5 | 20790 | 8071 | 0 | 0 |
T6 | 2450 | 1454 | 0 | 0 |
T7 | 2258 | 1405 | 0 | 0 |
T8 | 5744 | 5144 | 0 | 0 |
T9 | 223088 | 174793 | 0 | 0 |
T10 | 6067 | 5470 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9939486 | 5601763 | 0 | 0 |
T1 | 1607 | 966 | 0 | 0 |
T2 | 2676 | 1668 | 0 | 0 |
T3 | 3781 | 2847 | 0 | 0 |
T4 | 10815 | 10240 | 0 | 0 |
T5 | 20790 | 8071 | 0 | 0 |
T6 | 2450 | 1454 | 0 | 0 |
T7 | 2258 | 1405 | 0 | 0 |
T8 | 5744 | 5144 | 0 | 0 |
T9 | 223088 | 174793 | 0 | 0 |
T10 | 6067 | 5470 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 459 | 459 | 0 | 0 |
OutputsKnown_A | 9939486 | 5601763 | 0 | 0 |
gen_no_flops.OutputDelay_A | 9939486 | 5601763 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 459 | 459 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9939486 | 5601763 | 0 | 0 |
T1 | 1607 | 966 | 0 | 0 |
T2 | 2676 | 1668 | 0 | 0 |
T3 | 3781 | 2847 | 0 | 0 |
T4 | 10815 | 10240 | 0 | 0 |
T5 | 20790 | 8071 | 0 | 0 |
T6 | 2450 | 1454 | 0 | 0 |
T7 | 2258 | 1405 | 0 | 0 |
T8 | 5744 | 5144 | 0 | 0 |
T9 | 223088 | 174793 | 0 | 0 |
T10 | 6067 | 5470 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9939486 | 5601763 | 0 | 0 |
T1 | 1607 | 966 | 0 | 0 |
T2 | 2676 | 1668 | 0 | 0 |
T3 | 3781 | 2847 | 0 | 0 |
T4 | 10815 | 10240 | 0 | 0 |
T5 | 20790 | 8071 | 0 | 0 |
T6 | 2450 | 1454 | 0 | 0 |
T7 | 2258 | 1405 | 0 | 0 |
T8 | 5744 | 5144 | 0 | 0 |
T9 | 223088 | 174793 | 0 | 0 |
T10 | 6067 | 5470 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 459 | 459 | 0 | 0 |
OutputsKnown_A | 9939486 | 5601763 | 0 | 0 |
gen_no_flops.OutputDelay_A | 9939486 | 5601763 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 459 | 459 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9939486 | 5601763 | 0 | 0 |
T1 | 1607 | 966 | 0 | 0 |
T2 | 2676 | 1668 | 0 | 0 |
T3 | 3781 | 2847 | 0 | 0 |
T4 | 10815 | 10240 | 0 | 0 |
T5 | 20790 | 8071 | 0 | 0 |
T6 | 2450 | 1454 | 0 | 0 |
T7 | 2258 | 1405 | 0 | 0 |
T8 | 5744 | 5144 | 0 | 0 |
T9 | 223088 | 174793 | 0 | 0 |
T10 | 6067 | 5470 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9939486 | 5601763 | 0 | 0 |
T1 | 1607 | 966 | 0 | 0 |
T2 | 2676 | 1668 | 0 | 0 |
T3 | 3781 | 2847 | 0 | 0 |
T4 | 10815 | 10240 | 0 | 0 |
T5 | 20790 | 8071 | 0 | 0 |
T6 | 2450 | 1454 | 0 | 0 |
T7 | 2258 | 1405 | 0 | 0 |
T8 | 5744 | 5144 | 0 | 0 |
T9 | 223088 | 174793 | 0 | 0 |
T10 | 6067 | 5470 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 459 | 459 | 0 | 0 |
OutputsKnown_A | 9939486 | 5601763 | 0 | 0 |
gen_no_flops.OutputDelay_A | 9939486 | 5601763 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 459 | 459 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9939486 | 5601763 | 0 | 0 |
T1 | 1607 | 966 | 0 | 0 |
T2 | 2676 | 1668 | 0 | 0 |
T3 | 3781 | 2847 | 0 | 0 |
T4 | 10815 | 10240 | 0 | 0 |
T5 | 20790 | 8071 | 0 | 0 |
T6 | 2450 | 1454 | 0 | 0 |
T7 | 2258 | 1405 | 0 | 0 |
T8 | 5744 | 5144 | 0 | 0 |
T9 | 223088 | 174793 | 0 | 0 |
T10 | 6067 | 5470 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9939486 | 5601763 | 0 | 0 |
T1 | 1607 | 966 | 0 | 0 |
T2 | 2676 | 1668 | 0 | 0 |
T3 | 3781 | 2847 | 0 | 0 |
T4 | 10815 | 10240 | 0 | 0 |
T5 | 20790 | 8071 | 0 | 0 |
T6 | 2450 | 1454 | 0 | 0 |
T7 | 2258 | 1405 | 0 | 0 |
T8 | 5744 | 5144 | 0 | 0 |
T9 | 223088 | 174793 | 0 | 0 |
T10 | 6067 | 5470 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 459 | 459 | 0 | 0 |
OutputsKnown_A | 9939486 | 5601763 | 0 | 0 |
gen_no_flops.OutputDelay_A | 9939486 | 5601763 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 459 | 459 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9939486 | 5601763 | 0 | 0 |
T1 | 1607 | 966 | 0 | 0 |
T2 | 2676 | 1668 | 0 | 0 |
T3 | 3781 | 2847 | 0 | 0 |
T4 | 10815 | 10240 | 0 | 0 |
T5 | 20790 | 8071 | 0 | 0 |
T6 | 2450 | 1454 | 0 | 0 |
T7 | 2258 | 1405 | 0 | 0 |
T8 | 5744 | 5144 | 0 | 0 |
T9 | 223088 | 174793 | 0 | 0 |
T10 | 6067 | 5470 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9939486 | 5601763 | 0 | 0 |
T1 | 1607 | 966 | 0 | 0 |
T2 | 2676 | 1668 | 0 | 0 |
T3 | 3781 | 2847 | 0 | 0 |
T4 | 10815 | 10240 | 0 | 0 |
T5 | 20790 | 8071 | 0 | 0 |
T6 | 2450 | 1454 | 0 | 0 |
T7 | 2258 | 1405 | 0 | 0 |
T8 | 5744 | 5144 | 0 | 0 |
T9 | 223088 | 174793 | 0 | 0 |
T10 | 6067 | 5470 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 459 | 459 | 0 | 0 |
OutputsKnown_A | 9939486 | 5601763 | 0 | 0 |
gen_no_flops.OutputDelay_A | 9939486 | 5601763 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 459 | 459 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9939486 | 5601763 | 0 | 0 |
T1 | 1607 | 966 | 0 | 0 |
T2 | 2676 | 1668 | 0 | 0 |
T3 | 3781 | 2847 | 0 | 0 |
T4 | 10815 | 10240 | 0 | 0 |
T5 | 20790 | 8071 | 0 | 0 |
T6 | 2450 | 1454 | 0 | 0 |
T7 | 2258 | 1405 | 0 | 0 |
T8 | 5744 | 5144 | 0 | 0 |
T9 | 223088 | 174793 | 0 | 0 |
T10 | 6067 | 5470 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9939486 | 5601763 | 0 | 0 |
T1 | 1607 | 966 | 0 | 0 |
T2 | 2676 | 1668 | 0 | 0 |
T3 | 3781 | 2847 | 0 | 0 |
T4 | 10815 | 10240 | 0 | 0 |
T5 | 20790 | 8071 | 0 | 0 |
T6 | 2450 | 1454 | 0 | 0 |
T7 | 2258 | 1405 | 0 | 0 |
T8 | 5744 | 5144 | 0 | 0 |
T9 | 223088 | 174793 | 0 | 0 |
T10 | 6067 | 5470 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 459 | 459 | 0 | 0 |
OutputsKnown_A | 9939486 | 5601763 | 0 | 0 |
gen_no_flops.OutputDelay_A | 9939486 | 5601763 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 459 | 459 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9939486 | 5601763 | 0 | 0 |
T1 | 1607 | 966 | 0 | 0 |
T2 | 2676 | 1668 | 0 | 0 |
T3 | 3781 | 2847 | 0 | 0 |
T4 | 10815 | 10240 | 0 | 0 |
T5 | 20790 | 8071 | 0 | 0 |
T6 | 2450 | 1454 | 0 | 0 |
T7 | 2258 | 1405 | 0 | 0 |
T8 | 5744 | 5144 | 0 | 0 |
T9 | 223088 | 174793 | 0 | 0 |
T10 | 6067 | 5470 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9939486 | 5601763 | 0 | 0 |
T1 | 1607 | 966 | 0 | 0 |
T2 | 2676 | 1668 | 0 | 0 |
T3 | 3781 | 2847 | 0 | 0 |
T4 | 10815 | 10240 | 0 | 0 |
T5 | 20790 | 8071 | 0 | 0 |
T6 | 2450 | 1454 | 0 | 0 |
T7 | 2258 | 1405 | 0 | 0 |
T8 | 5744 | 5144 | 0 | 0 |
T9 | 223088 | 174793 | 0 | 0 |
T10 | 6067 | 5470 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 459 | 459 | 0 | 0 |
OutputsKnown_A | 9939486 | 5601763 | 0 | 0 |
gen_no_flops.OutputDelay_A | 9939486 | 5601763 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 459 | 459 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9939486 | 5601763 | 0 | 0 |
T1 | 1607 | 966 | 0 | 0 |
T2 | 2676 | 1668 | 0 | 0 |
T3 | 3781 | 2847 | 0 | 0 |
T4 | 10815 | 10240 | 0 | 0 |
T5 | 20790 | 8071 | 0 | 0 |
T6 | 2450 | 1454 | 0 | 0 |
T7 | 2258 | 1405 | 0 | 0 |
T8 | 5744 | 5144 | 0 | 0 |
T9 | 223088 | 174793 | 0 | 0 |
T10 | 6067 | 5470 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9939486 | 5601763 | 0 | 0 |
T1 | 1607 | 966 | 0 | 0 |
T2 | 2676 | 1668 | 0 | 0 |
T3 | 3781 | 2847 | 0 | 0 |
T4 | 10815 | 10240 | 0 | 0 |
T5 | 20790 | 8071 | 0 | 0 |
T6 | 2450 | 1454 | 0 | 0 |
T7 | 2258 | 1405 | 0 | 0 |
T8 | 5744 | 5144 | 0 | 0 |
T9 | 223088 | 174793 | 0 | 0 |
T10 | 6067 | 5470 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 459 | 459 | 0 | 0 |
OutputsKnown_A | 9939486 | 5601763 | 0 | 0 |
gen_no_flops.OutputDelay_A | 9939486 | 5601763 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 459 | 459 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9939486 | 5601763 | 0 | 0 |
T1 | 1607 | 966 | 0 | 0 |
T2 | 2676 | 1668 | 0 | 0 |
T3 | 3781 | 2847 | 0 | 0 |
T4 | 10815 | 10240 | 0 | 0 |
T5 | 20790 | 8071 | 0 | 0 |
T6 | 2450 | 1454 | 0 | 0 |
T7 | 2258 | 1405 | 0 | 0 |
T8 | 5744 | 5144 | 0 | 0 |
T9 | 223088 | 174793 | 0 | 0 |
T10 | 6067 | 5470 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9939486 | 5601763 | 0 | 0 |
T1 | 1607 | 966 | 0 | 0 |
T2 | 2676 | 1668 | 0 | 0 |
T3 | 3781 | 2847 | 0 | 0 |
T4 | 10815 | 10240 | 0 | 0 |
T5 | 20790 | 8071 | 0 | 0 |
T6 | 2450 | 1454 | 0 | 0 |
T7 | 2258 | 1405 | 0 | 0 |
T8 | 5744 | 5144 | 0 | 0 |
T9 | 223088 | 174793 | 0 | 0 |
T10 | 6067 | 5470 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 459 | 459 | 0 | 0 |
OutputsKnown_A | 9939486 | 5601763 | 0 | 0 |
gen_no_flops.OutputDelay_A | 9939486 | 5601763 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 459 | 459 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9939486 | 5601763 | 0 | 0 |
T1 | 1607 | 966 | 0 | 0 |
T2 | 2676 | 1668 | 0 | 0 |
T3 | 3781 | 2847 | 0 | 0 |
T4 | 10815 | 10240 | 0 | 0 |
T5 | 20790 | 8071 | 0 | 0 |
T6 | 2450 | 1454 | 0 | 0 |
T7 | 2258 | 1405 | 0 | 0 |
T8 | 5744 | 5144 | 0 | 0 |
T9 | 223088 | 174793 | 0 | 0 |
T10 | 6067 | 5470 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9939486 | 5601763 | 0 | 0 |
T1 | 1607 | 966 | 0 | 0 |
T2 | 2676 | 1668 | 0 | 0 |
T3 | 3781 | 2847 | 0 | 0 |
T4 | 10815 | 10240 | 0 | 0 |
T5 | 20790 | 8071 | 0 | 0 |
T6 | 2450 | 1454 | 0 | 0 |
T7 | 2258 | 1405 | 0 | 0 |
T8 | 5744 | 5144 | 0 | 0 |
T9 | 223088 | 174793 | 0 | 0 |
T10 | 6067 | 5470 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 459 | 459 | 0 | 0 |
OutputsKnown_A | 9939486 | 5601763 | 0 | 0 |
gen_no_flops.OutputDelay_A | 9939486 | 5601763 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 459 | 459 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9939486 | 5601763 | 0 | 0 |
T1 | 1607 | 966 | 0 | 0 |
T2 | 2676 | 1668 | 0 | 0 |
T3 | 3781 | 2847 | 0 | 0 |
T4 | 10815 | 10240 | 0 | 0 |
T5 | 20790 | 8071 | 0 | 0 |
T6 | 2450 | 1454 | 0 | 0 |
T7 | 2258 | 1405 | 0 | 0 |
T8 | 5744 | 5144 | 0 | 0 |
T9 | 223088 | 174793 | 0 | 0 |
T10 | 6067 | 5470 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9939486 | 5601763 | 0 | 0 |
T1 | 1607 | 966 | 0 | 0 |
T2 | 2676 | 1668 | 0 | 0 |
T3 | 3781 | 2847 | 0 | 0 |
T4 | 10815 | 10240 | 0 | 0 |
T5 | 20790 | 8071 | 0 | 0 |
T6 | 2450 | 1454 | 0 | 0 |
T7 | 2258 | 1405 | 0 | 0 |
T8 | 5744 | 5144 | 0 | 0 |
T9 | 223088 | 174793 | 0 | 0 |
T10 | 6067 | 5470 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 459 | 459 | 0 | 0 |
OutputsKnown_A | 9939486 | 5601763 | 0 | 0 |
gen_no_flops.OutputDelay_A | 9939486 | 5601763 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 459 | 459 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9939486 | 5601763 | 0 | 0 |
T1 | 1607 | 966 | 0 | 0 |
T2 | 2676 | 1668 | 0 | 0 |
T3 | 3781 | 2847 | 0 | 0 |
T4 | 10815 | 10240 | 0 | 0 |
T5 | 20790 | 8071 | 0 | 0 |
T6 | 2450 | 1454 | 0 | 0 |
T7 | 2258 | 1405 | 0 | 0 |
T8 | 5744 | 5144 | 0 | 0 |
T9 | 223088 | 174793 | 0 | 0 |
T10 | 6067 | 5470 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9939486 | 5601763 | 0 | 0 |
T1 | 1607 | 966 | 0 | 0 |
T2 | 2676 | 1668 | 0 | 0 |
T3 | 3781 | 2847 | 0 | 0 |
T4 | 10815 | 10240 | 0 | 0 |
T5 | 20790 | 8071 | 0 | 0 |
T6 | 2450 | 1454 | 0 | 0 |
T7 | 2258 | 1405 | 0 | 0 |
T8 | 5744 | 5144 | 0 | 0 |
T9 | 223088 | 174793 | 0 | 0 |
T10 | 6067 | 5470 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 459 | 459 | 0 | 0 |
OutputsKnown_A | 9939486 | 5601763 | 0 | 0 |
gen_no_flops.OutputDelay_A | 9939486 | 5601763 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 459 | 459 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9939486 | 5601763 | 0 | 0 |
T1 | 1607 | 966 | 0 | 0 |
T2 | 2676 | 1668 | 0 | 0 |
T3 | 3781 | 2847 | 0 | 0 |
T4 | 10815 | 10240 | 0 | 0 |
T5 | 20790 | 8071 | 0 | 0 |
T6 | 2450 | 1454 | 0 | 0 |
T7 | 2258 | 1405 | 0 | 0 |
T8 | 5744 | 5144 | 0 | 0 |
T9 | 223088 | 174793 | 0 | 0 |
T10 | 6067 | 5470 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9939486 | 5601763 | 0 | 0 |
T1 | 1607 | 966 | 0 | 0 |
T2 | 2676 | 1668 | 0 | 0 |
T3 | 3781 | 2847 | 0 | 0 |
T4 | 10815 | 10240 | 0 | 0 |
T5 | 20790 | 8071 | 0 | 0 |
T6 | 2450 | 1454 | 0 | 0 |
T7 | 2258 | 1405 | 0 | 0 |
T8 | 5744 | 5144 | 0 | 0 |
T9 | 223088 | 174793 | 0 | 0 |
T10 | 6067 | 5470 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 459 | 459 | 0 | 0 |
OutputsKnown_A | 9939486 | 5601763 | 0 | 0 |
gen_no_flops.OutputDelay_A | 9939486 | 5601763 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 459 | 459 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9939486 | 5601763 | 0 | 0 |
T1 | 1607 | 966 | 0 | 0 |
T2 | 2676 | 1668 | 0 | 0 |
T3 | 3781 | 2847 | 0 | 0 |
T4 | 10815 | 10240 | 0 | 0 |
T5 | 20790 | 8071 | 0 | 0 |
T6 | 2450 | 1454 | 0 | 0 |
T7 | 2258 | 1405 | 0 | 0 |
T8 | 5744 | 5144 | 0 | 0 |
T9 | 223088 | 174793 | 0 | 0 |
T10 | 6067 | 5470 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9939486 | 5601763 | 0 | 0 |
T1 | 1607 | 966 | 0 | 0 |
T2 | 2676 | 1668 | 0 | 0 |
T3 | 3781 | 2847 | 0 | 0 |
T4 | 10815 | 10240 | 0 | 0 |
T5 | 20790 | 8071 | 0 | 0 |
T6 | 2450 | 1454 | 0 | 0 |
T7 | 2258 | 1405 | 0 | 0 |
T8 | 5744 | 5144 | 0 | 0 |
T9 | 223088 | 174793 | 0 | 0 |
T10 | 6067 | 5470 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 459 | 459 | 0 | 0 |
OutputsKnown_A | 9939486 | 5601763 | 0 | 0 |
gen_no_flops.OutputDelay_A | 9939486 | 5601763 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 459 | 459 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9939486 | 5601763 | 0 | 0 |
T1 | 1607 | 966 | 0 | 0 |
T2 | 2676 | 1668 | 0 | 0 |
T3 | 3781 | 2847 | 0 | 0 |
T4 | 10815 | 10240 | 0 | 0 |
T5 | 20790 | 8071 | 0 | 0 |
T6 | 2450 | 1454 | 0 | 0 |
T7 | 2258 | 1405 | 0 | 0 |
T8 | 5744 | 5144 | 0 | 0 |
T9 | 223088 | 174793 | 0 | 0 |
T10 | 6067 | 5470 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9939486 | 5601763 | 0 | 0 |
T1 | 1607 | 966 | 0 | 0 |
T2 | 2676 | 1668 | 0 | 0 |
T3 | 3781 | 2847 | 0 | 0 |
T4 | 10815 | 10240 | 0 | 0 |
T5 | 20790 | 8071 | 0 | 0 |
T6 | 2450 | 1454 | 0 | 0 |
T7 | 2258 | 1405 | 0 | 0 |
T8 | 5744 | 5144 | 0 | 0 |
T9 | 223088 | 174793 | 0 | 0 |
T10 | 6067 | 5470 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 459 | 459 | 0 | 0 |
OutputsKnown_A | 9939486 | 5601763 | 0 | 0 |
gen_no_flops.OutputDelay_A | 9939486 | 5601763 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 459 | 459 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9939486 | 5601763 | 0 | 0 |
T1 | 1607 | 966 | 0 | 0 |
T2 | 2676 | 1668 | 0 | 0 |
T3 | 3781 | 2847 | 0 | 0 |
T4 | 10815 | 10240 | 0 | 0 |
T5 | 20790 | 8071 | 0 | 0 |
T6 | 2450 | 1454 | 0 | 0 |
T7 | 2258 | 1405 | 0 | 0 |
T8 | 5744 | 5144 | 0 | 0 |
T9 | 223088 | 174793 | 0 | 0 |
T10 | 6067 | 5470 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9939486 | 5601763 | 0 | 0 |
T1 | 1607 | 966 | 0 | 0 |
T2 | 2676 | 1668 | 0 | 0 |
T3 | 3781 | 2847 | 0 | 0 |
T4 | 10815 | 10240 | 0 | 0 |
T5 | 20790 | 8071 | 0 | 0 |
T6 | 2450 | 1454 | 0 | 0 |
T7 | 2258 | 1405 | 0 | 0 |
T8 | 5744 | 5144 | 0 | 0 |
T9 | 223088 | 174793 | 0 | 0 |
T10 | 6067 | 5470 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 459 | 459 | 0 | 0 |
OutputsKnown_A | 9939486 | 5601763 | 0 | 0 |
gen_no_flops.OutputDelay_A | 9939486 | 5601763 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 459 | 459 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9939486 | 5601763 | 0 | 0 |
T1 | 1607 | 966 | 0 | 0 |
T2 | 2676 | 1668 | 0 | 0 |
T3 | 3781 | 2847 | 0 | 0 |
T4 | 10815 | 10240 | 0 | 0 |
T5 | 20790 | 8071 | 0 | 0 |
T6 | 2450 | 1454 | 0 | 0 |
T7 | 2258 | 1405 | 0 | 0 |
T8 | 5744 | 5144 | 0 | 0 |
T9 | 223088 | 174793 | 0 | 0 |
T10 | 6067 | 5470 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9939486 | 5601763 | 0 | 0 |
T1 | 1607 | 966 | 0 | 0 |
T2 | 2676 | 1668 | 0 | 0 |
T3 | 3781 | 2847 | 0 | 0 |
T4 | 10815 | 10240 | 0 | 0 |
T5 | 20790 | 8071 | 0 | 0 |
T6 | 2450 | 1454 | 0 | 0 |
T7 | 2258 | 1405 | 0 | 0 |
T8 | 5744 | 5144 | 0 | 0 |
T9 | 223088 | 174793 | 0 | 0 |
T10 | 6067 | 5470 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 459 | 459 | 0 | 0 |
OutputsKnown_A | 9939486 | 5601763 | 0 | 0 |
gen_no_flops.OutputDelay_A | 9939486 | 5601763 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 459 | 459 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9939486 | 5601763 | 0 | 0 |
T1 | 1607 | 966 | 0 | 0 |
T2 | 2676 | 1668 | 0 | 0 |
T3 | 3781 | 2847 | 0 | 0 |
T4 | 10815 | 10240 | 0 | 0 |
T5 | 20790 | 8071 | 0 | 0 |
T6 | 2450 | 1454 | 0 | 0 |
T7 | 2258 | 1405 | 0 | 0 |
T8 | 5744 | 5144 | 0 | 0 |
T9 | 223088 | 174793 | 0 | 0 |
T10 | 6067 | 5470 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9939486 | 5601763 | 0 | 0 |
T1 | 1607 | 966 | 0 | 0 |
T2 | 2676 | 1668 | 0 | 0 |
T3 | 3781 | 2847 | 0 | 0 |
T4 | 10815 | 10240 | 0 | 0 |
T5 | 20790 | 8071 | 0 | 0 |
T6 | 2450 | 1454 | 0 | 0 |
T7 | 2258 | 1405 | 0 | 0 |
T8 | 5744 | 5144 | 0 | 0 |
T9 | 223088 | 174793 | 0 | 0 |
T10 | 6067 | 5470 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 459 | 459 | 0 | 0 |
OutputsKnown_A | 9939486 | 5601763 | 0 | 0 |
gen_no_flops.OutputDelay_A | 9939486 | 5601763 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 459 | 459 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9939486 | 5601763 | 0 | 0 |
T1 | 1607 | 966 | 0 | 0 |
T2 | 2676 | 1668 | 0 | 0 |
T3 | 3781 | 2847 | 0 | 0 |
T4 | 10815 | 10240 | 0 | 0 |
T5 | 20790 | 8071 | 0 | 0 |
T6 | 2450 | 1454 | 0 | 0 |
T7 | 2258 | 1405 | 0 | 0 |
T8 | 5744 | 5144 | 0 | 0 |
T9 | 223088 | 174793 | 0 | 0 |
T10 | 6067 | 5470 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9939486 | 5601763 | 0 | 0 |
T1 | 1607 | 966 | 0 | 0 |
T2 | 2676 | 1668 | 0 | 0 |
T3 | 3781 | 2847 | 0 | 0 |
T4 | 10815 | 10240 | 0 | 0 |
T5 | 20790 | 8071 | 0 | 0 |
T6 | 2450 | 1454 | 0 | 0 |
T7 | 2258 | 1405 | 0 | 0 |
T8 | 5744 | 5144 | 0 | 0 |
T9 | 223088 | 174793 | 0 | 0 |
T10 | 6067 | 5470 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 459 | 459 | 0 | 0 |
OutputsKnown_A | 9939486 | 5601763 | 0 | 0 |
gen_no_flops.OutputDelay_A | 9939486 | 5601763 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 459 | 459 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9939486 | 5601763 | 0 | 0 |
T1 | 1607 | 966 | 0 | 0 |
T2 | 2676 | 1668 | 0 | 0 |
T3 | 3781 | 2847 | 0 | 0 |
T4 | 10815 | 10240 | 0 | 0 |
T5 | 20790 | 8071 | 0 | 0 |
T6 | 2450 | 1454 | 0 | 0 |
T7 | 2258 | 1405 | 0 | 0 |
T8 | 5744 | 5144 | 0 | 0 |
T9 | 223088 | 174793 | 0 | 0 |
T10 | 6067 | 5470 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9939486 | 5601763 | 0 | 0 |
T1 | 1607 | 966 | 0 | 0 |
T2 | 2676 | 1668 | 0 | 0 |
T3 | 3781 | 2847 | 0 | 0 |
T4 | 10815 | 10240 | 0 | 0 |
T5 | 20790 | 8071 | 0 | 0 |
T6 | 2450 | 1454 | 0 | 0 |
T7 | 2258 | 1405 | 0 | 0 |
T8 | 5744 | 5144 | 0 | 0 |
T9 | 223088 | 174793 | 0 | 0 |
T10 | 6067 | 5470 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 459 | 459 | 0 | 0 |
OutputsKnown_A | 9939486 | 5601763 | 0 | 0 |
gen_no_flops.OutputDelay_A | 9939486 | 5601763 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 459 | 459 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9939486 | 5601763 | 0 | 0 |
T1 | 1607 | 966 | 0 | 0 |
T2 | 2676 | 1668 | 0 | 0 |
T3 | 3781 | 2847 | 0 | 0 |
T4 | 10815 | 10240 | 0 | 0 |
T5 | 20790 | 8071 | 0 | 0 |
T6 | 2450 | 1454 | 0 | 0 |
T7 | 2258 | 1405 | 0 | 0 |
T8 | 5744 | 5144 | 0 | 0 |
T9 | 223088 | 174793 | 0 | 0 |
T10 | 6067 | 5470 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9939486 | 5601763 | 0 | 0 |
T1 | 1607 | 966 | 0 | 0 |
T2 | 2676 | 1668 | 0 | 0 |
T3 | 3781 | 2847 | 0 | 0 |
T4 | 10815 | 10240 | 0 | 0 |
T5 | 20790 | 8071 | 0 | 0 |
T6 | 2450 | 1454 | 0 | 0 |
T7 | 2258 | 1405 | 0 | 0 |
T8 | 5744 | 5144 | 0 | 0 |
T9 | 223088 | 174793 | 0 | 0 |
T10 | 6067 | 5470 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |