Line Coverage for Module :
prim_generic_clock_mux2
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Module :
prim_generic_clock_mux2
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Module :
prim_generic_clock_mux2
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
1126881 |
1097505 |
0 |
0 |
selKnown1 |
145088 |
115712 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1126881 |
1097505 |
0 |
0 |
T2 |
348 |
285 |
0 |
0 |
T3 |
346 |
283 |
0 |
0 |
T4 |
122 |
59 |
0 |
0 |
T5 |
3304 |
3240 |
0 |
0 |
T6 |
354 |
290 |
0 |
0 |
T7 |
889 |
825 |
0 |
0 |
T8 |
99 |
35 |
0 |
0 |
T9 |
17668 |
17604 |
0 |
0 |
T10 |
97 |
33 |
0 |
0 |
T11 |
12 |
2427 |
0 |
0 |
T12 |
534 |
470 |
0 |
0 |
T13 |
27 |
4981 |
0 |
0 |
T14 |
0 |
216 |
0 |
0 |
T15 |
0 |
39 |
0 |
0 |
T16 |
8 |
414 |
0 |
0 |
T33 |
0 |
26 |
0 |
0 |
T43 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145088 |
115712 |
0 |
0 |
T2 |
128 |
64 |
0 |
0 |
T3 |
128 |
64 |
0 |
0 |
T4 |
64 |
0 |
0 |
0 |
T5 |
704 |
640 |
0 |
0 |
T6 |
128 |
64 |
0 |
0 |
T7 |
64 |
0 |
0 |
0 |
T8 |
64 |
0 |
0 |
0 |
T9 |
3200 |
3136 |
0 |
0 |
T10 |
64 |
0 |
0 |
0 |
T11 |
0 |
576 |
0 |
0 |
T12 |
64 |
0 |
0 |
0 |
T14 |
0 |
576 |
0 |
0 |
T15 |
0 |
1984 |
0 |
0 |
T42 |
0 |
64 |
0 |
0 |
T43 |
0 |
576 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
19080 |
18621 |
0 |
0 |
selKnown1 |
2267 |
1808 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19080 |
18621 |
0 |
0 |
T2 |
6 |
5 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
56 |
55 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
16 |
15 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
304 |
303 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
48 |
0 |
0 |
T12 |
8 |
7 |
0 |
0 |
T13 |
0 |
101 |
0 |
0 |
T16 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2267 |
1808 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
50 |
49 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
19080 |
18621 |
0 |
0 |
selKnown1 |
2267 |
1808 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19080 |
18621 |
0 |
0 |
T2 |
6 |
5 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
56 |
55 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
16 |
15 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
304 |
303 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
48 |
0 |
0 |
T12 |
8 |
7 |
0 |
0 |
T13 |
0 |
101 |
0 |
0 |
T16 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2267 |
1808 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
50 |
49 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
19080 |
18621 |
0 |
0 |
selKnown1 |
2267 |
1808 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19080 |
18621 |
0 |
0 |
T2 |
6 |
5 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
56 |
55 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
16 |
15 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
304 |
303 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
48 |
0 |
0 |
T12 |
8 |
7 |
0 |
0 |
T13 |
0 |
101 |
0 |
0 |
T16 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2267 |
1808 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
50 |
49 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
19080 |
18621 |
0 |
0 |
selKnown1 |
2267 |
1808 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19080 |
18621 |
0 |
0 |
T2 |
6 |
5 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
56 |
55 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
16 |
15 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
304 |
303 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
48 |
0 |
0 |
T12 |
8 |
7 |
0 |
0 |
T13 |
0 |
101 |
0 |
0 |
T16 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2267 |
1808 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
50 |
49 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
7847 |
7388 |
0 |
0 |
selKnown1 |
2267 |
1808 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7847 |
7388 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
26 |
25 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
104 |
103 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
20 |
0 |
0 |
T12 |
8 |
7 |
0 |
0 |
T13 |
0 |
26 |
0 |
0 |
T14 |
0 |
25 |
0 |
0 |
T16 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2267 |
1808 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
50 |
49 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
19127 |
18668 |
0 |
0 |
selKnown1 |
2267 |
1808 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19127 |
18668 |
0 |
0 |
T2 |
6 |
5 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
56 |
55 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
16 |
15 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
304 |
303 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
48 |
0 |
0 |
T12 |
9 |
8 |
0 |
0 |
T13 |
0 |
101 |
0 |
0 |
T16 |
0 |
8 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2267 |
1808 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
50 |
49 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
7847 |
7388 |
0 |
0 |
selKnown1 |
2267 |
1808 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7847 |
7388 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
26 |
25 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
104 |
103 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
20 |
0 |
0 |
T12 |
8 |
7 |
0 |
0 |
T13 |
0 |
26 |
0 |
0 |
T14 |
0 |
25 |
0 |
0 |
T16 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2267 |
1808 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
50 |
49 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
19127 |
18668 |
0 |
0 |
selKnown1 |
2267 |
1808 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19127 |
18668 |
0 |
0 |
T2 |
6 |
5 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
56 |
55 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
16 |
15 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
304 |
303 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
48 |
0 |
0 |
T12 |
9 |
8 |
0 |
0 |
T13 |
0 |
101 |
0 |
0 |
T16 |
0 |
8 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2267 |
1808 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
50 |
49 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
7847 |
7388 |
0 |
0 |
selKnown1 |
2267 |
1808 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7847 |
7388 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
26 |
25 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
104 |
103 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
20 |
0 |
0 |
T12 |
8 |
7 |
0 |
0 |
T13 |
0 |
26 |
0 |
0 |
T14 |
0 |
25 |
0 |
0 |
T16 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2267 |
1808 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
50 |
49 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
19127 |
18668 |
0 |
0 |
selKnown1 |
2267 |
1808 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19127 |
18668 |
0 |
0 |
T2 |
6 |
5 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
56 |
55 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
16 |
15 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
304 |
303 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
48 |
0 |
0 |
T12 |
9 |
8 |
0 |
0 |
T13 |
0 |
101 |
0 |
0 |
T16 |
0 |
8 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2267 |
1808 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
50 |
49 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
7847 |
7388 |
0 |
0 |
selKnown1 |
2267 |
1808 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7847 |
7388 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
26 |
25 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
104 |
103 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
20 |
0 |
0 |
T12 |
8 |
7 |
0 |
0 |
T13 |
0 |
26 |
0 |
0 |
T14 |
0 |
25 |
0 |
0 |
T16 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2267 |
1808 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
50 |
49 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
19127 |
18668 |
0 |
0 |
selKnown1 |
2267 |
1808 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19127 |
18668 |
0 |
0 |
T2 |
6 |
5 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
56 |
55 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
16 |
15 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
304 |
303 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
48 |
0 |
0 |
T12 |
9 |
8 |
0 |
0 |
T13 |
0 |
101 |
0 |
0 |
T16 |
0 |
8 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2267 |
1808 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
50 |
49 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
7847 |
7388 |
0 |
0 |
selKnown1 |
2267 |
1808 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7847 |
7388 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
26 |
25 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
104 |
103 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
20 |
0 |
0 |
T12 |
8 |
7 |
0 |
0 |
T13 |
0 |
26 |
0 |
0 |
T14 |
0 |
25 |
0 |
0 |
T16 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2267 |
1808 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
50 |
49 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
19127 |
18668 |
0 |
0 |
selKnown1 |
2267 |
1808 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19127 |
18668 |
0 |
0 |
T2 |
6 |
5 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
56 |
55 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
16 |
15 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
304 |
303 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
48 |
0 |
0 |
T12 |
9 |
8 |
0 |
0 |
T13 |
0 |
101 |
0 |
0 |
T16 |
0 |
8 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2267 |
1808 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
50 |
49 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
19080 |
18621 |
0 |
0 |
selKnown1 |
2267 |
1808 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19080 |
18621 |
0 |
0 |
T2 |
6 |
5 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
56 |
55 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
16 |
15 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
304 |
303 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
48 |
0 |
0 |
T12 |
8 |
7 |
0 |
0 |
T13 |
0 |
101 |
0 |
0 |
T16 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2267 |
1808 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
50 |
49 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
19127 |
18668 |
0 |
0 |
selKnown1 |
2267 |
1808 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19127 |
18668 |
0 |
0 |
T2 |
6 |
5 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
56 |
55 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
16 |
15 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
304 |
303 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
48 |
0 |
0 |
T12 |
9 |
8 |
0 |
0 |
T13 |
0 |
101 |
0 |
0 |
T16 |
0 |
8 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2267 |
1808 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
50 |
49 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
19080 |
18621 |
0 |
0 |
selKnown1 |
2267 |
1808 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19080 |
18621 |
0 |
0 |
T2 |
6 |
5 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
56 |
55 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
16 |
15 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
304 |
303 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
48 |
0 |
0 |
T12 |
8 |
7 |
0 |
0 |
T13 |
0 |
101 |
0 |
0 |
T16 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2267 |
1808 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
50 |
49 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
19127 |
18668 |
0 |
0 |
selKnown1 |
2267 |
1808 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19127 |
18668 |
0 |
0 |
T2 |
6 |
5 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
56 |
55 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
16 |
15 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
304 |
303 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
48 |
0 |
0 |
T12 |
9 |
8 |
0 |
0 |
T13 |
0 |
101 |
0 |
0 |
T16 |
0 |
8 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2267 |
1808 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
50 |
49 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
19080 |
18621 |
0 |
0 |
selKnown1 |
2267 |
1808 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19080 |
18621 |
0 |
0 |
T2 |
6 |
5 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
56 |
55 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
16 |
15 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
304 |
303 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
48 |
0 |
0 |
T12 |
8 |
7 |
0 |
0 |
T13 |
0 |
101 |
0 |
0 |
T16 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2267 |
1808 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
50 |
49 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
19127 |
18668 |
0 |
0 |
selKnown1 |
2267 |
1808 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19127 |
18668 |
0 |
0 |
T2 |
6 |
5 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
56 |
55 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
16 |
15 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
304 |
303 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
48 |
0 |
0 |
T12 |
9 |
8 |
0 |
0 |
T13 |
0 |
101 |
0 |
0 |
T16 |
0 |
8 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2267 |
1808 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
50 |
49 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
19080 |
18621 |
0 |
0 |
selKnown1 |
2267 |
1808 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19080 |
18621 |
0 |
0 |
T2 |
6 |
5 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
56 |
55 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
16 |
15 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
304 |
303 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
48 |
0 |
0 |
T12 |
8 |
7 |
0 |
0 |
T13 |
0 |
101 |
0 |
0 |
T16 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2267 |
1808 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
50 |
49 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
19127 |
18668 |
0 |
0 |
selKnown1 |
2267 |
1808 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19127 |
18668 |
0 |
0 |
T2 |
6 |
5 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
56 |
55 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
16 |
15 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
304 |
303 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
48 |
0 |
0 |
T12 |
9 |
8 |
0 |
0 |
T13 |
0 |
101 |
0 |
0 |
T16 |
0 |
8 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2267 |
1808 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
50 |
49 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
19080 |
18621 |
0 |
0 |
selKnown1 |
2267 |
1808 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19080 |
18621 |
0 |
0 |
T2 |
6 |
5 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
56 |
55 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
16 |
15 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
304 |
303 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
48 |
0 |
0 |
T12 |
8 |
7 |
0 |
0 |
T13 |
0 |
101 |
0 |
0 |
T16 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2267 |
1808 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
50 |
49 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
19017 |
18558 |
0 |
0 |
selKnown1 |
2267 |
1808 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19017 |
18558 |
0 |
0 |
T2 |
6 |
5 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
56 |
55 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
16 |
15 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
303 |
302 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
48 |
0 |
0 |
T12 |
7 |
6 |
0 |
0 |
T13 |
0 |
101 |
0 |
0 |
T16 |
0 |
6 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2267 |
1808 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
50 |
49 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
19080 |
18621 |
0 |
0 |
selKnown1 |
2267 |
1808 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19080 |
18621 |
0 |
0 |
T2 |
6 |
5 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
56 |
55 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
16 |
15 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
304 |
303 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
48 |
0 |
0 |
T12 |
8 |
7 |
0 |
0 |
T13 |
0 |
101 |
0 |
0 |
T16 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2267 |
1808 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
50 |
49 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
19127 |
18668 |
0 |
0 |
selKnown1 |
2267 |
1808 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19127 |
18668 |
0 |
0 |
T2 |
6 |
5 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
56 |
55 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
16 |
15 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
304 |
303 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
48 |
0 |
0 |
T12 |
9 |
8 |
0 |
0 |
T13 |
0 |
101 |
0 |
0 |
T16 |
0 |
8 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2267 |
1808 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
50 |
49 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
19080 |
18621 |
0 |
0 |
selKnown1 |
2267 |
1808 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19080 |
18621 |
0 |
0 |
T2 |
6 |
5 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
56 |
55 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
16 |
15 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
304 |
303 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
48 |
0 |
0 |
T12 |
8 |
7 |
0 |
0 |
T13 |
0 |
101 |
0 |
0 |
T16 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2267 |
1808 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
50 |
49 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
19127 |
18668 |
0 |
0 |
selKnown1 |
2267 |
1808 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19127 |
18668 |
0 |
0 |
T2 |
6 |
5 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
56 |
55 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
16 |
15 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
304 |
303 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
48 |
0 |
0 |
T12 |
9 |
8 |
0 |
0 |
T13 |
0 |
101 |
0 |
0 |
T16 |
0 |
8 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2267 |
1808 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
50 |
49 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
19080 |
18621 |
0 |
0 |
selKnown1 |
2267 |
1808 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19080 |
18621 |
0 |
0 |
T2 |
6 |
5 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
56 |
55 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
16 |
15 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
304 |
303 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
48 |
0 |
0 |
T12 |
8 |
7 |
0 |
0 |
T13 |
0 |
101 |
0 |
0 |
T16 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2267 |
1808 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
50 |
49 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
19127 |
18668 |
0 |
0 |
selKnown1 |
2267 |
1808 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19127 |
18668 |
0 |
0 |
T2 |
6 |
5 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
56 |
55 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
16 |
15 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
304 |
303 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
48 |
0 |
0 |
T12 |
9 |
8 |
0 |
0 |
T13 |
0 |
101 |
0 |
0 |
T16 |
0 |
8 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2267 |
1808 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
50 |
49 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
19080 |
18621 |
0 |
0 |
selKnown1 |
2267 |
1808 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19080 |
18621 |
0 |
0 |
T2 |
6 |
5 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
56 |
55 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
16 |
15 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
304 |
303 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
48 |
0 |
0 |
T12 |
8 |
7 |
0 |
0 |
T13 |
0 |
101 |
0 |
0 |
T16 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2267 |
1808 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
50 |
49 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
19127 |
18668 |
0 |
0 |
selKnown1 |
2267 |
1808 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19127 |
18668 |
0 |
0 |
T2 |
6 |
5 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
56 |
55 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
16 |
15 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
304 |
303 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
48 |
0 |
0 |
T12 |
9 |
8 |
0 |
0 |
T13 |
0 |
101 |
0 |
0 |
T16 |
0 |
8 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2267 |
1808 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
50 |
49 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
19080 |
18621 |
0 |
0 |
selKnown1 |
2267 |
1808 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19080 |
18621 |
0 |
0 |
T2 |
6 |
5 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
56 |
55 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
16 |
15 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
304 |
303 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
48 |
0 |
0 |
T12 |
8 |
7 |
0 |
0 |
T13 |
0 |
101 |
0 |
0 |
T16 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2267 |
1808 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
50 |
49 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
19080 |
18621 |
0 |
0 |
selKnown1 |
2267 |
1808 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19080 |
18621 |
0 |
0 |
T2 |
6 |
5 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
56 |
55 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
16 |
15 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
304 |
303 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
48 |
0 |
0 |
T12 |
8 |
7 |
0 |
0 |
T13 |
0 |
101 |
0 |
0 |
T16 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2267 |
1808 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
50 |
49 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
19080 |
18621 |
0 |
0 |
selKnown1 |
2267 |
1808 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19080 |
18621 |
0 |
0 |
T2 |
6 |
5 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
56 |
55 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
16 |
15 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
304 |
303 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
48 |
0 |
0 |
T12 |
8 |
7 |
0 |
0 |
T13 |
0 |
101 |
0 |
0 |
T16 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2267 |
1808 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
50 |
49 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
19080 |
18621 |
0 |
0 |
selKnown1 |
2267 |
1808 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19080 |
18621 |
0 |
0 |
T2 |
6 |
5 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
56 |
55 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
16 |
15 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
304 |
303 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
48 |
0 |
0 |
T12 |
8 |
7 |
0 |
0 |
T13 |
0 |
101 |
0 |
0 |
T16 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2267 |
1808 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
50 |
49 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
19080 |
18621 |
0 |
0 |
selKnown1 |
2267 |
1808 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19080 |
18621 |
0 |
0 |
T2 |
6 |
5 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
56 |
55 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
16 |
15 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
304 |
303 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
48 |
0 |
0 |
T12 |
8 |
7 |
0 |
0 |
T13 |
0 |
101 |
0 |
0 |
T16 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2267 |
1808 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
50 |
49 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
19127 |
18668 |
0 |
0 |
selKnown1 |
2267 |
1808 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19127 |
18668 |
0 |
0 |
T2 |
6 |
5 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
56 |
55 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
16 |
15 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
304 |
303 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
48 |
0 |
0 |
T12 |
9 |
8 |
0 |
0 |
T13 |
0 |
101 |
0 |
0 |
T16 |
0 |
8 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2267 |
1808 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
50 |
49 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
19080 |
18621 |
0 |
0 |
selKnown1 |
2267 |
1808 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19080 |
18621 |
0 |
0 |
T2 |
6 |
5 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
56 |
55 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
16 |
15 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
304 |
303 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
48 |
0 |
0 |
T12 |
8 |
7 |
0 |
0 |
T13 |
0 |
101 |
0 |
0 |
T16 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2267 |
1808 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
50 |
49 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
19127 |
18668 |
0 |
0 |
selKnown1 |
2267 |
1808 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19127 |
18668 |
0 |
0 |
T2 |
6 |
5 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
56 |
55 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
16 |
15 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
304 |
303 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
48 |
0 |
0 |
T12 |
9 |
8 |
0 |
0 |
T13 |
0 |
101 |
0 |
0 |
T16 |
0 |
8 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2267 |
1808 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
50 |
49 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
19080 |
18621 |
0 |
0 |
selKnown1 |
2267 |
1808 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19080 |
18621 |
0 |
0 |
T2 |
6 |
5 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
56 |
55 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
16 |
15 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
304 |
303 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
48 |
0 |
0 |
T12 |
8 |
7 |
0 |
0 |
T13 |
0 |
101 |
0 |
0 |
T16 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2267 |
1808 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
50 |
49 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
19127 |
18668 |
0 |
0 |
selKnown1 |
2267 |
1808 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19127 |
18668 |
0 |
0 |
T2 |
6 |
5 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
56 |
55 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
16 |
15 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
304 |
303 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
48 |
0 |
0 |
T12 |
9 |
8 |
0 |
0 |
T13 |
0 |
101 |
0 |
0 |
T16 |
0 |
8 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2267 |
1808 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
50 |
49 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
19080 |
18621 |
0 |
0 |
selKnown1 |
2267 |
1808 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19080 |
18621 |
0 |
0 |
T2 |
6 |
5 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
56 |
55 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
16 |
15 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
304 |
303 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
48 |
0 |
0 |
T12 |
8 |
7 |
0 |
0 |
T13 |
0 |
101 |
0 |
0 |
T16 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2267 |
1808 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
50 |
49 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
19127 |
18668 |
0 |
0 |
selKnown1 |
2267 |
1808 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19127 |
18668 |
0 |
0 |
T2 |
6 |
5 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
56 |
55 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
16 |
15 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
304 |
303 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
48 |
0 |
0 |
T12 |
9 |
8 |
0 |
0 |
T13 |
0 |
101 |
0 |
0 |
T16 |
0 |
8 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2267 |
1808 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
50 |
49 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
19777 |
19318 |
0 |
0 |
selKnown1 |
2267 |
1808 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19777 |
19318 |
0 |
0 |
T2 |
6 |
5 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
5 |
4 |
0 |
0 |
T5 |
56 |
55 |
0 |
0 |
T6 |
7 |
6 |
0 |
0 |
T7 |
16 |
15 |
0 |
0 |
T8 |
2 |
1 |
0 |
0 |
T9 |
313 |
312 |
0 |
0 |
T10 |
2 |
1 |
0 |
0 |
T12 |
8 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2267 |
1808 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
50 |
49 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
19127 |
18668 |
0 |
0 |
selKnown1 |
2267 |
1808 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19127 |
18668 |
0 |
0 |
T2 |
6 |
5 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
56 |
55 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
16 |
15 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
304 |
303 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
48 |
0 |
0 |
T12 |
9 |
8 |
0 |
0 |
T13 |
0 |
101 |
0 |
0 |
T16 |
0 |
8 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2267 |
1808 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
50 |
49 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
19810 |
19351 |
0 |
0 |
selKnown1 |
2267 |
1808 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19810 |
19351 |
0 |
0 |
T2 |
7 |
6 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
7 |
6 |
0 |
0 |
T5 |
56 |
55 |
0 |
0 |
T6 |
7 |
6 |
0 |
0 |
T7 |
16 |
15 |
0 |
0 |
T8 |
3 |
2 |
0 |
0 |
T9 |
313 |
312 |
0 |
0 |
T10 |
3 |
2 |
0 |
0 |
T12 |
8 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2267 |
1808 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
50 |
49 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
19127 |
18668 |
0 |
0 |
selKnown1 |
2267 |
1808 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19127 |
18668 |
0 |
0 |
T2 |
6 |
5 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
56 |
55 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
16 |
15 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
304 |
303 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
48 |
0 |
0 |
T12 |
9 |
8 |
0 |
0 |
T13 |
0 |
101 |
0 |
0 |
T16 |
0 |
8 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2267 |
1808 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
50 |
49 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
19829 |
19370 |
0 |
0 |
selKnown1 |
2267 |
1808 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19829 |
19370 |
0 |
0 |
T2 |
6 |
5 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
7 |
6 |
0 |
0 |
T5 |
56 |
55 |
0 |
0 |
T6 |
7 |
6 |
0 |
0 |
T7 |
16 |
15 |
0 |
0 |
T8 |
4 |
3 |
0 |
0 |
T9 |
312 |
311 |
0 |
0 |
T10 |
3 |
2 |
0 |
0 |
T12 |
8 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2267 |
1808 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
50 |
49 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
19127 |
18668 |
0 |
0 |
selKnown1 |
2267 |
1808 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19127 |
18668 |
0 |
0 |
T2 |
6 |
5 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
56 |
55 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
16 |
15 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
304 |
303 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
48 |
0 |
0 |
T12 |
9 |
8 |
0 |
0 |
T13 |
0 |
101 |
0 |
0 |
T16 |
0 |
8 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2267 |
1808 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
50 |
49 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
19913 |
19454 |
0 |
0 |
selKnown1 |
2267 |
1808 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19913 |
19454 |
0 |
0 |
T2 |
7 |
6 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
9 |
8 |
0 |
0 |
T5 |
56 |
55 |
0 |
0 |
T6 |
7 |
6 |
0 |
0 |
T7 |
16 |
15 |
0 |
0 |
T8 |
4 |
3 |
0 |
0 |
T9 |
311 |
310 |
0 |
0 |
T10 |
5 |
4 |
0 |
0 |
T12 |
8 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2267 |
1808 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
50 |
49 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
19127 |
18668 |
0 |
0 |
selKnown1 |
2267 |
1808 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19127 |
18668 |
0 |
0 |
T2 |
6 |
5 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
56 |
55 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
16 |
15 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
304 |
303 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
48 |
0 |
0 |
T12 |
9 |
8 |
0 |
0 |
T13 |
0 |
101 |
0 |
0 |
T16 |
0 |
8 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2267 |
1808 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
50 |
49 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
19966 |
19507 |
0 |
0 |
selKnown1 |
2267 |
1808 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19966 |
19507 |
0 |
0 |
T2 |
6 |
5 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
9 |
8 |
0 |
0 |
T5 |
56 |
55 |
0 |
0 |
T6 |
7 |
6 |
0 |
0 |
T7 |
16 |
15 |
0 |
0 |
T8 |
6 |
5 |
0 |
0 |
T9 |
313 |
312 |
0 |
0 |
T10 |
6 |
5 |
0 |
0 |
T12 |
8 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2267 |
1808 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
50 |
49 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
19017 |
18558 |
0 |
0 |
selKnown1 |
2267 |
1808 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19017 |
18558 |
0 |
0 |
T2 |
6 |
5 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
56 |
55 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
16 |
15 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
303 |
302 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
48 |
0 |
0 |
T12 |
7 |
6 |
0 |
0 |
T13 |
0 |
101 |
0 |
0 |
T16 |
0 |
6 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2267 |
1808 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
50 |
49 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
20005 |
19546 |
0 |
0 |
selKnown1 |
2267 |
1808 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
20005 |
19546 |
0 |
0 |
T2 |
6 |
5 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
10 |
9 |
0 |
0 |
T5 |
56 |
55 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
16 |
15 |
0 |
0 |
T8 |
7 |
6 |
0 |
0 |
T9 |
309 |
308 |
0 |
0 |
T10 |
7 |
6 |
0 |
0 |
T12 |
8 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2267 |
1808 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
50 |
49 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
19127 |
18668 |
0 |
0 |
selKnown1 |
2267 |
1808 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19127 |
18668 |
0 |
0 |
T2 |
6 |
5 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
56 |
55 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
16 |
15 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
304 |
303 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
48 |
0 |
0 |
T12 |
9 |
8 |
0 |
0 |
T13 |
0 |
101 |
0 |
0 |
T16 |
0 |
8 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2267 |
1808 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
50 |
49 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
20063 |
19604 |
0 |
0 |
selKnown1 |
2267 |
1808 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
20063 |
19604 |
0 |
0 |
T2 |
6 |
5 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
10 |
9 |
0 |
0 |
T5 |
56 |
55 |
0 |
0 |
T6 |
7 |
6 |
0 |
0 |
T7 |
16 |
15 |
0 |
0 |
T8 |
8 |
7 |
0 |
0 |
T9 |
314 |
313 |
0 |
0 |
T10 |
7 |
6 |
0 |
0 |
T12 |
8 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2267 |
1808 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
50 |
49 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
19127 |
18668 |
0 |
0 |
selKnown1 |
2267 |
1808 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19127 |
18668 |
0 |
0 |
T2 |
6 |
5 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
56 |
55 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
16 |
15 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
304 |
303 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
48 |
0 |
0 |
T12 |
9 |
8 |
0 |
0 |
T13 |
0 |
101 |
0 |
0 |
T16 |
0 |
8 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2267 |
1808 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
50 |
49 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
20094 |
19635 |
0 |
0 |
selKnown1 |
2267 |
1808 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
20094 |
19635 |
0 |
0 |
T2 |
6 |
5 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
10 |
9 |
0 |
0 |
T5 |
56 |
55 |
0 |
0 |
T6 |
7 |
6 |
0 |
0 |
T7 |
16 |
15 |
0 |
0 |
T8 |
9 |
8 |
0 |
0 |
T9 |
310 |
309 |
0 |
0 |
T10 |
8 |
7 |
0 |
0 |
T12 |
8 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2267 |
1808 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
50 |
49 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
19127 |
18668 |
0 |
0 |
selKnown1 |
2267 |
1808 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19127 |
18668 |
0 |
0 |
T2 |
6 |
5 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
56 |
55 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
16 |
15 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
304 |
303 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
48 |
0 |
0 |
T12 |
9 |
8 |
0 |
0 |
T13 |
0 |
101 |
0 |
0 |
T16 |
0 |
8 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2267 |
1808 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
50 |
49 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
6483 |
6024 |
0 |
0 |
selKnown1 |
2267 |
1808 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
6483 |
6024 |
0 |
0 |
T5 |
16 |
15 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
55 |
54 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
12 |
11 |
0 |
0 |
T12 |
8 |
7 |
0 |
0 |
T13 |
27 |
26 |
0 |
0 |
T14 |
0 |
16 |
0 |
0 |
T15 |
0 |
39 |
0 |
0 |
T16 |
8 |
7 |
0 |
0 |
T33 |
0 |
26 |
0 |
0 |
T43 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2267 |
1808 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
50 |
49 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
8250 |
7791 |
0 |
0 |
selKnown1 |
2267 |
1808 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8250 |
7791 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
26 |
25 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
104 |
103 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
20 |
0 |
0 |
T12 |
8 |
7 |
0 |
0 |
T13 |
0 |
26 |
0 |
0 |
T14 |
0 |
25 |
0 |
0 |
T16 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2267 |
1808 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
50 |
49 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
7847 |
7388 |
0 |
0 |
selKnown1 |
2267 |
1808 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7847 |
7388 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
26 |
25 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
104 |
103 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
20 |
0 |
0 |
T12 |
8 |
7 |
0 |
0 |
T13 |
0 |
26 |
0 |
0 |
T14 |
0 |
25 |
0 |
0 |
T16 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2267 |
1808 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
50 |
49 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T3,T5,T6 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
7847 |
7388 |
0 |
0 |
selKnown1 |
2267 |
1808 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7847 |
7388 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
26 |
25 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
104 |
103 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
20 |
0 |
0 |
T12 |
8 |
7 |
0 |
0 |
T13 |
0 |
26 |
0 |
0 |
T14 |
0 |
25 |
0 |
0 |
T16 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2267 |
1808 |
0 |
0 |
T2 |
2 |
1 |
0 |
0 |
T3 |
2 |
1 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T6 |
2 |
1 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
50 |
49 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
9 |
0 |
0 |