Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T7
1	0	Covered	T2,T3,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T6
1	0	Covered	T2,T3,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T8
1	0	Covered	T2,T3,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T6
1	0	Covered	T2,T3,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T8
1	0	Covered	T2,T3,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T8,T9
1	0	Covered	T2,T3,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T8
1	0	Covered	T2,T3,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T8
1	0	Covered	T2,T3,T5

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	11216477	11930	0	0
gen_assertions[0].RstEnOn_A	11216477	841	0	0
gen_assertions[0].RstNOff_A	11216477	11930	0	0
gen_assertions[0].RstNOn_A	11216477	841	0	0
gen_assertions[1].RstEnOff_A	44865238	10865	0	0
gen_assertions[1].RstEnOn_A	44865238	795	0	0
gen_assertions[1].RstNOff_A	44865238	10865	0	0
gen_assertions[1].RstNOn_A	44865238	795	0	0
gen_assertions[2].RstEnOff_A	22433383	10884	0	0
gen_assertions[2].RstEnOn_A	22433383	770	0	0
gen_assertions[2].RstNOff_A	22433383	10884	0	0
gen_assertions[2].RstNOn_A	22433383	770	0	0
gen_assertions[3].RstEnOff_A	22433485	10968	0	0
gen_assertions[3].RstEnOn_A	22433485	856	0	0
gen_assertions[3].RstNOff_A	22433485	10968	0	0
gen_assertions[3].RstNOn_A	22433485	856	0	0
gen_assertions[4].RstEnOff_A	1415728	18741	0	0
gen_assertions[4].RstEnOn_A	1415728	935	0	0
gen_assertions[4].RstNOff_A	1415728	18741	0	0
gen_assertions[4].RstNOn_A	1415728	935	0	0
gen_assertions[5].RstEnOff_A	11216477	12158	0	0
gen_assertions[5].RstEnOn_A	11216477	955	0	0
gen_assertions[5].RstNOff_A	11216477	12158	0	0
gen_assertions[5].RstNOn_A	11216477	955	0	0
gen_assertions[6].RstEnOff_A	11216477	12216	0	0
gen_assertions[6].RstEnOn_A	11216477	1013	0	0
gen_assertions[6].RstNOff_A	11216477	12216	0	0
gen_assertions[6].RstNOn_A	11216477	1013	0	0
gen_assertions[7].RstEnOff_A	11216477	12247	0	0
gen_assertions[7].RstEnOn_A	11216477	1035	0	0
gen_assertions[7].RstNOff_A	11216477	12247	0	0
gen_assertions[7].RstNOn_A	11216477	1035	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11216477	11930	0	0
T2	2820	4	0	0
T3	4166	4	0	0
T4	10904	4	0	0
T5	25320	30	0	0
T6	2739	5	0	0
T7	3139	15	0	0
T8	5811	1	0	0
T9	247746	209	0	0
T10	6134	1	0	0
T11	0	28	0	0
T12	5876	0	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11216477	841	0	0
T4	10904	4	0	0
T5	25320	0	0	0
T6	2739	1	0	0
T7	3139	9	0	0
T8	5811	1	0	0
T9	247746	9	0	0
T10	6134	1	0	0
T11	21949	0	0	0
T12	5876	0	0	0
T13	29221	0	0	0
T15	0	11	0	0
T42	0	1	0	0
T91	0	2	0	0
T92	0	1	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11216477	11930	0	0
T2	2820	4	0	0
T3	4166	4	0	0
T4	10904	4	0	0
T5	25320	30	0	0
T6	2739	5	0	0
T7	3139	15	0	0
T8	5811	1	0	0
T9	247746	209	0	0
T10	6134	1	0	0
T11	0	28	0	0
T12	5876	0	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11216477	841	0	0
T4	10904	4	0	0
T5	25320	0	0	0
T6	2739	1	0	0
T7	3139	9	0	0
T8	5811	1	0	0
T9	247746	9	0	0
T10	6134	1	0	0
T11	21949	0	0	0
T12	5876	0	0	0
T13	29221	0	0	0
T15	0	11	0	0
T42	0	1	0	0
T91	0	2	0	0
T92	0	1	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	44865238	10865	0	0
T2	11287	4	0	0
T3	16667	4	0	0
T4	43623	6	0	0
T5	101266	29	0	0
T6	10956	5	0	0
T7	12563	13	0	0
T8	23245	2	0	0
T9	991002	194	0	0
T10	24538	2	0	0
T11	0	25	0	0
T12	23526	0	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	44865238	795	0	0
T2	11287	1	0	0
T3	16667	0	0	0
T4	43623	6	0	0
T5	101266	0	0	0
T6	10956	1	0	0
T7	12563	2	0	0
T8	23245	2	0	0
T9	991002	10	0	0
T10	24538	2	0	0
T12	23526	0	0	0
T15	0	9	0	0
T92	0	2	0	0
T93	0	3	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	44865238	10865	0	0
T2	11287	4	0	0
T3	16667	4	0	0
T4	43623	6	0	0
T5	101266	29	0	0
T6	10956	5	0	0
T7	12563	13	0	0
T8	23245	2	0	0
T9	991002	194	0	0
T10	24538	2	0	0
T11	0	25	0	0
T12	23526	0	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	44865238	795	0	0
T2	11287	1	0	0
T3	16667	0	0	0
T4	43623	6	0	0
T5	101266	0	0	0
T6	10956	1	0	0
T7	12563	2	0	0
T8	23245	2	0	0
T9	991002	10	0	0
T10	24538	2	0	0
T12	23526	0	0	0
T15	0	9	0	0
T92	0	2	0	0
T93	0	3	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22433383	10884	0	0
T2	5644	3	0	0
T3	8332	4	0	0
T4	21812	6	0	0
T5	50653	29	0	0
T6	5480	5	0	0
T7	6280	13	0	0
T8	11623	3	0	0
T9	495474	193	0	0
T10	12270	2	0	0
T11	0	25	0	0
T12	11762	0	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22433383	770	0	0
T4	21812	6	0	0
T5	50653	0	0	0
T6	5480	1	0	0
T7	6280	0	0	0
T8	11623	3	0	0
T9	495474	8	0	0
T10	12270	2	0	0
T11	43901	0	0	0
T12	11762	0	0	0
T13	58424	0	0	0
T15	0	12	0	0
T92	0	4	0	0
T93	0	4	0	0
T94	0	21	0	0
T95	0	8	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22433383	10884	0	0
T2	5644	3	0	0
T3	8332	4	0	0
T4	21812	6	0	0
T5	50653	29	0	0
T6	5480	5	0	0
T7	6280	13	0	0
T8	11623	3	0	0
T9	495474	193	0	0
T10	12270	2	0	0
T11	0	25	0	0
T12	11762	0	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22433383	770	0	0
T4	21812	6	0	0
T5	50653	0	0	0
T6	5480	1	0	0
T7	6280	0	0	0
T8	11623	3	0	0
T9	495474	8	0	0
T10	12270	2	0	0
T11	43901	0	0	0
T12	11762	0	0	0
T13	58424	0	0	0
T15	0	12	0	0
T92	0	4	0	0
T93	0	4	0	0
T94	0	21	0	0
T95	0	8	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22433485	10968	0	0
T2	5646	4	0	0
T3	8332	4	0	0
T4	21812	8	0	0
T5	50642	29	0	0
T6	5483	5	0	0
T7	6280	13	0	0
T8	11622	3	0	0
T9	495498	192	0	0
T10	12269	4	0	0
T11	0	25	0	0
T12	11759	0	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22433485	856	0	0
T2	5646	1	0	0
T3	8332	0	0	0
T4	21812	8	0	0
T5	50642	0	0	0
T6	5483	1	0	0
T7	6280	0	0	0
T8	11622	3	0	0
T9	495498	7	0	0
T10	12269	4	0	0
T12	11759	0	0	0
T15	0	12	0	0
T92	0	5	0	0
T93	0	5	0	0
T94	0	26	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22433485	10968	0	0
T2	5646	4	0	0
T3	8332	4	0	0
T4	21812	8	0	0
T5	50642	29	0	0
T6	5483	5	0	0
T7	6280	13	0	0
T8	11622	3	0	0
T9	495498	192	0	0
T10	12269	4	0	0
T11	0	25	0	0
T12	11759	0	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22433485	856	0	0
T2	5646	1	0	0
T3	8332	0	0	0
T4	21812	8	0	0
T5	50642	0	0	0
T6	5483	1	0	0
T7	6280	0	0	0
T8	11622	3	0	0
T9	495498	7	0	0
T10	12269	4	0	0
T12	11759	0	0	0
T15	0	12	0	0
T92	0	5	0	0
T93	0	5	0	0
T94	0	26	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1415728	18741	0	0
T1	203	1	0	0
T2	352	6	0	0
T3	520	6	0	0
T4	1362	9	0	0
T5	3230	56	0	0
T6	341	7	0	0
T7	391	15	0	0
T8	725	6	0	0
T9	31358	312	0	0
T10	766	6	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1415728	935	0	0
T4	1362	8	0	0
T5	3230	0	0	0
T6	341	1	0	0
T7	391	0	0	0
T8	725	5	0	0
T9	31358	10	0	0
T10	766	5	0	0
T11	2775	0	0	0
T12	736	0	0	0
T13	3667	0	0	0
T15	0	14	0	0
T42	0	1	0	0
T92	0	6	0	0
T93	0	6	0	0
T94	0	23	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1415728	18741	0	0
T1	203	1	0	0
T2	352	6	0	0
T3	520	6	0	0
T4	1362	9	0	0
T5	3230	56	0	0
T6	341	7	0	0
T7	391	15	0	0
T8	725	6	0	0
T9	31358	312	0	0
T10	766	6	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1415728	935	0	0
T4	1362	8	0	0
T5	3230	0	0	0
T6	341	1	0	0
T7	391	0	0	0
T8	725	5	0	0
T9	31358	10	0	0
T10	766	5	0	0
T11	2775	0	0	0
T12	736	0	0	0
T13	3667	0	0	0
T15	0	14	0	0
T42	0	1	0	0
T92	0	6	0	0
T93	0	6	0	0
T94	0	23	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11216477	12158	0	0
T2	2820	4	0	0
T3	4166	4	0	0
T4	10904	9	0	0
T5	25320	30	0	0
T6	2739	4	0	0
T7	3139	15	0	0
T8	5811	6	0	0
T9	247746	205	0	0
T10	6134	6	0	0
T11	0	28	0	0
T12	5876	0	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11216477	955	0	0
T4	10904	9	0	0
T5	25320	0	0	0
T6	2739	0	0	0
T7	3139	0	0	0
T8	5811	6	0	0
T9	247746	5	0	0
T10	6134	6	0	0
T11	21949	0	0	0
T12	5876	0	0	0
T13	29221	0	0	0
T15	0	13	0	0
T92	0	7	0	0
T93	0	8	0	0
T94	0	28	0	0
T95	0	11	0	0
T96	0	10	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11216477	12158	0	0
T2	2820	4	0	0
T3	4166	4	0	0
T4	10904	9	0	0
T5	25320	30	0	0
T6	2739	4	0	0
T7	3139	15	0	0
T8	5811	6	0	0
T9	247746	205	0	0
T10	6134	6	0	0
T11	0	28	0	0
T12	5876	0	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11216477	955	0	0
T4	10904	9	0	0
T5	25320	0	0	0
T6	2739	0	0	0
T7	3139	0	0	0
T8	5811	6	0	0
T9	247746	5	0	0
T10	6134	6	0	0
T11	21949	0	0	0
T12	5876	0	0	0
T13	29221	0	0	0
T15	0	13	0	0
T92	0	7	0	0
T93	0	8	0	0
T94	0	28	0	0
T95	0	11	0	0
T96	0	10	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11216477	12216	0	0
T2	2820	4	0	0
T3	4166	4	0	0
T4	10904	9	0	0
T5	25320	30	0	0
T6	2739	5	0	0
T7	3139	15	0	0
T8	5811	7	0	0
T9	247746	210	0	0
T10	6134	6	0	0
T11	0	28	0	0
T12	5876	0	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11216477	1013	0	0
T4	10904	9	0	0
T5	25320	0	0	0
T6	2739	1	0	0
T7	3139	0	0	0
T8	5811	7	0	0
T9	247746	12	0	0
T10	6134	6	0	0
T11	21949	0	0	0
T12	5876	0	0	0
T13	29221	0	0	0
T15	0	12	0	0
T92	0	7	0	0
T93	0	9	0	0
T94	0	24	0	0
T95	0	8	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11216477	12216	0	0
T2	2820	4	0	0
T3	4166	4	0	0
T4	10904	9	0	0
T5	25320	30	0	0
T6	2739	5	0	0
T7	3139	15	0	0
T8	5811	7	0	0
T9	247746	210	0	0
T10	6134	6	0	0
T11	0	28	0	0
T12	5876	0	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11216477	1013	0	0
T4	10904	9	0	0
T5	25320	0	0	0
T6	2739	1	0	0
T7	3139	0	0	0
T8	5811	7	0	0
T9	247746	12	0	0
T10	6134	6	0	0
T11	21949	0	0	0
T12	5876	0	0	0
T13	29221	0	0	0
T15	0	12	0	0
T92	0	7	0	0
T93	0	9	0	0
T94	0	24	0	0
T95	0	8	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11216477	12247	0	0
T2	2820	4	0	0
T3	4166	4	0	0
T4	10904	9	0	0
T5	25320	30	0	0
T6	2739	5	0	0
T7	3139	15	0	0
T8	5811	8	0	0
T9	247746	206	0	0
T10	6134	7	0	0
T11	0	28	0	0
T12	5876	0	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11216477	1035	0	0
T4	10904	9	0	0
T5	25320	0	0	0
T6	2739	1	0	0
T7	3139	0	0	0
T8	5811	8	0	0
T9	247746	8	0	0
T10	6134	7	0	0
T11	21949	0	0	0
T12	5876	0	0	0
T13	29221	0	0	0
T15	0	11	0	0
T92	0	9	0	0
T93	0	8	0	0
T94	0	25	0	0
T95	0	13	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11216477	12247	0	0
T2	2820	4	0	0
T3	4166	4	0	0
T4	10904	9	0	0
T5	25320	30	0	0
T6	2739	5	0	0
T7	3139	15	0	0
T8	5811	8	0	0
T9	247746	206	0	0
T10	6134	7	0	0
T11	0	28	0	0
T12	5876	0	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11216477	1035	0	0
T4	10904	9	0	0
T5	25320	0	0	0
T6	2739	1	0	0
T7	3139	0	0	0
T8	5811	8	0	0
T9	247746	8	0	0
T10	6134	7	0	0
T11	21949	0	0	0
T12	5876	0	0	0
T13	29221	0	0	0
T15	0	11	0	0
T92	0	9	0	0
T93	0	8	0	0
T94	0	25	0	0
T95	0	13	0	0