SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_por |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_por_io |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_por_io_div2 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_por_io_div4 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_por_usb |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_lc |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc_shadowed |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_lc_shadowed |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc_aon |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc_io |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_lc_io |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc_io_div2 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_lc_io_div2 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_daon_lc_io_div4 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_d0_lc_io_div4 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_daon_lc_io_div4_shadowed |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_d0_lc_io_div4_shadowed |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc_usb |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_lc_usb |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_sys |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_sys_io_div4 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_spi_device |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_spi_host0 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_spi_host1 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_usb |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | u_d0_usb_aon |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_i2c0 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_i2c1 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_i2c2 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.55 | 100.00 | 98.21 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.55 | 100.00 | 98.21 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_flops.u_prim_flop | 100.00 | 100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 757174656 | 394843934 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 757174656 | 394843934 | 0 | 0 |
T1 | 109732 | 65907 | 0 | 0 |
T2 | 190512 | 116833 | 0 | 0 |
T3 | 281230 | 197813 | 0 | 0 |
T4 | 736134 | 676117 | 0 | 0 |
T5 | 1709496 | 601846 | 0 | 0 |
T6 | 184944 | 103458 | 0 | 0 |
T7 | 211956 | 113314 | 0 | 0 |
T8 | 392254 | 344549 | 0 | 0 |
T9 | 11150138 | 12088872 | 0 | 0 |
T10 | 414078 | 366358 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 46736425 | 27294830 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 46736425 | 27294830 | 0 | 0 |
T1 | 6776 | 4109 | 0 | 0 |
T2 | 11766 | 7805 | 0 | 0 |
T3 | 17361 | 13112 | 0 | 0 |
T4 | 45443 | 42750 | 0 | 0 |
T5 | 105522 | 46414 | 0 | 0 |
T6 | 11419 | 7314 | 0 | 0 |
T7 | 13085 | 10396 | 0 | 0 |
T8 | 24214 | 21517 | 0 | 0 |
T9 | 103225 | 804121 | 0 | 0 |
T10 | 25561 | 22875 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 44865238 | 26201867 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 44865238 | 26201867 | 0 | 0 |
T1 | 6503 | 3944 | 0 | 0 |
T2 | 11287 | 7486 | 0 | 0 |
T3 | 16667 | 12588 | 0 | 0 |
T4 | 43623 | 41038 | 0 | 0 |
T5 | 101266 | 44556 | 0 | 0 |
T6 | 10956 | 7014 | 0 | 0 |
T7 | 12563 | 9979 | 0 | 0 |
T8 | 23245 | 20656 | 0 | 0 |
T9 | 991002 | 771940 | 0 | 0 |
T10 | 24538 | 21960 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 22433383 | 13097587 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 22433383 | 13097587 | 0 | 0 |
T1 | 3252 | 1972 | 0 | 0 |
T2 | 5644 | 3743 | 0 | 0 |
T3 | 8332 | 6294 | 0 | 0 |
T4 | 21812 | 20519 | 0 | 0 |
T5 | 50653 | 22274 | 0 | 0 |
T6 | 5480 | 3508 | 0 | 0 |
T7 | 6280 | 4990 | 0 | 0 |
T8 | 11623 | 10328 | 0 | 0 |
T9 | 495474 | 385923 | 0 | 0 |
T10 | 12270 | 10980 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 11216477 | 6546037 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11216477 | 6546037 | 0 | 0 |
T1 | 1624 | 985 | 0 | 0 |
T2 | 2820 | 1871 | 0 | 0 |
T3 | 4166 | 3147 | 0 | 0 |
T4 | 10904 | 10259 | 0 | 0 |
T5 | 25320 | 11129 | 0 | 0 |
T6 | 2739 | 1753 | 0 | 0 |
T7 | 3139 | 2494 | 0 | 0 |
T8 | 5811 | 5163 | 0 | 0 |
T9 | 247746 | 192956 | 0 | 0 |
T10 | 6134 | 5489 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 22433485 | 13097623 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 22433485 | 13097623 | 0 | 0 |
T1 | 3251 | 1972 | 0 | 0 |
T2 | 5646 | 3746 | 0 | 0 |
T3 | 8332 | 6293 | 0 | 0 |
T4 | 21812 | 20519 | 0 | 0 |
T5 | 50642 | 22271 | 0 | 0 |
T6 | 5483 | 3511 | 0 | 0 |
T7 | 6280 | 4990 | 0 | 0 |
T8 | 11622 | 10328 | 0 | 0 |
T9 | 495498 | 385942 | 0 | 0 |
T10 | 12269 | 10980 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 46736425 | 24215454 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 46736425 | 24215454 | 0 | 0 |
T1 | 6776 | 4103 | 0 | 0 |
T2 | 11766 | 7205 | 0 | 0 |
T3 | 17361 | 12116 | 0 | 0 |
T4 | 45443 | 42745 | 0 | 0 |
T5 | 105522 | 36268 | 0 | 0 |
T6 | 11419 | 6310 | 0 | 0 |
T7 | 13085 | 6333 | 0 | 0 |
T8 | 24214 | 21510 | 0 | 0 |
T9 | 103225 | 740869 | 0 | 0 |
T10 | 25561 | 22869 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 46736425 | 23573403 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 46736425 | 23573403 | 0 | 0 |
T1 | 6776 | 4036 | 0 | 0 |
T2 | 11766 | 7039 | 0 | 0 |
T3 | 17361 | 11948 | 0 | 0 |
T4 | 45443 | 42678 | 0 | 0 |
T5 | 105522 | 34283 | 0 | 0 |
T6 | 11419 | 6142 | 0 | 0 |
T7 | 13085 | 6144 | 0 | 0 |
T8 | 24214 | 21443 | 0 | 0 |
T9 | 103225 | 732271 | 0 | 0 |
T10 | 25561 | 22803 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 46736425 | 24215730 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 46736425 | 24215730 | 0 | 0 |
T1 | 6776 | 4103 | 0 | 0 |
T2 | 11766 | 7205 | 0 | 0 |
T3 | 17361 | 12116 | 0 | 0 |
T4 | 45443 | 42745 | 0 | 0 |
T5 | 105522 | 36268 | 0 | 0 |
T6 | 11419 | 6310 | 0 | 0 |
T7 | 13085 | 6333 | 0 | 0 |
T8 | 24214 | 21510 | 0 | 0 |
T9 | 103225 | 740869 | 0 | 0 |
T10 | 25561 | 22869 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 46736425 | 23574909 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 46736425 | 23574909 | 0 | 0 |
T1 | 6776 | 4036 | 0 | 0 |
T2 | 11766 | 7039 | 0 | 0 |
T3 | 17361 | 11948 | 0 | 0 |
T4 | 45443 | 42678 | 0 | 0 |
T5 | 105522 | 34283 | 0 | 0 |
T6 | 11419 | 6142 | 0 | 0 |
T7 | 13085 | 6144 | 0 | 0 |
T8 | 24214 | 21443 | 0 | 0 |
T9 | 103225 | 732271 | 0 | 0 |
T10 | 25561 | 22803 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 1415728 | 717326 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1415728 | 717326 | 0 | 0 |
T1 | 203 | 122 | 0 | 0 |
T2 | 352 | 208 | 0 | 0 |
T3 | 520 | 357 | 0 | 0 |
T4 | 1362 | 1281 | 0 | 0 |
T5 | 3230 | 1082 | 0 | 0 |
T6 | 341 | 183 | 0 | 0 |
T7 | 391 | 174 | 0 | 0 |
T8 | 725 | 644 | 0 | 0 |
T9 | 31358 | 22257 | 0 | 0 |
T10 | 766 | 685 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 44865238 | 23247567 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 44865238 | 23247567 | 0 | 0 |
T1 | 6503 | 3938 | 0 | 0 |
T2 | 11287 | 6910 | 0 | 0 |
T3 | 16667 | 11630 | 0 | 0 |
T4 | 43623 | 41033 | 0 | 0 |
T5 | 101266 | 34813 | 0 | 0 |
T6 | 10956 | 6048 | 0 | 0 |
T7 | 12563 | 6077 | 0 | 0 |
T8 | 23245 | 20650 | 0 | 0 |
T9 | 991002 | 711213 | 0 | 0 |
T10 | 24538 | 21954 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 44865238 | 22629572 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 44865238 | 22629572 | 0 | 0 |
T1 | 6503 | 3874 | 0 | 0 |
T2 | 11287 | 6750 | 0 | 0 |
T3 | 16667 | 11470 | 0 | 0 |
T4 | 43623 | 40969 | 0 | 0 |
T5 | 101266 | 32909 | 0 | 0 |
T6 | 10956 | 5889 | 0 | 0 |
T7 | 12563 | 5893 | 0 | 0 |
T8 | 23245 | 20586 | 0 | 0 |
T9 | 991002 | 702957 | 0 | 0 |
T10 | 24538 | 21890 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 22433383 | 11615053 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 22433383 | 11615053 | 0 | 0 |
T1 | 3252 | 1969 | 0 | 0 |
T2 | 5644 | 3453 | 0 | 0 |
T3 | 8332 | 5812 | 0 | 0 |
T4 | 21812 | 20517 | 0 | 0 |
T5 | 50653 | 17385 | 0 | 0 |
T6 | 5480 | 3024 | 0 | 0 |
T7 | 6280 | 3031 | 0 | 0 |
T8 | 11623 | 10325 | 0 | 0 |
T9 | 495474 | 355457 | 0 | 0 |
T10 | 12270 | 10977 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 22433383 | 11305580 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 22433383 | 11305580 | 0 | 0 |
T1 | 3252 | 1937 | 0 | 0 |
T2 | 5644 | 3373 | 0 | 0 |
T3 | 8332 | 5732 | 0 | 0 |
T4 | 21812 | 20485 | 0 | 0 |
T5 | 50653 | 16433 | 0 | 0 |
T6 | 5480 | 2944 | 0 | 0 |
T7 | 6280 | 2939 | 0 | 0 |
T8 | 11623 | 10293 | 0 | 0 |
T9 | 495474 | 351329 | 0 | 0 |
T10 | 12270 | 10945 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 11216477 | 5783687 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11216477 | 5783687 | 0 | 0 |
T1 | 1624 | 983 | 0 | 0 |
T2 | 2820 | 1719 | 0 | 0 |
T3 | 4166 | 2899 | 0 | 0 |
T4 | 10904 | 10257 | 0 | 0 |
T5 | 25320 | 8621 | 0 | 0 |
T6 | 2739 | 1504 | 0 | 0 |
T7 | 3139 | 1492 | 0 | 0 |
T8 | 5811 | 5161 | 0 | 0 |
T9 | 247746 | 177375 | 0 | 0 |
T10 | 6134 | 5487 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 11216477 | 5629087 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11216477 | 5629087 | 0 | 0 |
T1 | 1624 | 967 | 0 | 0 |
T2 | 2820 | 1679 | 0 | 0 |
T3 | 4166 | 2859 | 0 | 0 |
T4 | 10904 | 10241 | 0 | 0 |
T5 | 25320 | 8145 | 0 | 0 |
T6 | 2739 | 1464 | 0 | 0 |
T7 | 3139 | 1446 | 0 | 0 |
T8 | 5811 | 5145 | 0 | 0 |
T9 | 247746 | 175311 | 0 | 0 |
T10 | 6134 | 5471 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 11216477 | 5783687 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11216477 | 5783687 | 0 | 0 |
T1 | 1624 | 983 | 0 | 0 |
T2 | 2820 | 1719 | 0 | 0 |
T3 | 4166 | 2899 | 0 | 0 |
T4 | 10904 | 10257 | 0 | 0 |
T5 | 25320 | 8621 | 0 | 0 |
T6 | 2739 | 1504 | 0 | 0 |
T7 | 3139 | 1492 | 0 | 0 |
T8 | 5811 | 5161 | 0 | 0 |
T9 | 247746 | 177375 | 0 | 0 |
T10 | 6134 | 5487 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 11216477 | 5629087 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11216477 | 5629087 | 0 | 0 |
T1 | 1624 | 967 | 0 | 0 |
T2 | 2820 | 1679 | 0 | 0 |
T3 | 4166 | 2859 | 0 | 0 |
T4 | 10904 | 10241 | 0 | 0 |
T5 | 25320 | 8145 | 0 | 0 |
T6 | 2739 | 1464 | 0 | 0 |
T7 | 3139 | 1446 | 0 | 0 |
T8 | 5811 | 5145 | 0 | 0 |
T9 | 247746 | 175311 | 0 | 0 |
T10 | 6134 | 5471 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 22433485 | 11615132 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 22433485 | 11615132 | 0 | 0 |
T1 | 3251 | 1969 | 0 | 0 |
T2 | 5646 | 3456 | 0 | 0 |
T3 | 8332 | 5811 | 0 | 0 |
T4 | 21812 | 20517 | 0 | 0 |
T5 | 50642 | 17382 | 0 | 0 |
T6 | 5483 | 3027 | 0 | 0 |
T7 | 6280 | 3031 | 0 | 0 |
T8 | 11622 | 10325 | 0 | 0 |
T9 | 495498 | 355476 | 0 | 0 |
T10 | 12269 | 10977 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 22433485 | 11305647 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 22433485 | 11305647 | 0 | 0 |
T1 | 3251 | 1937 | 0 | 0 |
T2 | 5646 | 3376 | 0 | 0 |
T3 | 8332 | 5731 | 0 | 0 |
T4 | 21812 | 20485 | 0 | 0 |
T5 | 50642 | 16430 | 0 | 0 |
T6 | 5483 | 2947 | 0 | 0 |
T7 | 6280 | 2939 | 0 | 0 |
T8 | 11622 | 10293 | 0 | 0 |
T9 | 495498 | 351348 | 0 | 0 |
T10 | 12269 | 10945 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 46736425 | 23317074 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 46736425 | 23317074 | 0 | 0 |
T1 | 6776 | 4036 | 0 | 0 |
T2 | 11766 | 6960 | 0 | 0 |
T3 | 17361 | 11818 | 0 | 0 |
T4 | 45443 | 42678 | 0 | 0 |
T5 | 105522 | 33460 | 0 | 0 |
T6 | 11419 | 6022 | 0 | 0 |
T7 | 13085 | 5864 | 0 | 0 |
T8 | 24214 | 21443 | 0 | 0 |
T9 | 103225 | 727660 | 0 | 0 |
T10 | 25561 | 22803 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 11216477 | 5722263 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11216477 | 5722263 | 0 | 0 |
T1 | 1624 | 983 | 0 | 0 |
T2 | 2820 | 1700 | 0 | 0 |
T3 | 4166 | 2868 | 0 | 0 |
T4 | 10904 | 10257 | 0 | 0 |
T5 | 25320 | 8423 | 0 | 0 |
T6 | 2739 | 1475 | 0 | 0 |
T7 | 3139 | 1425 | 0 | 0 |
T8 | 5811 | 5161 | 0 | 0 |
T9 | 247746 | 176270 | 0 | 0 |
T10 | 6134 | 5487 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 11216477 | 5513579 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11216477 | 5513579 | 0 | 0 |
T1 | 1624 | 967 | 0 | 0 |
T2 | 2820 | 1679 | 0 | 0 |
T3 | 4166 | 2859 | 0 | 0 |
T4 | 10904 | 9388 | 0 | 0 |
T5 | 25320 | 8145 | 0 | 0 |
T6 | 2739 | 1433 | 0 | 0 |
T7 | 3139 | 1396 | 0 | 0 |
T8 | 5811 | 5029 | 0 | 0 |
T9 | 247746 | 172808 | 0 | 0 |
T10 | 6134 | 5354 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 44865238 | 22172269 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 44865238 | 22172269 | 0 | 0 |
T1 | 6503 | 3874 | 0 | 0 |
T2 | 11287 | 6630 | 0 | 0 |
T3 | 16667 | 11470 | 0 | 0 |
T4 | 43623 | 34960 | 0 | 0 |
T5 | 101266 | 32909 | 0 | 0 |
T6 | 10956 | 5770 | 0 | 0 |
T7 | 12563 | 5860 | 0 | 0 |
T8 | 23245 | 19780 | 0 | 0 |
T9 | 991002 | 689285 | 0 | 0 |
T10 | 24538 | 21062 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 22433383 | 11090005 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 22433383 | 11090005 | 0 | 0 |
T1 | 3252 | 1937 | 0 | 0 |
T2 | 5644 | 3373 | 0 | 0 |
T3 | 8332 | 5732 | 0 | 0 |
T4 | 21812 | 17984 | 0 | 0 |
T5 | 50653 | 16433 | 0 | 0 |
T6 | 5480 | 2889 | 0 | 0 |
T7 | 6280 | 2939 | 0 | 0 |
T8 | 11623 | 9735 | 0 | 0 |
T9 | 495474 | 347213 | 0 | 0 |
T10 | 12270 | 10549 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 22433485 | 11076614 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 22433485 | 11076614 | 0 | 0 |
T1 | 3251 | 1937 | 0 | 0 |
T2 | 5646 | 3324 | 0 | 0 |
T3 | 8332 | 5731 | 0 | 0 |
T4 | 21812 | 17887 | 0 | 0 |
T5 | 50642 | 16430 | 0 | 0 |
T6 | 5483 | 2896 | 0 | 0 |
T7 | 6280 | 2939 | 0 | 0 |
T8 | 11622 | 9817 | 0 | 0 |
T9 | 495498 | 345865 | 0 | 0 |
T10 | 12269 | 10197 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 1415728 | 682191 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1415728 | 682191 | 0 | 0 |
T1 | 203 | 120 | 0 | 0 |
T2 | 352 | 203 | 0 | 0 |
T3 | 520 | 353 | 0 | 0 |
T4 | 1362 | 1118 | 0 | 0 |
T5 | 3230 | 1023 | 0 | 0 |
T6 | 341 | 177 | 0 | 0 |
T7 | 391 | 168 | 0 | 0 |
T8 | 725 | 593 | 0 | 0 |
T9 | 31358 | 21657 | 0 | 0 |
T10 | 766 | 625 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 11216477 | 5508764 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11216477 | 5508764 | 0 | 0 |
T1 | 1624 | 967 | 0 | 0 |
T2 | 2820 | 1679 | 0 | 0 |
T3 | 4166 | 2859 | 0 | 0 |
T4 | 10904 | 8853 | 0 | 0 |
T5 | 25320 | 8145 | 0 | 0 |
T6 | 2739 | 1464 | 0 | 0 |
T7 | 3139 | 1446 | 0 | 0 |
T8 | 5811 | 4714 | 0 | 0 |
T9 | 247746 | 174441 | 0 | 0 |
T10 | 6134 | 4966 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 11216477 | 5508299 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11216477 | 5508299 | 0 | 0 |
T1 | 1624 | 967 | 0 | 0 |
T2 | 2820 | 1679 | 0 | 0 |
T3 | 4166 | 2859 | 0 | 0 |
T4 | 10904 | 9030 | 0 | 0 |
T5 | 25320 | 8145 | 0 | 0 |
T6 | 2739 | 1445 | 0 | 0 |
T7 | 3139 | 1446 | 0 | 0 |
T8 | 5811 | 4702 | 0 | 0 |
T9 | 247746 | 170181 | 0 | 0 |
T10 | 6134 | 5024 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 11216477 | 5520962 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11216477 | 5520962 | 0 | 0 |
T1 | 1624 | 967 | 0 | 0 |
T2 | 2820 | 1679 | 0 | 0 |
T3 | 4166 | 2859 | 0 | 0 |
T4 | 10904 | 9184 | 0 | 0 |
T5 | 25320 | 8145 | 0 | 0 |
T6 | 2739 | 1447 | 0 | 0 |
T7 | 3139 | 1446 | 0 | 0 |
T8 | 5811 | 4659 | 0 | 0 |
T9 | 247746 | 172045 | 0 | 0 |
T10 | 6134 | 5002 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 1415728 | 834783 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1415728 | 834783 | 0 | 0 |
T1 | 203 | 124 | 0 | 0 |
T2 | 352 | 235 | 0 | 0 |
T3 | 520 | 394 | 0 | 0 |
T4 | 1362 | 1283 | 0 | 0 |
T5 | 3230 | 1464 | 0 | 0 |
T6 | 341 | 221 | 0 | 0 |
T7 | 391 | 312 | 0 | 0 |
T8 | 725 | 646 | 0 | 0 |
T9 | 31358 | 24542 | 0 | 0 |
T10 | 766 | 687 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 34 | 0 | 0 | |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
34 | unreachable | ||
82 | 1 | 1 | |
85 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A | 1415728 | 818266 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1415728 | 818266 | 0 | 0 |
T1 | 203 | 122 | 0 | 0 |
T2 | 352 | 231 | 0 | 0 |
T3 | 520 | 390 | 0 | 0 |
T4 | 1362 | 1281 | 0 | 0 |
T5 | 3230 | 1412 | 0 | 0 |
T6 | 341 | 217 | 0 | 0 |
T7 | 391 | 310 | 0 | 0 |
T8 | 725 | 644 | 0 | 0 |
T9 | 31358 | 24334 | 0 | 0 |
T10 | 766 | 685 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |