Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	10600833	7769	0	0
alert_regwen_rd_A	10600833	4653	0	0
cpu_regwen_rd_A	10600833	4543	0	0
sw_rst_ctrl_n_0_rd_A	10600833	8145	0	0
sw_rst_ctrl_n_1_rd_A	10600833	8391	0	0
sw_rst_ctrl_n_2_rd_A	10600833	8379	0	0
sw_rst_ctrl_n_3_rd_A	10600833	8488	0	0
sw_rst_ctrl_n_4_rd_A	10600833	8390	0	0
sw_rst_ctrl_n_5_rd_A	10600833	8523	0	0
sw_rst_ctrl_n_6_rd_A	10600833	8364	0	0
sw_rst_ctrl_n_7_rd_A	10600833	8412	0	0
sw_rst_regwen_0_rd_A	10600833	5079	0	0
sw_rst_regwen_1_rd_A	10600833	5204	0	0
sw_rst_regwen_2_rd_A	10600833	5238	0	0
sw_rst_regwen_3_rd_A	10600833	4952	0	0
sw_rst_regwen_4_rd_A	10600833	5123	0	0
sw_rst_regwen_5_rd_A	10600833	5102	0	0
sw_rst_regwen_6_rd_A	10600833	4994	0	0
sw_rst_regwen_7_rd_A	10600833	4981	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10600833	7769	0	0
T73	19578	4	0	0
T74	12142	737	0	0
T75	11308	2	0	0
T76	20094	1	0	0
T77	2548	233	0	0
T78	2552	47	0	0
T98	20018	2	0	0
T99	0	2	0	0
T104	1480	0	0	0
T105	11285	3	0	0
T106	1855	0	0	0
T125	0	2	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10600833	4653	0	0
T9	223088	358	0	0
T10	6067	0	0	0
T11	17137	0	0	0
T12	5526	0	0	0
T13	25837	0	0	0
T14	21010	0	0	0
T15	143411	214	0	0
T16	5083	0	0	0
T42	5960	0	0	0
T43	31850	70	0	0
T72	0	13	0	0
T75	0	40	0	0
T94	0	220	0	0
T105	0	12	0	0
T109	0	432	0	0
T110	0	4	0	0
T114	0	4	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10600833	4543	0	0
T9	223088	334	0	0
T10	6067	0	0	0
T11	17137	0	0	0
T12	5526	0	0	0
T13	25837	0	0	0
T14	21010	0	0	0
T15	143411	188	0	0
T16	5083	0	0	0
T42	5960	0	0	0
T43	31850	66	0	0
T75	0	30	0	0
T94	0	176	0	0
T105	0	33	0	0
T109	0	486	0	0
T110	0	4	0	0
T112	0	229	0	0
T114	0	6	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10600833	8145	0	0
T4	10815	175	0	0
T5	20790	0	0	0
T6	2450	0	0	0
T7	2258	0	0	0
T8	5744	0	0	0
T9	223088	430	0	0
T10	6067	0	0	0
T11	17137	0	0	0
T12	5526	0	0	0
T13	25837	0	0	0
T15	0	338	0	0
T42	0	8	0	0
T43	0	51	0	0
T92	0	109	0	0
T94	0	629	0	0
T96	0	258	0	0
T126	0	14	0	0
T127	0	47	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10600833	8391	0	0
T4	10815	169	0	0
T5	20790	0	0	0
T6	2450	0	0	0
T7	2258	0	0	0
T8	5744	0	0	0
T9	223088	482	0	0
T10	6067	0	0	0
T11	17137	0	0	0
T12	5526	0	0	0
T13	25837	0	0	0
T15	0	371	0	0
T42	0	22	0	0
T43	0	58	0	0
T92	0	142	0	0
T94	0	567	0	0
T96	0	172	0	0
T126	0	2	0	0
T127	0	40	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10600833	8379	0	0
T4	10815	168	0	0
T5	20790	0	0	0
T6	2450	0	0	0
T7	2258	0	0	0
T8	5744	0	0	0
T9	223088	451	0	0
T10	6067	0	0	0
T11	17137	0	0	0
T12	5526	0	0	0
T13	25837	0	0	0
T15	0	355	0	0
T42	0	16	0	0
T43	0	52	0	0
T92	0	127	0	0
T94	0	547	0	0
T96	0	237	0	0
T126	0	11	0	0
T127	0	81	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10600833	8488	0	0
T4	10815	181	0	0
T5	20790	0	0	0
T6	2450	0	0	0
T7	2258	0	0	0
T8	5744	0	0	0
T9	223088	438	0	0
T10	6067	0	0	0
T11	17137	0	0	0
T12	5526	0	0	0
T13	25837	0	0	0
T15	0	355	0	0
T42	0	12	0	0
T43	0	85	0	0
T92	0	124	0	0
T94	0	497	0	0
T96	0	230	0	0
T126	0	19	0	0
T127	0	79	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10600833	8390	0	0
T4	10815	145	0	0
T5	20790	0	0	0
T6	2450	0	0	0
T7	2258	0	0	0
T8	5744	0	0	0
T9	223088	427	0	0
T10	6067	0	0	0
T11	17137	0	0	0
T12	5526	0	0	0
T13	25837	0	0	0
T15	0	388	0	0
T42	0	27	0	0
T43	0	66	0	0
T92	0	153	0	0
T94	0	550	0	0
T96	0	226	0	0
T126	0	8	0	0
T127	0	59	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10600833	8523	0	0
T4	10815	165	0	0
T5	20790	0	0	0
T6	2450	0	0	0
T7	2258	0	0	0
T8	5744	0	0	0
T9	223088	467	0	0
T10	6067	0	0	0
T11	17137	0	0	0
T12	5526	0	0	0
T13	25837	0	0	0
T15	0	386	0	0
T42	0	16	0	0
T43	0	35	0	0
T92	0	118	0	0
T94	0	574	0	0
T96	0	167	0	0
T126	0	14	0	0
T127	0	75	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10600833	8364	0	0
T4	10815	173	0	0
T5	20790	0	0	0
T6	2450	0	0	0
T7	2258	0	0	0
T8	5744	0	0	0
T9	223088	418	0	0
T10	6067	0	0	0
T11	17137	0	0	0
T12	5526	0	0	0
T13	25837	0	0	0
T15	0	376	0	0
T42	0	21	0	0
T43	0	40	0	0
T92	0	122	0	0
T94	0	548	0	0
T96	0	239	0	0
T126	0	4	0	0
T127	0	76	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10600833	8412	0	0
T4	10815	175	0	0
T5	20790	0	0	0
T6	2450	0	0	0
T7	2258	0	0	0
T8	5744	0	0	0
T9	223088	462	0	0
T10	6067	0	0	0
T11	17137	0	0	0
T12	5526	0	0	0
T13	25837	0	0	0
T15	0	350	0	0
T42	0	8	0	0
T43	0	59	0	0
T92	0	129	0	0
T94	0	512	0	0
T96	0	171	0	0
T126	0	7	0	0
T127	0	76	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10600833	5079	0	0
T4	10815	26	0	0
T5	20790	0	0	0
T6	2450	0	0	0
T7	2258	0	0	0
T8	5744	0	0	0
T9	223088	293	0	0
T10	6067	0	0	0
T11	17137	0	0	0
T12	5526	0	0	0
T13	25837	0	0	0
T15	0	224	0	0
T42	0	5	0	0
T43	0	50	0	0
T72	0	16	0	0
T75	0	30	0	0
T92	0	27	0	0
T94	0	206	0	0
T96	0	46	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10600833	5204	0	0
T4	10815	42	0	0
T5	20790	0	0	0
T6	2450	0	0	0
T7	2258	0	0	0
T8	5744	0	0	0
T9	223088	365	0	0
T10	6067	0	0	0
T11	17137	0	0	0
T12	5526	0	0	0
T13	25837	0	0	0
T15	0	220	0	0
T42	0	5	0	0
T43	0	66	0	0
T72	0	4	0	0
T75	0	27	0	0
T92	0	22	0	0
T94	0	221	0	0
T96	0	39	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10600833	5238	0	0
T4	10815	18	0	0
T5	20790	0	0	0
T6	2450	0	0	0
T7	2258	0	0	0
T8	5744	0	0	0
T9	223088	337	0	0
T10	6067	0	0	0
T11	17137	0	0	0
T12	5526	0	0	0
T13	25837	0	0	0
T15	0	232	0	0
T43	0	57	0	0
T72	0	3	0	0
T75	0	60	0	0
T92	0	31	0	0
T94	0	237	0	0
T96	0	23	0	0
T105	0	28	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10600833	4952	0	0
T4	10815	22	0	0
T5	20790	0	0	0
T6	2450	0	0	0
T7	2258	0	0	0
T8	5744	0	0	0
T9	223088	331	0	0
T10	6067	0	0	0
T11	17137	0	0	0
T12	5526	0	0	0
T13	25837	0	0	0
T15	0	203	0	0
T42	0	7	0	0
T43	0	48	0	0
T72	0	13	0	0
T75	0	37	0	0
T92	0	41	0	0
T94	0	220	0	0
T96	0	23	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10600833	5123	0	0
T4	10815	34	0	0
T5	20790	0	0	0
T6	2450	0	0	0
T7	2258	0	0	0
T8	5744	0	0	0
T9	223088	304	0	0
T10	6067	0	0	0
T11	17137	0	0	0
T12	5526	0	0	0
T13	25837	0	0	0
T15	0	253	0	0
T42	0	1	0	0
T43	0	79	0	0
T72	0	15	0	0
T75	0	51	0	0
T92	0	31	0	0
T94	0	153	0	0
T96	0	11	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10600833	5102	0	0
T4	10815	31	0	0
T5	20790	0	0	0
T6	2450	0	0	0
T7	2258	0	0	0
T8	5744	0	0	0
T9	223088	349	0	0
T10	6067	0	0	0
T11	17137	0	0	0
T12	5526	0	0	0
T13	25837	0	0	0
T15	0	202	0	0
T42	0	9	0	0
T43	0	53	0	0
T72	0	8	0	0
T75	0	55	0	0
T92	0	31	0	0
T94	0	222	0	0
T96	0	42	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10600833	4994	0	0
T4	10815	41	0	0
T5	20790	0	0	0
T6	2450	0	0	0
T7	2258	0	0	0
T8	5744	0	0	0
T9	223088	294	0	0
T10	6067	0	0	0
T11	17137	0	0	0
T12	5526	0	0	0
T13	25837	0	0	0
T15	0	218	0	0
T43	0	64	0	0
T72	0	10	0	0
T75	0	33	0	0
T92	0	34	0	0
T94	0	195	0	0
T96	0	34	0	0
T105	0	24	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10600833	4981	0	0
T4	10815	22	0	0
T5	20790	0	0	0
T6	2450	0	0	0
T7	2258	0	0	0
T8	5744	0	0	0
T9	223088	318	0	0
T10	6067	0	0	0
T11	17137	0	0	0
T12	5526	0	0	0
T13	25837	0	0	0
T15	0	211	0	0
T42	0	5	0	0
T43	0	66	0	0
T72	0	2	0	0
T75	0	51	0	0
T92	0	37	0	0
T94	0	196	0	0
T96	0	24	0	0