Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T2,T3,T5

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	9939486	11233	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	9939486	103705	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	9939486	5637168	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	9939486	165294	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	9939486	11233	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	9939486	103705	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	9939486	5637168	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	9939486	165294	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9939486	11233	0	0
T2	2676	4	0	0
T3	3781	4	0	0
T4	10815	0	0	0
T5	20790	30	0	0
T6	2450	4	0	0
T7	2258	15	0	0
T8	5744	0	0	0
T9	223088	200	0	0
T10	6067	0	0	0
T11	0	28	0	0
T12	5526	0	0	0
T13	0	75	0	0
T14	0	37	0	0
T15	0	113	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9939486	103705	0	0
T2	2676	37	0	0
T3	3781	37	0	0
T4	10815	0	0	0
T5	20790	275	0	0
T6	2450	37	0	0
T7	2258	135	0	0
T8	5744	0	0	0
T9	223088	1806	0	0
T10	6067	0	0	0
T11	0	255	0	0
T12	5526	0	0	0
T13	0	702	0	0
T14	0	334	0	0
T15	0	1023	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9939486	5637168	0	0
T1	1607	970	0	0
T2	2676	1681	0	0
T3	3781	2848	0	0
T4	10815	10244	0	0
T5	20790	8142	0	0
T6	2450	1458	0	0
T7	2258	1438	0	0
T8	5744	5148	0	0
T9	223088	175276	0	0
T10	6067	5474	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9939486	165294	0	0
T2	2676	56	0	0
T3	3781	68	0	0
T4	10815	0	0	0
T5	20790	473	0	0
T6	2450	66	0	0
T7	2258	202	0	0
T8	5744	0	0	0
T9	223088	2911	0	0
T10	6067	0	0	0
T11	0	412	0	0
T12	5526	0	0	0
T13	0	1101	0	0
T14	0	531	0	0
T15	0	1663	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9939486	11233	0	0
T2	2676	4	0	0
T3	3781	4	0	0
T4	10815	0	0	0
T5	20790	30	0	0
T6	2450	4	0	0
T7	2258	15	0	0
T8	5744	0	0	0
T9	223088	200	0	0
T10	6067	0	0	0
T11	0	28	0	0
T12	5526	0	0	0
T13	0	75	0	0
T14	0	37	0	0
T15	0	113	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9939486	103705	0	0
T2	2676	37	0	0
T3	3781	37	0	0
T4	10815	0	0	0
T5	20790	275	0	0
T6	2450	37	0	0
T7	2258	135	0	0
T8	5744	0	0	0
T9	223088	1806	0	0
T10	6067	0	0	0
T11	0	255	0	0
T12	5526	0	0	0
T13	0	702	0	0
T14	0	334	0	0
T15	0	1023	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9939486	5637168	0	0
T1	1607	970	0	0
T2	2676	1681	0	0
T3	3781	2848	0	0
T4	10815	10244	0	0
T5	20790	8142	0	0
T6	2450	1458	0	0
T7	2258	1438	0	0
T8	5744	5148	0	0
T9	223088	175276	0	0
T10	6067	5474	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9939486	165294	0	0
T2	2676	56	0	0
T3	3781	68	0	0
T4	10815	0	0	0
T5	20790	473	0	0
T6	2450	66	0	0
T7	2258	202	0	0
T8	5744	0	0	0
T9	223088	2911	0	0
T10	6067	0	0	0
T11	0	412	0	0
T12	5526	0	0	0
T13	0	1101	0	0
T14	0	531	0	0
T15	0	1663	0	0