Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T5
0	1	Covered	T3,T5,T6
1	0	Covered	T2,T5,T9

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T5,T9,T12
1	0	Covered	T2,T3,T5
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	46736425	7847	0	0
CascadeEffAonToRstPorAboveRise_A	46736425	7847	0	0
CascadeEffAonToRstPorIoAboveFall_A	44865238	7847	0	0
CascadeEffAonToRstPorIoAboveRise_A	44865238	7847	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	22433383	7847	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	22433383	7847	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	11216477	7847	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	11216477	7847	0	0
CascadeEffAonToRstPorUcbAboveFall_A	22433485	7847	0	0
CascadeEffAonToRstPorUcbAboveRise_A	22433485	7847	0	0
CascadeLcToLcAboveFall_A	46736425	19080	0	0
CascadeLcToLcAboveRise_A	46736425	19080	0	0
CascadeLcToLcAonAboveFall_A	1415728	19080	0	0
CascadeLcToLcAonAboveRise_A	1415728	19080	0	0
CascadeLcToLcShadowedAboveFall_A	46736425	19080	0	0
CascadeLcToLcShadowedAboveRise_A	46736425	19080	0	0
CascadePorToAonAboveFall_A	1415728	6496	0	0
CascadeSysToSysAboveFall_A	46736425	19080	0	0
CascadeSysToSysAboveRise_A	46736425	19080	0	0
ScanRstToAonRise_A	1415728	175	0	0
StablePorToAonRise_A	1415728	7847	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	9939486	19080	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	9939486	19080	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	9939486	19080	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	9939486	19080	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	11216477	19080	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	11216477	19080	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	9939486	19080	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	9939486	19080	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	9939486	19080	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	9939486	19080	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	46736425	7847	0	0
T1	6776	1	0	0
T2	11766	2	0	0
T3	17361	2	0	0
T4	45443	1	0	0
T5	105522	26	0	0
T6	11419	2	0	0
T7	13085	1	0	0
T8	24214	1	0	0
T9	103225	104	0	0
T10	25561	1	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	46736425	7847	0	0
T1	6776	1	0	0
T2	11766	2	0	0
T3	17361	2	0	0
T4	45443	1	0	0
T5	105522	26	0	0
T6	11419	2	0	0
T7	13085	1	0	0
T8	24214	1	0	0
T9	103225	104	0	0
T10	25561	1	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	44865238	7847	0	0
T1	6503	1	0	0
T2	11287	2	0	0
T3	16667	2	0	0
T4	43623	1	0	0
T5	101266	26	0	0
T6	10956	2	0	0
T7	12563	1	0	0
T8	23245	1	0	0
T9	991002	104	0	0
T10	24538	1	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	44865238	7847	0	0
T1	6503	1	0	0
T2	11287	2	0	0
T3	16667	2	0	0
T4	43623	1	0	0
T5	101266	26	0	0
T6	10956	2	0	0
T7	12563	1	0	0
T8	23245	1	0	0
T9	991002	104	0	0
T10	24538	1	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22433383	7847	0	0
T1	3252	1	0	0
T2	5644	2	0	0
T3	8332	2	0	0
T4	21812	1	0	0
T5	50653	26	0	0
T6	5480	2	0	0
T7	6280	1	0	0
T8	11623	1	0	0
T9	495474	104	0	0
T10	12270	1	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22433383	7847	0	0
T1	3252	1	0	0
T2	5644	2	0	0
T3	8332	2	0	0
T4	21812	1	0	0
T5	50653	26	0	0
T6	5480	2	0	0
T7	6280	1	0	0
T8	11623	1	0	0
T9	495474	104	0	0
T10	12270	1	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11216477	7847	0	0
T1	1624	1	0	0
T2	2820	2	0	0
T3	4166	2	0	0
T4	10904	1	0	0
T5	25320	26	0	0
T6	2739	2	0	0
T7	3139	1	0	0
T8	5811	1	0	0
T9	247746	104	0	0
T10	6134	1	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11216477	7847	0	0
T1	1624	1	0	0
T2	2820	2	0	0
T3	4166	2	0	0
T4	10904	1	0	0
T5	25320	26	0	0
T6	2739	2	0	0
T7	3139	1	0	0
T8	5811	1	0	0
T9	247746	104	0	0
T10	6134	1	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22433485	7847	0	0
T1	3251	1	0	0
T2	5646	2	0	0
T3	8332	2	0	0
T4	21812	1	0	0
T5	50642	26	0	0
T6	5483	2	0	0
T7	6280	1	0	0
T8	11622	1	0	0
T9	495498	104	0	0
T10	12269	1	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22433485	7847	0	0
T1	3251	1	0	0
T2	5646	2	0	0
T3	8332	2	0	0
T4	21812	1	0	0
T5	50642	26	0	0
T6	5483	2	0	0
T7	6280	1	0	0
T8	11622	1	0	0
T9	495498	104	0	0
T10	12269	1	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	46736425	19080	0	0
T1	6776	1	0	0
T2	11766	6	0	0
T3	17361	6	0	0
T4	45443	1	0	0
T5	105522	56	0	0
T6	11419	6	0	0
T7	13085	16	0	0
T8	24214	1	0	0
T9	103225	304	0	0
T10	25561	1	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	46736425	19080	0	0
T1	6776	1	0	0
T2	11766	6	0	0
T3	17361	6	0	0
T4	45443	1	0	0
T5	105522	56	0	0
T6	11419	6	0	0
T7	13085	16	0	0
T8	24214	1	0	0
T9	103225	304	0	0
T10	25561	1	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1415728	19080	0	0
T1	203	1	0	0
T2	352	6	0	0
T3	520	6	0	0
T4	1362	1	0	0
T5	3230	56	0	0
T6	341	6	0	0
T7	391	16	0	0
T8	725	1	0	0
T9	31358	304	0	0
T10	766	1	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1415728	19080	0	0
T1	203	1	0	0
T2	352	6	0	0
T3	520	6	0	0
T4	1362	1	0	0
T5	3230	56	0	0
T6	341	6	0	0
T7	391	16	0	0
T8	725	1	0	0
T9	31358	304	0	0
T10	766	1	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	46736425	19080	0	0
T1	6776	1	0	0
T2	11766	6	0	0
T3	17361	6	0	0
T4	45443	1	0	0
T5	105522	56	0	0
T6	11419	6	0	0
T7	13085	16	0	0
T8	24214	1	0	0
T9	103225	304	0	0
T10	25561	1	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	46736425	19080	0	0
T1	6776	1	0	0
T2	11766	6	0	0
T3	17361	6	0	0
T4	45443	1	0	0
T5	105522	56	0	0
T6	11419	6	0	0
T7	13085	16	0	0
T8	24214	1	0	0
T9	103225	304	0	0
T10	25561	1	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1415728	6496	0	0
T1	203	1	0	0
T2	352	1	0	0
T3	520	1	0	0
T4	1362	1	0	0
T5	3230	16	0	0
T6	341	1	0	0
T7	391	1	0	0
T8	725	1	0	0
T9	31358	55	0	0
T10	766	1	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	46736425	19080	0	0
T1	6776	1	0	0
T2	11766	6	0	0
T3	17361	6	0	0
T4	45443	1	0	0
T5	105522	56	0	0
T6	11419	6	0	0
T7	13085	16	0	0
T8	24214	1	0	0
T9	103225	304	0	0
T10	25561	1	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	46736425	19080	0	0
T1	6776	1	0	0
T2	11766	6	0	0
T3	17361	6	0	0
T4	45443	1	0	0
T5	105522	56	0	0
T6	11419	6	0	0
T7	13085	16	0	0
T8	24214	1	0	0
T9	103225	304	0	0
T10	25561	1	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1415728	175	0	0
T5	3230	1	0	0
T6	341	0	0	0
T7	391	0	0	0
T8	725	0	0	0
T9	31358	3	0	0
T10	766	0	0	0
T11	2775	1	0	0
T12	736	0	0	0
T13	3667	0	0	0
T14	0	1	0	0
T15	0	6	0	0
T16	730	0	0	0
T27	0	5	0	0
T42	0	1	0	0
T43	0	1	0	0
T94	0	3	0	0
T129	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1415728	7847	0	0
T1	203	1	0	0
T2	352	2	0	0
T3	520	2	0	0
T4	1362	1	0	0
T5	3230	26	0	0
T6	341	2	0	0
T7	391	1	0	0
T8	725	1	0	0
T9	31358	104	0	0
T10	766	1	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9939486	19080	0	0
T1	1607	1	0	0
T2	2676	6	0	0
T3	3781	6	0	0
T4	10815	1	0	0
T5	20790	56	0	0
T6	2450	6	0	0
T7	2258	16	0	0
T8	5744	1	0	0
T9	223088	304	0	0
T10	6067	1	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9939486	19080	0	0
T1	1607	1	0	0
T2	2676	6	0	0
T3	3781	6	0	0
T4	10815	1	0	0
T5	20790	56	0	0
T6	2450	6	0	0
T7	2258	16	0	0
T8	5744	1	0	0
T9	223088	304	0	0
T10	6067	1	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9939486	19080	0	0
T1	1607	1	0	0
T2	2676	6	0	0
T3	3781	6	0	0
T4	10815	1	0	0
T5	20790	56	0	0
T6	2450	6	0	0
T7	2258	16	0	0
T8	5744	1	0	0
T9	223088	304	0	0
T10	6067	1	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9939486	19080	0	0
T1	1607	1	0	0
T2	2676	6	0	0
T3	3781	6	0	0
T4	10815	1	0	0
T5	20790	56	0	0
T6	2450	6	0	0
T7	2258	16	0	0
T8	5744	1	0	0
T9	223088	304	0	0
T10	6067	1	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11216477	19080	0	0
T1	1624	1	0	0
T2	2820	6	0	0
T3	4166	6	0	0
T4	10904	1	0	0
T5	25320	56	0	0
T6	2739	6	0	0
T7	3139	16	0	0
T8	5811	1	0	0
T9	247746	304	0	0
T10	6134	1	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11216477	19080	0	0
T1	1624	1	0	0
T2	2820	6	0	0
T3	4166	6	0	0
T4	10904	1	0	0
T5	25320	56	0	0
T6	2739	6	0	0
T7	3139	16	0	0
T8	5811	1	0	0
T9	247746	304	0	0
T10	6134	1	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9939486	19080	0	0
T1	1607	1	0	0
T2	2676	6	0	0
T3	3781	6	0	0
T4	10815	1	0	0
T5	20790	56	0	0
T6	2450	6	0	0
T7	2258	16	0	0
T8	5744	1	0	0
T9	223088	304	0	0
T10	6067	1	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9939486	19080	0	0
T1	1607	1	0	0
T2	2676	6	0	0
T3	3781	6	0	0
T4	10815	1	0	0
T5	20790	56	0	0
T6	2450	6	0	0
T7	2258	16	0	0
T8	5744	1	0	0
T9	223088	304	0	0
T10	6067	1	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9939486	19080	0	0
T1	1607	1	0	0
T2	2676	6	0	0
T3	3781	6	0	0
T4	10815	1	0	0
T5	20790	56	0	0
T6	2450	6	0	0
T7	2258	16	0	0
T8	5744	1	0	0
T9	223088	304	0	0
T10	6067	1	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9939486	19080	0	0
T1	1607	1	0	0
T2	2676	6	0	0
T3	3781	6	0	0
T4	10815	1	0	0
T5	20790	56	0	0
T6	2450	6	0	0
T7	2258	16	0	0
T8	5744	1	0	0
T9	223088	304	0	0
T10	6067	1	0	0