Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7793

1

T1

19

T4

26

T9

153

auto[1]

10640

1

T1

82

T3

4

T4

23

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5823	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6157	1			T1	27		T2	1		T3	2
reset_info_cp[2]	2834	1			T1	15		T3	1		T4	7
reset_info_cp[4]	3701	1			T1	17		T3	1		T4	12
reset_info_cp[8]	112	1			T9	2		T49	2		T52	1
reset_info_cp[16]	129	1			T4	2		T9	2		T49	6
reset_info_cp[32]	93	1			T8	1		T9	1		T49	2
reset_info_cp[64]	111	1			T9	1		T13	1		T49	2
reset_info_cp[128]	91	1			T1	1		T9	2		T35	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3006	1			T1	19		T4	12		T9	50
reset_info_cp[1]	auto[1]	2533	1			T1	7		T3	1		T4	5
reset_info_cp[2]	auto[0]	884	1			T4	4		T9	24		T23	4
reset_info_cp[2]	auto[1]	1950	1			T1	15		T3	1		T4	3
reset_info_cp[4]	auto[0]	1285	1			T4	4		T9	21		T23	8
reset_info_cp[4]	auto[1]	2416	1			T1	17		T3	1		T4	8
reset_info_cp[8]	auto[0]	39	1			T49	1		T130	2		T140	1
reset_info_cp[8]	auto[1]	73	1			T9	2		T49	1		T52	1
reset_info_cp[16]	auto[0]	51	1			T4	2		T9	1		T49	1
reset_info_cp[16]	auto[1]	78	1			T9	1		T49	5		T26	2
reset_info_cp[32]	auto[0]	32	1			T49	1		T45	1		T111	1
reset_info_cp[32]	auto[1]	61	1			T8	1		T9	1		T49	1
reset_info_cp[64]	auto[0]	51	1			T9	1		T49	1		T130	1
reset_info_cp[64]	auto[1]	60	1			T13	1		T49	1		T27	1
reset_info_cp[128]	auto[0]	37	1			T9	1		T111	1		T139	2
reset_info_cp[128]	auto[1]	54	1			T1	1		T9	1		T35	1