Assertions
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Assertions by Category
ASSERTPROPERTIESSEQUENCES
Total733010
Category 0733010


Assertions by Severity
ASSERTPROPERTIESSEQUENCES
Total733010
Severity 0733010


Summary for Assertions
NUMBERPERCENT
Total Number733100.00
Uncovered40.55
Success72999.45
Failure00.00
Incomplete00.00
Without Attempts00.00


Summary for Cover Sequences
NUMBERPERCENT
Total Number10100.00
Uncovered00.00
All Matches10100.00
First Matches10100.00


Detail Report for Assertions

Assertions Uncovered:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorAonEnTracksRstPorAonActive_A 001585816000
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorEnTracksRstPorInactive_A 0052335522000
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoDiv4EnTracksRstPorIoDiv4Active_A 0012560289000
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoEnTracksRstPorIoInactive_A 0050240270000

Assertions Success:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
tb.dut.AlertsKnownO_A 0011137395646513000
tb.dut.FpvSecCmRegWeOnehotCheck_A 00111373958000
tb.dut.ParameterMatch_A 0050350300
tb.dut.PwrKnownO_A 0011137395646513000
tb.dut.ResetsKnownO_A 0011137395646513000
tb.dut.RstEnKnownO_A 0011137395646513000
tb.dut.TlAReadyKnownO_A 0011137395646513000
tb.dut.TlDValidKnownO_A 0011137395646513000
tb.dut.gen_d0_i2c0_assert.FpvSecCmD0I2c0FsmCheck_A 00111373958000
tb.dut.gen_d0_i2c1_assert.FpvSecCmD0I2c1FsmCheck_A 00111373958000
tb.dut.gen_d0_i2c2_assert.FpvSecCmD0I2c2FsmCheck_A 00111373958000
tb.dut.gen_d0_lc_assert.FpvSecCmD0LcFsmCheck_A 00111373958000
tb.dut.gen_d0_lc_io_assert.FpvSecCmD0LcIoFsmCheck_A 00111373958000
tb.dut.gen_d0_lc_io_div2_assert.FpvSecCmD0LcIoDiv2FsmCheck_A 00111373958000
tb.dut.gen_d0_lc_shadowed_assert.FpvSecCmD0LcShadowedFsmCheck_A 00111373958000
tb.dut.gen_d0_lc_usb_assert.FpvSecCmD0LcUsbFsmCheck_A 00111373958000
tb.dut.gen_d0_spi_device_assert.FpvSecCmD0SpiDeviceFsmCheck_A 00111373958000
tb.dut.gen_d0_spi_host0_assert.FpvSecCmD0SpiHost0FsmCheck_A 00111373958000
tb.dut.gen_d0_spi_host1_assert.FpvSecCmD0SpiHost1FsmCheck_A 00111373958000
tb.dut.gen_d0_sys_assert.FpvSecCmD0SysFsmCheck_A 00111373958000
tb.dut.gen_d0_usb_aon_assert.FpvSecCmD0UsbAonFsmCheck_A 00111373958000
tb.dut.gen_d0_usb_assert.FpvSecCmD0UsbFsmCheck_A 00111373958000
tb.dut.gen_daon_lc_aon_assert.FpvSecCmDAonLcAonFsmCheck_A 00111373958000
tb.dut.gen_daon_lc_assert.FpvSecCmDAonLcFsmCheck_A 00111373958000
tb.dut.gen_daon_lc_io_assert.FpvSecCmDAonLcIoFsmCheck_A 00111373958000
tb.dut.gen_daon_lc_io_div2_assert.FpvSecCmDAonLcIoDiv2FsmCheck_A 00111373958000
tb.dut.gen_daon_lc_shadowed_assert.FpvSecCmDAonLcShadowedFsmCheck_A 00111373958000
tb.dut.gen_daon_lc_usb_assert.FpvSecCmDAonLcUsbFsmCheck_A 00111373958000
tb.dut.gen_daon_por_assert.FpvSecCmDAonPorFsmCheck_A 00111373958000
tb.dut.gen_daon_por_io_assert.FpvSecCmDAonPorIoFsmCheck_A 00111373958000
tb.dut.gen_daon_por_io_div2_assert.FpvSecCmDAonPorIoDiv2FsmCheck_A 00111373958000
tb.dut.gen_daon_por_io_div4_assert.FpvSecCmDAonPorIoDiv4FsmCheck_A 00111373958000
tb.dut.gen_daon_por_usb_assert.FpvSecCmDAonPorUsbFsmCheck_A 00111373958000
tb.dut.gen_daon_sys_io_div4_assert.FpvSecCmDAonSysIoDiv4FsmCheck_A 00111373958000
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_prim_mubi4_sender.OutputsKnown_A 00158581696074500
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic.selKnown0 008897839400
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic.selKnown1 002555205200
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic.selKnown0 008497799400
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic.selKnown1 002555205200
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic.selKnown0 006888638500
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic.selKnown1 002555205200
tb.dut.gen_rst_por_aon[0].u_por_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050350300
tb.dut.gen_rst_por_aon[0].u_por_scanmode_sync.OutputsKnown_A 0011137395646513000
tb.dut.gen_rst_por_aon[0].u_por_scanmode_sync.gen_no_flops.OutputDelay_A 0011137395646513000
tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic.selKnown0 008497799400
tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic.selKnown1 002555205200
tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_prim_mubi4_sender.OutputsKnown_A 00158581694292900
tb.dut.gen_rst_por_aon[1].u_por_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050350300
tb.dut.gen_rst_por_aon[1].u_por_scanmode_sync.OutputsKnown_A 0011137395646513000
tb.dut.gen_rst_por_aon[1].u_por_scanmode_sync.gen_no_flops.OutputDelay_A 0011137395646513000
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[0].LcHandshakeOff_A 00111373951262600
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[0].LcHandshakeOn_A 001113739511637100
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[0].SysHandshakeOff_A 0011137395650431900
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[0].SysHandshakeOn_A 001113739518574700
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[1].LcHandshakeOff_A 00111373951262600
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[1].LcHandshakeOn_A 001113739511637100
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[1].SysHandshakeOff_A 0011137395650431900
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[1].SysHandshakeOn_A 001113739518574700
tb.dut.rstmgr_attrs_sva_if.AlertInfoAttr_A 0050350300
tb.dut.rstmgr_attrs_sva_if.CpuInfoAttr_A 0050350300
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorAboveFall_A 0052335522849700
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorAboveRise_A 0052335522849700
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoAboveFall_A 0050240270849700
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoAboveRise_A 0050240270849700
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoDiv2AboveFall_A 0025121023849700
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoDiv2AboveRise_A 0025121023849700
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoDiv4AboveFall_A 0012560289849700
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoDiv4AboveRise_A 0012560289849700
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorUcbAboveFall_A 0025120854849700
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorUcbAboveRise_A 0025120854849700
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcAboveFall_A 00523355222112300
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcAboveRise_A 00523355222112300
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcAonAboveFall_A 0015858162112300
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcAonAboveRise_A 0015858162112300
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcShadowedAboveFall_A 00523355222112300
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcShadowedAboveRise_A 00523355222112300
tb.dut.rstmgr_cascading_sva_if.CascadePorToAonAboveFall_A 001585816690200
tb.dut.rstmgr_cascading_sva_if.CascadeSysToSysAboveFall_A 00523355222112300
tb.dut.rstmgr_cascading_sva_if.CascadeSysToSysAboveRise_A 00523355222112300
tb.dut.rstmgr_cascading_sva_if.ScanRstToAonRise_A 00158581616800
tb.dut.rstmgr_cascading_sva_if.StablePorToAonRise_A 001585816849700
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].CascadeLcToSysAboveFall_A 00111373952112300
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].CascadeLcToSysAboveRise_A 00111373952112300
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].CascadeLocalRstToLcAboveFall_A 00111373952112300
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].CascadeLocalRstToLcAboveRise_A 00111373952112300
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A 00125602892112300
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A 00125602892112300
tb.dut.rstmgr_cascading_sva_if.g_power_domains[1].CascadeLcToSysAboveFall_A 00111373952112300
tb.dut.rstmgr_cascading_sva_if.g_power_domains[1].CascadeLcToSysAboveRise_A 00111373952112300
tb.dut.rstmgr_cascading_sva_if.g_power_domains[1].CascadeLocalRstToLcAboveFall_A 00111373952112300
tb.dut.rstmgr_cascading_sva_if.g_power_domains[1].CascadeLocalRstToLcAboveRise_A 00111373952112300
tb.dut.rstmgr_csr_assert.TlulOOBAddrErr_A 0011898967615100
tb.dut.rstmgr_csr_assert.alert_regwen_rd_A 0011898967511600
tb.dut.rstmgr_csr_assert.cpu_regwen_rd_A 0011898967508000
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_0_rd_A 0011898967867500
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_1_rd_A 0011898967862400
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_2_rd_A 0011898967868700
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_3_rd_A 0011898967875400
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_4_rd_A 0011898967866700
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_5_rd_A 0011898967894400
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_6_rd_A 0011898967873700
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_7_rd_A 0011898967857300
tb.dut.rstmgr_csr_assert.sw_rst_regwen_0_rd_A 0011898967538800
tb.dut.rstmgr_csr_assert.sw_rst_regwen_1_rd_A 0011898967540600
tb.dut.rstmgr_csr_assert.sw_rst_regwen_2_rd_A 0011898967554100
tb.dut.rstmgr_csr_assert.sw_rst_regwen_3_rd_A 0011898967590000
tb.dut.rstmgr_csr_assert.sw_rst_regwen_4_rd_A 0011898967552000
tb.dut.rstmgr_csr_assert.sw_rst_regwen_5_rd_A 0011898967563600
tb.dut.rstmgr_csr_assert.sw_rst_regwen_6_rd_A 0011898967551100
tb.dut.rstmgr_csr_assert.sw_rst_regwen_7_rd_A 0011898967585400
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c0EnTracksRstI2c0Active_A 00125602891374500
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c0EnTracksRstI2c0Inactive_A 00125602892214900
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c1EnTracksRstI2c1Active_A 00125602891382900
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c1EnTracksRstI2c1Inactive_A 00125602892221900
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c2EnTracksRstI2c2Active_A 00125602891388400
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c2EnTracksRstI2c2Inactive_A 00125602892226400
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoDiv2EnTracksRstLcIoDiv2Active_A 00251210231270100
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoDiv2EnTracksRstLcIoDiv2Inactive_A 00251210232112300
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoDiv4ShadowedEnTracksRstLcIoDiv4ShadowedActive_A 00125602891272600
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoDiv4ShadowedEnTracksRstLcIoDiv4ShadowedInactive_A 00125602892117300
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoEnTracksRstLcIoActive_A 00502402701270500
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoEnTracksRstLcIoInactive_A 00502402702112300
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcShadowedEnTracksRstLcShadowedActive_A 00523355221267600
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcShadowedEnTracksRstLcShadowedInactive_A 00523355222112300
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcUsbEnTracksRstLcUsbActive_A 00251208541269900
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcUsbEnTracksRstLcUsbInactive_A 00251208542112300
tb.dut.rstmgr_rst_en_track_sva_if.D0RstPorAonEnTracksRstPorAonActive_A 0015858165000
tb.dut.rstmgr_rst_en_track_sva_if.D0RstPorAonEnTracksRstPorAonInactive_A 001585816848300
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiDeviceEnTracksRstSpiDeviceActive_A 00125602891353600
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiDeviceEnTracksRstSpiDeviceInactive_A 00125602892192500
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiHost0EnTracksRstSpiHost0Active_A 00502402701356200
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiHost0EnTracksRstSpiHost0Inactive_A 00502402702195400
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiHost1EnTracksRstSpiHost1Active_A 00251210231364000
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiHost1EnTracksRstSpiHost1Inactive_A 00251210232202500
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSysEnTracksRstSysActive_A 00523355221270200
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSysEnTracksRstSysInactive_A 00523355222112300
tb.dut.rstmgr_rst_en_track_sva_if.D0RstUsbAonEnTracksRstUsbAonActive_A 0015858161321000
tb.dut.rstmgr_rst_en_track_sva_if.D0RstUsbAonEnTracksRstUsbAonInactive_A 0015858162121500
tb.dut.rstmgr_rst_en_track_sva_if.D0RstUsbEnTracksRstUsbActive_A 00251208541366200
tb.dut.rstmgr_rst_en_track_sva_if.D0RstUsbEnTracksRstUsbInactive_A 00251208542204900
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcAonEnTracksRstLcAonActive_A 0015858161264600
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcAonEnTracksRstLcAonInactive_A 0015858162110900
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoDiv2EnTracksRstLcIoDiv2Active_A 00251210231264800
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoDiv2EnTracksRstLcIoDiv2Inactive_A 00251210232112300
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoDiv4ShadowedEnTracksRstLcIoDiv4ShadowedActive_A 00125602891267600
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoDiv4ShadowedEnTracksRstLcIoDiv4ShadowedInactive_A 00125602892117300
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoEnTracksRstLcIoActive_A 00502402701265200
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoEnTracksRstLcIoInactive_A 00502402702112300
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcShadowedEnTracksRstLcShadowedActive_A 00523355221269400
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcShadowedEnTracksRstLcShadowedInactive_A 00523355222117300
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcUsbEnTracksRstLcUsbActive_A 00251208541265000
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcUsbEnTracksRstLcUsbInactive_A 00251208542112300
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorAonEnTracksRstPorAonInactive_A 001585816849700
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorEnTracksRstPorActive_A 00523355222600
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoDiv2EnTracksRstPorIoDiv2Active_A 00251210231900
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoDiv2EnTracksRstPorIoDiv2Inactive_A 0025121023224700
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoDiv4EnTracksRstPorIoDiv4Inactive_A 0012560289849700
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoEnTracksRstPorIoActive_A 00502402702600
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorUsbEnTracksRstPorUsbActive_A 00251208542000
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorUsbEnTracksRstPorUsbInactive_A 0025120854224700
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstSysIoDiv4EnTracksRstSysIoDiv4Active_A 00125602891265700
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstSysIoDiv4EnTracksRstSysIoDiv4Inactive_A 00125602892112300
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[0].RstEnOff_A 00125602891342500
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[0].RstEnOn_A 001256028999200
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[0].RstNOff_A 00125602891342500
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[0].RstNOn_A 001256028999200
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[1].RstEnOff_A 00502402701216700
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[1].RstEnOn_A 005024027093100
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[1].RstNOff_A 00502402701216700
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[1].RstNOn_A 005024027093100
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[2].RstEnOff_A 00251210231223600
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[2].RstEnOn_A 002512102394500
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[2].RstNOff_A 00251210231223600
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[2].RstNOn_A 002512102394500
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[3].RstEnOff_A 00251208541226300
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[3].RstEnOn_A 002512085496300
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[3].RstNOff_A 00251208541226300
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[3].RstNOn_A 002512085496300
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[4].RstEnOff_A 0015858162080300
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[4].RstEnOn_A 001585816102500
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[4].RstNOff_A 0015858162080300
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[4].RstNOn_A 001585816102500
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[5].RstEnOff_A 00125602891364900
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[5].RstEnOn_A 0012560289104600
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tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[5].RstNOn_A 0012560289104600
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tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[7].RstNOn_A 0012560289117900
tb.dut.tlul_assert_device.aKnown_A 0011898967105223000
tb.dut.tlul_assert_device.aKnown_AKnownEnable 0011898967696045800
tb.dut.tlul_assert_device.aReadyKnown_A 0011898967696045800
tb.dut.tlul_assert_device.dKnown_A 0011898967189802400
tb.dut.tlul_assert_device.dKnown_AKnownEnable 0011898967696045800
tb.dut.tlul_assert_device.dReadyKnown_A 0011898967696045800
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tb.dut.tlul_assert_device.gen_device.aDataKnown_M 001189958546415300
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A 0011898967413300
tb.dut.tlul_assert_device.gen_device.contigMask_M 001189958578184100
tb.dut.tlul_assert_device.gen_device.dDataKnown_A 001189958598358700
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A 0011898967446500
tb.dut.tlul_assert_device.gen_device.legalAParam_M 0011899585105240700
tb.dut.tlul_assert_device.gen_device.legalDParam_A 0011899585189820100
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M 0011899585105240700
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A 0011899585189820100
tb.dut.tlul_assert_device.gen_device.respOpcode_A 0011899585189820100
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A 0011899585189820100
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A 0011898967246400
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A 0011898967205000
tb.dut.tlul_assert_device.p_dbw.TlDbw_A 0061861800
tb.dut.u_alert_info.CntStoreSlot_A 0050350300
tb.dut.u_alert_info.CntWidth_A 0050350300
tb.dut.u_cpu_info.CntStoreSlot_A 0050350300
tb.dut.u_cpu_info.CntWidth_A 0050350300
tb.dut.u_ctrl_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050350300
tb.dut.u_ctrl_scanmode_sync.OutputsKnown_A 0012560289753461900
tb.dut.u_ctrl_scanmode_sync.gen_no_flops.OutputDelay_A 0012560289753461900
tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00211732067000
tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002555205200
tb.dut.u_d0_i2c0.u_prim_mubi4_sender.OutputsKnown_A 0012560289638204400
tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00221462164300
tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002555205200
tb.dut.u_d0_i2c0.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050350300
tb.dut.u_d0_i2c0.u_scanmode_sync.OutputsKnown_A 0011137395646513000
tb.dut.u_d0_i2c0.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011137395646513000
tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00211732067000
tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002555205200
tb.dut.u_d0_i2c1.u_prim_mubi4_sender.OutputsKnown_A 0012560289636501800
tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00222162171300
tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002555205200
tb.dut.u_d0_i2c1.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050350300
tb.dut.u_d0_i2c1.u_scanmode_sync.OutputsKnown_A 0011137395646513000
tb.dut.u_d0_i2c1.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011137395646513000
tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00211732067000
tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002555205200
tb.dut.u_d0_i2c2.u_prim_mubi4_sender.OutputsKnown_A 0012560289636719000
tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00222592175600
tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002555205200
tb.dut.u_d0_i2c2.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050350300
tb.dut.u_d0_i2c2.u_scanmode_sync.OutputsKnown_A 0011137395646513000
tb.dut.u_d0_i2c2.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011137395646513000
tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00211732067000
tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002555205200
tb.dut.u_d0_lc.u_prim_mubi4_sender.OutputsKnown_A 00523355222719954000
tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00211232062000
tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002555205200
tb.dut.u_d0_lc.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050350300
tb.dut.u_d0_lc.u_scanmode_sync.OutputsKnown_A 0011137395646513000
tb.dut.u_d0_lc.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011137395646513000
tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00211732067000
tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002555205200
tb.dut.u_d0_lc_io.u_prim_mubi4_sender.OutputsKnown_A 00502402702610969000
tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00211232062000
tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002555205200
tb.dut.u_d0_lc_io.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050350300
tb.dut.u_d0_lc_io.u_scanmode_sync.OutputsKnown_A 0011137395646513000
tb.dut.u_d0_lc_io.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011137395646513000
tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00211732067000
tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002555205200
tb.dut.u_d0_lc_io_div2.u_prim_mubi4_sender.OutputsKnown_A 00251210231304523700
tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00211232062000
tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002555205200
tb.dut.u_d0_lc_io_div2.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050350300
tb.dut.u_d0_lc_io_div2.u_scanmode_sync.OutputsKnown_A 0011137395646513000
tb.dut.u_d0_lc_io_div2.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011137395646513000
tb.dut.u_d0_lc_io_div4.u_prim_mubi4_sender.OutputsKnown_A 0012560289649600600
tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00211232062000
tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002555205200
tb.dut.u_d0_lc_io_div4.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050350300
tb.dut.u_d0_lc_io_div4.u_scanmode_sync.OutputsKnown_A 0011137395646513000
tb.dut.u_d0_lc_io_div4.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011137395646513000
tb.dut.u_d0_lc_io_div4_shadowed.u_prim_mubi4_sender.OutputsKnown_A 0012560289649600600
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tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002555205200
tb.dut.u_d0_lc_io_div4_shadowed.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050350300
tb.dut.u_d0_lc_io_div4_shadowed.u_scanmode_sync.OutputsKnown_A 0011137395646513000
tb.dut.u_d0_lc_io_div4_shadowed.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011137395646513000
tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00211732067000
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tb.dut.u_d0_lc_shadowed.u_prim_mubi4_sender.OutputsKnown_A 00523355222720086300
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tb.dut.u_d0_lc_shadowed.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050350300
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tb.dut.u_d0_lc_shadowed.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011137395646513000
tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00211732067000
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tb.dut.u_d0_lc_usb.u_prim_mubi4_sender.OutputsKnown_A 00251208541304532400
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tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002555205200
tb.dut.u_d0_lc_usb.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050350300
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tb.dut.u_d0_spi_device.u_prim_mubi4_sender.OutputsKnown_A 0012560289635692800
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tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002555205200
tb.dut.u_d0_spi_device.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050350300
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tb.dut.u_d0_spi_host0.u_prim_mubi4_sender.OutputsKnown_A 00502402702558548300
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tb.dut.u_d0_spi_host0.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050350300
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tb.dut.u_d0_spi_host1.u_prim_mubi4_sender.OutputsKnown_A 00251210231275861300
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tb.dut.u_d0_spi_host1.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050350300
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tb.dut.u_d0_sys.u_prim_mubi4_sender.OutputsKnown_A 00523355222691042000
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tb.dut.u_d0_sys.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050350300
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tb.dut.u_d0_sys.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011137395646513000
tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00211732067000
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tb.dut.u_d0_usb.u_prim_mubi4_sender.OutputsKnown_A 00251208541277602200
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tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002555205200
tb.dut.u_d0_usb.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050350300
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tb.dut.u_d0_usb.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011137395646513000
tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00210592055600
tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002555205200
tb.dut.u_d0_usb_aon.u_prim_mubi4_sender.OutputsKnown_A 00158581678968700
tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00220942159100
tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002555205200
tb.dut.u_d0_usb_aon.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050350300
tb.dut.u_d0_usb_aon.u_scanmode_sync.OutputsKnown_A 0011137395646513000
tb.dut.u_d0_usb_aon.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011137395646513000
tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00211732067000
tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002555205200
tb.dut.u_daon_lc.u_prim_mubi4_sender.OutputsKnown_A 00523355222789655300
tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00211232062000
tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002555205200
tb.dut.u_daon_lc.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050350300
tb.dut.u_daon_lc.u_scanmode_sync.OutputsKnown_A 0011137395646513000
tb.dut.u_daon_lc.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011137395646513000
tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00210592055600
tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002555205200
tb.dut.u_daon_lc_aon.u_prim_mubi4_sender.OutputsKnown_A 00158581682757300
tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00211232062000
tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002555205200
tb.dut.u_daon_lc_aon.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050350300
tb.dut.u_daon_lc_aon.u_scanmode_sync.OutputsKnown_A 0011137395646513000
tb.dut.u_daon_lc_aon.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011137395646513000
tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00211732067000
tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002555205200
tb.dut.u_daon_lc_io.u_prim_mubi4_sender.OutputsKnown_A 00502402702678099800
tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00211232062000
tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002555205200
tb.dut.u_daon_lc_io.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050350300
tb.dut.u_daon_lc_io.u_scanmode_sync.OutputsKnown_A 0011137395646513000
tb.dut.u_daon_lc_io.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011137395646513000
tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00211732067000
tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002555205200
tb.dut.u_daon_lc_io_div2.u_prim_mubi4_sender.OutputsKnown_A 00251210231338089400
tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00211232062000
tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002555205200
tb.dut.u_daon_lc_io_div2.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050350300
tb.dut.u_daon_lc_io_div2.u_scanmode_sync.OutputsKnown_A 0011137395646513000
tb.dut.u_daon_lc_io_div2.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011137395646513000
tb.dut.u_daon_lc_io_div4.u_prim_mubi4_sender.OutputsKnown_A 0012560289666378600
tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00211232062000
tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002555205200
tb.dut.u_daon_lc_io_div4.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050350300
tb.dut.u_daon_lc_io_div4.u_scanmode_sync.OutputsKnown_A 0011137395646513000
tb.dut.u_daon_lc_io_div4.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011137395646513000
tb.dut.u_daon_lc_io_div4_shadowed.u_prim_mubi4_sender.OutputsKnown_A 0012560289666378600
tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00211232062000
tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002555205200
tb.dut.u_daon_lc_io_div4_shadowed.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050350300
tb.dut.u_daon_lc_io_div4_shadowed.u_scanmode_sync.OutputsKnown_A 0011137395646513000
tb.dut.u_daon_lc_io_div4_shadowed.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011137395646513000
tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00211732067000
tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002555205200
tb.dut.u_daon_lc_shadowed.u_prim_mubi4_sender.OutputsKnown_A 00523355222789694200
tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00211232062000
tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002555205200
tb.dut.u_daon_lc_shadowed.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050350300
tb.dut.u_daon_lc_shadowed.u_scanmode_sync.OutputsKnown_A 0011137395646513000
tb.dut.u_daon_lc_shadowed.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011137395646513000
tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00211732067000
tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002555205200
tb.dut.u_daon_lc_usb.u_prim_mubi4_sender.OutputsKnown_A 00251208541338082900
tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00211232062000
tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002555205200
tb.dut.u_daon_lc_usb.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050350300
tb.dut.u_daon_lc_usb.u_scanmode_sync.OutputsKnown_A 0011137395646513000
tb.dut.u_daon_lc_usb.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011137395646513000
tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00211732067000
tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002555205200
tb.dut.u_daon_por.u_prim_mubi4_sender.OutputsKnown_A 00523355223141548300
tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic.selKnown0 008497799400
tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002555205200
tb.dut.u_daon_por.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050350300
tb.dut.u_daon_por.u_scanmode_sync.OutputsKnown_A 0011137395646513000
tb.dut.u_daon_por.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011137395646513000
tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00211732067000
tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002555205200
tb.dut.u_daon_por_io.u_prim_mubi4_sender.OutputsKnown_A 00502402703015769000
tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic.selKnown0 008497799400
tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002555205200
tb.dut.u_daon_por_io.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050350300
tb.dut.u_daon_por_io.u_scanmode_sync.OutputsKnown_A 0011137395646513000
tb.dut.u_daon_por_io.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011137395646513000
tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00211732067000
tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002555205200
tb.dut.u_daon_por_io_div2.u_prim_mubi4_sender.OutputsKnown_A 00251210231507555800
tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown0 008497799400
tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002555205200
tb.dut.u_daon_por_io_div2.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050350300
tb.dut.u_daon_por_io_div2.u_scanmode_sync.OutputsKnown_A 0011137395646513000
tb.dut.u_daon_por_io_div2.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011137395646513000
tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00211732067000
tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002555205200
tb.dut.u_daon_por_io_div4.u_prim_mubi4_sender.OutputsKnown_A 0012560289753461900
tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown0 008497799400
tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002555205200
tb.dut.u_daon_por_io_div4.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050350300
tb.dut.u_daon_por_io_div4.u_scanmode_sync.OutputsKnown_A 0011137395646513000
tb.dut.u_daon_por_io_div4.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011137395646513000
tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00211732067000
tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002555205200
tb.dut.u_daon_por_usb.u_prim_mubi4_sender.OutputsKnown_A 00251208541507548600
tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown0 008497799400
tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002555205200
tb.dut.u_daon_por_usb.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050350300
tb.dut.u_daon_por_usb.u_scanmode_sync.OutputsKnown_A 0011137395646513000
tb.dut.u_daon_por_usb.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011137395646513000
tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00211732067000
tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 002555205200
tb.dut.u_daon_sys_io_div4.u_prim_mubi4_sender.OutputsKnown_A 0012560289659450000
tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown0 00211232062000
tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown1 002555205200
tb.dut.u_daon_sys_io_div4.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0050350300
tb.dut.u_daon_sys_io_div4.u_scanmode_sync.OutputsKnown_A 0011137395646513000
tb.dut.u_daon_sys_io_div4.u_scanmode_sync.gen_no_flops.OutputDelay_A 0011137395646513000
tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic.selKnown0 00211232062000
tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic.selKnown1 002555205200
tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic.selKnown0 00211232062000
tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic.selKnown1 002555205200
tb.dut.u_reg.en2addrHit 001189896792611000
tb.dut.u_reg.reAfterRv 001189896792596700
tb.dut.u_reg.rePulse 001189896749448600
tb.dut.u_reg.u_chk.PayLoadWidthCheck 0061861800
tb.dut.u_reg.u_reg_if.AllowedLatency_A 0061861800
tb.dut.u_reg.u_reg_if.MatchedWidthAssert 0061861800
tb.dut.u_reg.u_reg_if.u_err.dataWidthOnly32_A 0061861800
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A 0061861800
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck 0061861800
tb.dut.u_reg.u_rsp_intg_gen.DataWidthCheck_A 0061861800
tb.dut.u_reg.u_rsp_intg_gen.PayLoadWidthCheck 0061861800
tb.dut.u_reg.wePulse 001189896743148100
tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic.selKnown0 00211232062000
tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic.selKnown1 002555205200
tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic.selKnown0 00211232062000
tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic.selKnown1 002555205200


Detail Report for Cover Sequences

Cover Sequences All Matches:
COVER SEQUENCESCATEGORYSEVERITYATTEMPTSALL MATCHESFIRST MATCHESINCOMPLETESRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C 0011899585581058100
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C 0011899585230223021
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C 0011899585231223121
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C 0011899585158515851
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C 001189958581811
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C 0011899585123912391
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C 0011899585108010801
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C 0011899585352635260
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C 001189958545272452720
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C 0011899585427529427529452

Cover Sequences First Matches:
COVER SEQUENCESCATEGORYSEVERITYATTEMPTSALL MATCHESFIRST MATCHESINCOMPLETESRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C 0011899585581058100
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C 0011899585230223021
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C 0011899585231223121
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C 0011899585158515851
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C 001189958581811
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C 0011899585123912391
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C 0011899585108010801
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C 0011899585352635260
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C 001189958545272452720
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C 0011899585427529427529452

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