Group : rstmgr_env_pkg::rstmgr_env_cov::reset_stretcher_cg
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Group : rstmgr_env_pkg::rstmgr_env_cov::reset_stretcher_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv



Summary for Group rstmgr_env_pkg::rstmgr_env_cov::reset_stretcher_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00


Variables for Group rstmgr_env_pkg::rstmgr_env_cov::reset_stretcher_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
count_cp 4 0 4 100.00 100 1 1 0
length_cp 8 0 8 100.00 100 1 1 0


Summary for Variable count_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for count_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
others 9107 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
cb[0] 1290 1 T1 3 T2 1 T3 1
cb[1] 1157 1 T1 4 T4 4 T7 4
cb[2] 1060 1 T1 4 T4 4 T7 1
cb[3] 983 1 T1 4 T4 4 T9 4



Summary for Variable length_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for length_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
others 11114 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
lb[0] 358 1 T9 1 T24 2 T14 4
lb[1] 348 1 T1 1 T7 2 T9 2
lb[2] 294 1 T1 3 T9 3 T49 1
lb[3] 320 1 T1 1 T4 1 T7 1
lb[4] 304 1 T1 1 T7 2 T9 1
lb[5] 303 1 T7 2 T9 2 T14 6
lb[6] 318 1 T4 1 T9 1 T14 3
lb[7] 238 1 T1 2 T4 1 T9 1

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