Group : rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv



Summary for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 16 0 16 100.00


Variables for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
enable_cp 2 0 2 100.00 100 1 1 2
reset_info_cp 8 0 8 100.00 100 1 1 0


Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
capture_cross 16 0 16 100.00 100 1 1 0


Summary for Variable enable_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 7661 1 T1 19 T4 21 T9 151
auto[1] 10772 1 T1 82 T3 4 T4 28



Summary for Variable reset_info_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for reset_info_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
others 5823 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
reset_info_cp[1] 6157 1 T1 27 T2 1 T3 2
reset_info_cp[2] 2834 1 T1 15 T3 1 T4 7
reset_info_cp[4] 3701 1 T1 17 T3 1 T4 12
reset_info_cp[8] 112 1 T9 2 T49 2 T52 1
reset_info_cp[16] 129 1 T4 2 T9 2 T49 6
reset_info_cp[32] 93 1 T8 1 T9 1 T49 2
reset_info_cp[64] 111 1 T9 1 T13 1 T49 2
reset_info_cp[128] 91 1 T1 1 T9 2 T35 1



Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for capture_cross

Bins
reset_info_cpenable_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
reset_info_cp[1] auto[0] 2932 1 T1 19 T4 7 T9 45
reset_info_cp[1] auto[1] 2607 1 T1 7 T3 1 T4 10
reset_info_cp[2] auto[0] 831 1 T4 4 T9 29 T23 3
reset_info_cp[2] auto[1] 2003 1 T1 15 T3 1 T4 3
reset_info_cp[4] auto[0] 1273 1 T4 6 T9 24 T23 6
reset_info_cp[4] auto[1] 2428 1 T1 17 T3 1 T4 6
reset_info_cp[8] auto[0] 51 1 T9 1 T49 2 T52 1
reset_info_cp[8] auto[1] 61 1 T9 1 T26 1 T28 1
reset_info_cp[16] auto[0] 45 1 T9 1 T49 2 T111 1
reset_info_cp[16] auto[1] 84 1 T4 2 T9 1 T49 4
reset_info_cp[32] auto[0] 42 1 T9 1 T45 1 T111 2
reset_info_cp[32] auto[1] 51 1 T8 1 T49 2 T27 1
reset_info_cp[64] auto[0] 47 1 T9 1 T49 1 T130 1
reset_info_cp[64] auto[1] 64 1 T13 1 T49 1 T27 1
reset_info_cp[128] auto[0] 35 1 T9 1 T111 1 T139 2
reset_info_cp[128] auto[1] 56 1 T1 1 T9 1 T35 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%