Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.88 99.83 99.46 98.77


Total test records in report: 618
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T501 /workspace/coverage/default/12.rstmgr_por_stretcher.1784169980 Jan 10 12:46:20 PM PST 24 Jan 10 12:47:40 PM PST 24 167080828 ps
T502 /workspace/coverage/default/36.rstmgr_sw_rst.3482071199 Jan 10 12:32:03 PM PST 24 Jan 10 12:32:50 PM PST 24 121230301 ps
T503 /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.3175875352 Jan 10 12:47:04 PM PST 24 Jan 10 12:48:31 PM PST 24 1895132669 ps
T504 /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.3102477936 Jan 10 12:31:19 PM PST 24 Jan 10 12:32:05 PM PST 24 112570904 ps
T505 /workspace/coverage/default/23.rstmgr_smoke.1412275672 Jan 10 12:47:26 PM PST 24 Jan 10 12:48:49 PM PST 24 117455374 ps
T506 /workspace/coverage/default/35.rstmgr_smoke.1576468851 Jan 10 12:29:52 PM PST 24 Jan 10 12:30:30 PM PST 24 253405316 ps
T507 /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.3039701837 Jan 10 12:57:17 PM PST 24 Jan 10 12:58:31 PM PST 24 104413521 ps
T508 /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.2442765049 Jan 10 12:37:29 PM PST 24 Jan 10 12:38:10 PM PST 24 1223333868 ps
T509 /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.660157684 Jan 10 12:28:59 PM PST 24 Jan 10 12:29:19 PM PST 24 121491819 ps
T510 /workspace/coverage/default/41.rstmgr_stress_all.2641002557 Jan 10 12:30:27 PM PST 24 Jan 10 12:31:35 PM PST 24 6844716552 ps
T511 /workspace/coverage/default/27.rstmgr_sw_rst.3600082809 Jan 10 12:28:16 PM PST 24 Jan 10 12:28:31 PM PST 24 113166129 ps
T512 /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.3616114445 Jan 10 12:37:53 PM PST 24 Jan 10 12:38:27 PM PST 24 244407183 ps
T513 /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.1336509363 Jan 10 12:27:34 PM PST 24 Jan 10 12:27:41 PM PST 24 102314960 ps
T514 /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.3101611490 Jan 10 12:41:14 PM PST 24 Jan 10 12:42:16 PM PST 24 173073079 ps
T515 /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.3970445746 Jan 10 12:29:46 PM PST 24 Jan 10 12:30:20 PM PST 24 130040304 ps
T516 /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.2256118849 Jan 10 12:30:28 PM PST 24 Jan 10 12:31:10 PM PST 24 267998886 ps
T517 /workspace/coverage/default/9.rstmgr_sw_rst.813717299 Jan 10 12:27:47 PM PST 24 Jan 10 12:28:01 PM PST 24 269277792 ps
T518 /workspace/coverage/default/39.rstmgr_alert_test.1496366615 Jan 10 12:30:29 PM PST 24 Jan 10 12:31:11 PM PST 24 63742604 ps
T519 /workspace/coverage/default/49.rstmgr_por_stretcher.1158512580 Jan 10 12:30:01 PM PST 24 Jan 10 12:30:44 PM PST 24 160529086 ps
T520 /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.50147371 Jan 10 12:28:38 PM PST 24 Jan 10 12:28:56 PM PST 24 1237007110 ps
T521 /workspace/coverage/default/37.rstmgr_por_stretcher.645282151 Jan 10 12:28:19 PM PST 24 Jan 10 12:28:33 PM PST 24 170655103 ps
T522 /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.956507705 Jan 10 12:28:28 PM PST 24 Jan 10 12:28:40 PM PST 24 145866283 ps
T523 /workspace/coverage/default/43.rstmgr_reset.1925662232 Jan 10 12:32:04 PM PST 24 Jan 10 12:32:54 PM PST 24 847820756 ps
T524 /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.3622409806 Jan 10 12:28:48 PM PST 24 Jan 10 12:29:04 PM PST 24 246199396 ps
T525 /workspace/coverage/default/7.rstmgr_alert_test.3238973351 Jan 10 12:45:08 PM PST 24 Jan 10 12:46:35 PM PST 24 70278450 ps
T526 /workspace/coverage/default/18.rstmgr_sw_rst.2036059812 Jan 10 12:52:13 PM PST 24 Jan 10 12:53:30 PM PST 24 390162149 ps
T527 /workspace/coverage/default/46.rstmgr_reset.389990178 Jan 10 12:27:28 PM PST 24 Jan 10 12:27:37 PM PST 24 1047955614 ps
T528 /workspace/coverage/default/46.rstmgr_smoke.3002758542 Jan 10 12:31:20 PM PST 24 Jan 10 12:32:07 PM PST 24 125445950 ps
T529 /workspace/coverage/default/49.rstmgr_smoke.3541245223 Jan 10 12:27:59 PM PST 24 Jan 10 12:28:14 PM PST 24 112482761 ps
T530 /workspace/coverage/default/35.rstmgr_reset.3751818333 Jan 10 12:29:31 PM PST 24 Jan 10 12:30:02 PM PST 24 1846136021 ps
T531 /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.285644468 Jan 10 12:29:02 PM PST 24 Jan 10 12:29:26 PM PST 24 1221503656 ps
T532 /workspace/coverage/default/48.rstmgr_alert_test.1708890347 Jan 10 12:29:48 PM PST 24 Jan 10 12:30:22 PM PST 24 69447938 ps
T533 /workspace/coverage/default/14.rstmgr_smoke.1217676387 Jan 10 12:44:07 PM PST 24 Jan 10 12:45:34 PM PST 24 202536170 ps
T534 /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.1166618746 Jan 10 12:49:06 PM PST 24 Jan 10 12:50:43 PM PST 24 1228088043 ps
T535 /workspace/coverage/default/27.rstmgr_reset.2849262727 Jan 10 12:28:17 PM PST 24 Jan 10 12:28:36 PM PST 24 1643553383 ps
T536 /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.3364735706 Jan 10 12:30:48 PM PST 24 Jan 10 12:31:34 PM PST 24 123705560 ps
T537 /workspace/coverage/default/16.rstmgr_sw_rst.364769192 Jan 10 12:35:29 PM PST 24 Jan 10 12:35:59 PM PST 24 467198665 ps
T538 /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.1102454746 Jan 10 12:44:59 PM PST 24 Jan 10 12:46:22 PM PST 24 139494939 ps
T539 /workspace/coverage/default/27.rstmgr_smoke.1864140308 Jan 10 12:30:48 PM PST 24 Jan 10 12:31:35 PM PST 24 197787847 ps
T540 /workspace/coverage/default/25.rstmgr_reset.3767377064 Jan 10 12:34:49 PM PST 24 Jan 10 12:35:37 PM PST 24 1732453171 ps
T541 /workspace/coverage/default/23.rstmgr_alert_test.622860788 Jan 10 12:44:53 PM PST 24 Jan 10 12:46:15 PM PST 24 67897647 ps
T542 /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.3513365724 Jan 10 12:46:29 PM PST 24 Jan 10 12:48:09 PM PST 24 1227748447 ps
T543 /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.1371275917 Jan 10 12:30:47 PM PST 24 Jan 10 12:31:33 PM PST 24 243444625 ps
T544 /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.3774332790 Jan 10 12:28:01 PM PST 24 Jan 10 12:28:18 PM PST 24 154952820 ps
T545 /workspace/coverage/default/9.rstmgr_por_stretcher.1989921290 Jan 10 12:54:15 PM PST 24 Jan 10 12:55:22 PM PST 24 126487199 ps
T546 /workspace/coverage/default/47.rstmgr_stress_all.3678892781 Jan 10 12:31:14 PM PST 24 Jan 10 12:32:34 PM PST 24 11293322313 ps
T547 /workspace/coverage/default/34.rstmgr_por_stretcher.1094066974 Jan 10 12:50:06 PM PST 24 Jan 10 12:51:30 PM PST 24 188953457 ps
T548 /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.1116925644 Jan 10 12:44:04 PM PST 24 Jan 10 12:45:31 PM PST 24 99700440 ps
T549 /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.1601445650 Jan 10 12:46:11 PM PST 24 Jan 10 12:47:31 PM PST 24 165829919 ps
T550 /workspace/coverage/default/33.rstmgr_sw_rst.1848282330 Jan 10 12:36:18 PM PST 24 Jan 10 12:36:55 PM PST 24 151022125 ps
T551 /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.3603996041 Jan 10 12:27:38 PM PST 24 Jan 10 12:27:47 PM PST 24 250071251 ps
T552 /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.2818326485 Jan 10 12:38:42 PM PST 24 Jan 10 12:39:16 PM PST 24 144205413 ps
T553 /workspace/coverage/default/11.rstmgr_por_stretcher.25800918 Jan 10 12:28:39 PM PST 24 Jan 10 12:28:52 PM PST 24 143857530 ps
T554 /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.165815262 Jan 10 12:30:59 PM PST 24 Jan 10 12:31:48 PM PST 24 158907819 ps
T555 /workspace/coverage/default/17.rstmgr_alert_test.2188467675 Jan 10 12:28:06 PM PST 24 Jan 10 12:28:22 PM PST 24 56687986 ps
T556 /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.3464091494 Jan 10 12:28:25 PM PST 24 Jan 10 12:28:37 PM PST 24 247910206 ps
T557 /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.3329866238 Jan 10 12:49:07 PM PST 24 Jan 10 12:50:45 PM PST 24 230624856 ps
T558 /workspace/coverage/default/10.rstmgr_smoke.1929222248 Jan 10 12:28:43 PM PST 24 Jan 10 12:28:59 PM PST 24 255533605 ps
T559 /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.3941967857 Jan 10 12:29:04 PM PST 24 Jan 10 12:29:25 PM PST 24 244081966 ps
T560 /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.1284625234 Jan 10 12:42:42 PM PST 24 Jan 10 12:43:58 PM PST 24 142081051 ps
T561 /workspace/coverage/default/18.rstmgr_alert_test.1408875642 Jan 10 12:29:55 PM PST 24 Jan 10 12:30:34 PM PST 24 69154661 ps
T562 /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.1984560013 Jan 10 12:52:55 PM PST 24 Jan 10 12:54:10 PM PST 24 161820548 ps
T563 /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.998690746 Jan 10 12:27:27 PM PST 24 Jan 10 12:27:33 PM PST 24 244081893 ps
T564 /workspace/coverage/default/36.rstmgr_smoke.2241695792 Jan 10 12:28:56 PM PST 24 Jan 10 12:29:16 PM PST 24 232608230 ps
T565 /workspace/coverage/default/42.rstmgr_alert_test.449030443 Jan 10 12:30:32 PM PST 24 Jan 10 12:31:15 PM PST 24 74399665 ps
T566 /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.1161504928 Jan 10 12:31:20 PM PST 24 Jan 10 12:32:07 PM PST 24 252617329 ps
T567 /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.3160363193 Jan 10 12:29:13 PM PST 24 Jan 10 12:29:36 PM PST 24 76775365 ps
T568 /workspace/coverage/default/40.rstmgr_reset.853315061 Jan 10 12:27:37 PM PST 24 Jan 10 12:27:51 PM PST 24 1911841004 ps
T569 /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.463546554 Jan 10 12:30:28 PM PST 24 Jan 10 12:31:11 PM PST 24 244074448 ps
T570 /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.1659137572 Jan 10 12:49:57 PM PST 24 Jan 10 12:51:40 PM PST 24 229619999 ps
T571 /workspace/coverage/default/47.rstmgr_sw_rst.3558574372 Jan 10 12:30:19 PM PST 24 Jan 10 12:31:00 PM PST 24 126065652 ps
T572 /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.710760757 Jan 10 12:28:37 PM PST 24 Jan 10 12:28:50 PM PST 24 166570247 ps
T573 /workspace/coverage/default/19.rstmgr_smoke.3126101450 Jan 10 12:46:24 PM PST 24 Jan 10 12:47:44 PM PST 24 259109571 ps
T574 /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.2381379315 Jan 10 12:29:17 PM PST 24 Jan 10 12:29:46 PM PST 24 1214090509 ps
T575 /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.1663727351 Jan 10 12:40:39 PM PST 24 Jan 10 12:41:25 PM PST 24 181571219 ps
T576 /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.3139648542 Jan 10 12:28:55 PM PST 24 Jan 10 12:29:15 PM PST 24 244192872 ps
T577 /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.2558381601 Jan 10 01:04:02 PM PST 24 Jan 10 01:05:25 PM PST 24 148407161 ps
T578 /workspace/coverage/default/23.rstmgr_sw_rst.2849712991 Jan 10 12:40:11 PM PST 24 Jan 10 12:41:00 PM PST 24 288291181 ps
T579 /workspace/coverage/default/0.rstmgr_stress_all.1827314638 Jan 10 12:48:26 PM PST 24 Jan 10 12:49:51 PM PST 24 262280323 ps
T580 /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.647764991 Jan 10 12:26:13 PM PST 24 Jan 10 12:26:19 PM PST 24 243499094 ps
T581 /workspace/coverage/default/13.rstmgr_por_stretcher.2006899293 Jan 10 12:28:38 PM PST 24 Jan 10 12:28:51 PM PST 24 155780117 ps
T582 /workspace/coverage/default/25.rstmgr_sw_rst.1789418705 Jan 10 01:04:36 PM PST 24 Jan 10 01:06:00 PM PST 24 268785565 ps
T583 /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.1225168793 Jan 10 12:34:26 PM PST 24 Jan 10 12:35:04 PM PST 24 105033857 ps
T584 /workspace/coverage/default/34.rstmgr_smoke.2162513525 Jan 10 12:36:05 PM PST 24 Jan 10 12:36:33 PM PST 24 118074550 ps
T585 /workspace/coverage/default/18.rstmgr_smoke.985890618 Jan 10 12:39:15 PM PST 24 Jan 10 12:39:45 PM PST 24 109571125 ps
T586 /workspace/coverage/default/15.rstmgr_reset.2981078100 Jan 10 01:05:41 PM PST 24 Jan 10 01:07:39 PM PST 24 1006326719 ps
T587 /workspace/coverage/default/14.rstmgr_por_stretcher.2696951051 Jan 10 12:41:01 PM PST 24 Jan 10 12:41:59 PM PST 24 235582636 ps
T588 /workspace/coverage/default/44.rstmgr_alert_test.1414540051 Jan 10 12:27:28 PM PST 24 Jan 10 12:27:34 PM PST 24 73440353 ps
T589 /workspace/coverage/default/16.rstmgr_smoke.3744605144 Jan 10 12:46:32 PM PST 24 Jan 10 12:47:51 PM PST 24 226073919 ps
T590 /workspace/coverage/default/36.rstmgr_stress_all.1147534112 Jan 10 12:26:16 PM PST 24 Jan 10 12:26:32 PM PST 24 3304591683 ps
T591 /workspace/coverage/default/25.rstmgr_smoke.557516247 Jan 10 12:29:07 PM PST 24 Jan 10 12:29:30 PM PST 24 206332238 ps
T592 /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.706310087 Jan 10 12:38:05 PM PST 24 Jan 10 12:38:47 PM PST 24 1897923145 ps
T593 /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.2295238500 Jan 10 12:31:59 PM PST 24 Jan 10 12:32:53 PM PST 24 2364516561 ps
T594 /workspace/coverage/default/32.rstmgr_alert_test.2733106103 Jan 10 12:47:04 PM PST 24 Jan 10 12:48:26 PM PST 24 73072775 ps
T595 /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.2968278611 Jan 10 01:06:34 PM PST 24 Jan 10 01:07:58 PM PST 24 1220124055 ps
T596 /workspace/coverage/default/26.rstmgr_sw_rst.3063448848 Jan 10 01:02:28 PM PST 24 Jan 10 01:03:57 PM PST 24 137821257 ps
T597 /workspace/coverage/default/17.rstmgr_reset.3811663505 Jan 10 12:59:47 PM PST 24 Jan 10 01:01:20 PM PST 24 1513536649 ps
T598 /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.1352010871 Jan 10 12:40:02 PM PST 24 Jan 10 12:40:47 PM PST 24 156574678 ps
T599 /workspace/coverage/default/4.rstmgr_por_stretcher.215875476 Jan 10 12:31:41 PM PST 24 Jan 10 12:32:32 PM PST 24 212323541 ps
T600 /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.3596376072 Jan 10 12:28:00 PM PST 24 Jan 10 12:28:24 PM PST 24 2373003293 ps
T601 /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.1754391983 Jan 10 12:31:03 PM PST 24 Jan 10 12:31:51 PM PST 24 211289341 ps
T602 /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.3445145363 Jan 10 12:28:04 PM PST 24 Jan 10 12:28:20 PM PST 24 185447925 ps
T603 /workspace/coverage/default/18.rstmgr_stress_all.414761291 Jan 10 12:35:08 PM PST 24 Jan 10 12:35:57 PM PST 24 3203297689 ps
T604 /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.689196139 Jan 10 12:27:28 PM PST 24 Jan 10 12:27:34 PM PST 24 105360007 ps
T605 /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.3641293082 Jan 10 12:28:02 PM PST 24 Jan 10 12:28:18 PM PST 24 143915089 ps
T606 /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.851626371 Jan 10 12:31:17 PM PST 24 Jan 10 12:32:09 PM PST 24 1901288203 ps
T607 /workspace/coverage/default/38.rstmgr_alert_test.27078788 Jan 10 12:27:08 PM PST 24 Jan 10 12:27:15 PM PST 24 64775887 ps
T608 /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.4199749466 Jan 10 12:30:06 PM PST 24 Jan 10 12:30:55 PM PST 24 2365139243 ps
T609 /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.1298070890 Jan 10 01:00:49 PM PST 24 Jan 10 01:02:35 PM PST 24 1893835433 ps
T610 /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.691028060 Jan 10 12:40:36 PM PST 24 Jan 10 12:41:20 PM PST 24 216734305 ps
T611 /workspace/coverage/default/1.rstmgr_alert_test.2426792775 Jan 10 12:45:58 PM PST 24 Jan 10 12:47:20 PM PST 24 70355220 ps
T612 /workspace/coverage/default/38.rstmgr_smoke.4228090589 Jan 10 12:30:02 PM PST 24 Jan 10 12:30:45 PM PST 24 120829383 ps
T613 /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.3419201415 Jan 10 12:31:43 PM PST 24 Jan 10 12:32:38 PM PST 24 1887757273 ps
T614 /workspace/coverage/default/48.rstmgr_smoke.3205997675 Jan 10 12:31:15 PM PST 24 Jan 10 12:32:01 PM PST 24 114317784 ps
T615 /workspace/coverage/default/32.rstmgr_sw_rst.2791049962 Jan 10 12:28:24 PM PST 24 Jan 10 12:28:37 PM PST 24 367817712 ps
T616 /workspace/coverage/default/10.rstmgr_alert_test.3934887609 Jan 10 12:29:04 PM PST 24 Jan 10 12:29:25 PM PST 24 77205760 ps
T617 /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.855289617 Jan 10 12:54:15 PM PST 24 Jan 10 12:55:29 PM PST 24 2163010310 ps
T618 /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.942308750 Jan 10 12:27:29 PM PST 24 Jan 10 12:27:35 PM PST 24 146705273 ps

Test location /workspace/coverage/default/48.rstmgr_stress_all.4089607213
Short name T9
Test name
Test status
Simulation time 5550910671 ps
CPU time 26.53 seconds
Started Jan 10 12:28:05 PM PST 24
Finished Jan 10 12:28:47 PM PST 24
Peak memory 199412 kb
Host smart-01d1b249-fd17-4131-b6dc-54c7f47d6172
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089607213 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.4089607213
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.2142506886
Short name T3
Test name
Test status
Simulation time 220867923 ps
CPU time 1.42 seconds
Started Jan 10 12:45:16 PM PST 24
Finished Jan 10 12:46:39 PM PST 24
Peak memory 199500 kb
Host smart-086ca00d-8619-4e36-a504-cc469ce988f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142506886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.2142506886
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1387123383
Short name T70
Test name
Test status
Simulation time 177499671 ps
CPU time 1.39 seconds
Started Jan 10 12:26:48 PM PST 24
Finished Jan 10 12:26:54 PM PST 24
Peak memory 198048 kb
Host smart-75f232ef-8be4-4c68-95a8-1fb524c98e15
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387123383 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.1387123383
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.2600508013
Short name T25
Test name
Test status
Simulation time 139990406 ps
CPU time 1.59 seconds
Started Jan 10 12:30:25 PM PST 24
Finished Jan 10 12:31:08 PM PST 24
Peak memory 198944 kb
Host smart-99981025-8e16-45ca-b453-39dc257bb5ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600508013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.2600508013
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.153524328
Short name T76
Test name
Test status
Simulation time 8347679234 ps
CPU time 13.63 seconds
Started Jan 10 01:23:54 PM PST 24
Finished Jan 10 01:24:17 PM PST 24
Peak memory 220472 kb
Host smart-bbf13091-ae69-43c8-8f3f-45ec5411cba5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153524328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.153524328
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.3189014876
Short name T56
Test name
Test status
Simulation time 1874042227 ps
CPU time 6.98 seconds
Started Jan 10 12:40:27 PM PST 24
Finished Jan 10 12:41:20 PM PST 24
Peak memory 221316 kb
Host smart-53973f74-f15f-45c2-bcac-9a90ba228e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189014876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.3189014876
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.727735
Short name T103
Test name
Test status
Simulation time 802713568 ps
CPU time 2.67 seconds
Started Jan 10 12:28:22 PM PST 24
Finished Jan 10 12:28:37 PM PST 24
Peak memory 198500 kb
Host smart-1d2d9c40-3b50-4165-833a-edd3c1d73a95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_err.727735
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.1200485729
Short name T13
Test name
Test status
Simulation time 105855441 ps
CPU time 0.93 seconds
Started Jan 10 12:30:46 PM PST 24
Finished Jan 10 12:31:31 PM PST 24
Peak memory 198980 kb
Host smart-d68cbffe-53a6-418c-97d8-9e6a66753ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200485729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.1200485729
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.3970221051
Short name T72
Test name
Test status
Simulation time 110069181 ps
CPU time 1.51 seconds
Started Jan 10 12:26:33 PM PST 24
Finished Jan 10 12:26:38 PM PST 24
Peak memory 198768 kb
Host smart-19be6f40-3fb5-4d9d-b1a4-1254ad055c80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970221051 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.3970221051
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.2788267982
Short name T1
Test name
Test status
Simulation time 1893258389 ps
CPU time 7.07 seconds
Started Jan 10 12:40:38 PM PST 24
Finished Jan 10 12:41:29 PM PST 24
Peak memory 216100 kb
Host smart-68d4089f-12cc-454a-a331-4f8a2473f44b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788267982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.2788267982
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.2560269101
Short name T66
Test name
Test status
Simulation time 220653818 ps
CPU time 1.43 seconds
Started Jan 10 12:30:32 PM PST 24
Finished Jan 10 12:31:16 PM PST 24
Peak memory 199308 kb
Host smart-aad27d1d-6b44-4f13-8f92-7d8b9ad33369
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560269101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.2560269101
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.3422851452
Short name T49
Test name
Test status
Simulation time 16548830586 ps
CPU time 49.33 seconds
Started Jan 10 12:27:59 PM PST 24
Finished Jan 10 12:29:04 PM PST 24
Peak memory 198636 kb
Host smart-f275557e-fa27-4508-b784-7e5afd943a76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422851452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.3422851452
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.2685181672
Short name T120
Test name
Test status
Simulation time 1612089405 ps
CPU time 4.3 seconds
Started Jan 10 12:29:35 PM PST 24
Finished Jan 10 12:30:06 PM PST 24
Peak memory 199040 kb
Host smart-f420c297-faa7-44f5-8369-86f8bc14bb2c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685181672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.2685181672
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.823033562
Short name T37
Test name
Test status
Simulation time 2375301310 ps
CPU time 9.4 seconds
Started Jan 10 12:54:38 PM PST 24
Finished Jan 10 12:55:52 PM PST 24
Peak memory 216556 kb
Host smart-41ba0ec5-9124-4819-9966-b7f576186275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823033562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.823033562
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.3387278671
Short name T202
Test name
Test status
Simulation time 485500492 ps
CPU time 3.24 seconds
Started Jan 10 12:26:06 PM PST 24
Finished Jan 10 12:26:15 PM PST 24
Peak memory 199272 kb
Host smart-a629fdf6-d1da-409b-a1bf-5512f9bce0be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387278671 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.3387278671
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.3496226439
Short name T153
Test name
Test status
Simulation time 64996975 ps
CPU time 0.7 seconds
Started Jan 10 12:31:14 PM PST 24
Finished Jan 10 12:32:00 PM PST 24
Peak memory 198824 kb
Host smart-e6799a4f-9ca2-4ae6-b0c3-7013e67b3285
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496226439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.3496226439
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.2403100390
Short name T71
Test name
Test status
Simulation time 199496955 ps
CPU time 1.27 seconds
Started Jan 10 12:28:05 PM PST 24
Finished Jan 10 12:28:22 PM PST 24
Peak memory 199416 kb
Host smart-5d1dcf57-5c08-4679-b130-cf50f2e3cde2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403100390 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.2403100390
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.1856254627
Short name T17
Test name
Test status
Simulation time 183955854 ps
CPU time 0.83 seconds
Started Jan 10 12:34:21 PM PST 24
Finished Jan 10 12:34:55 PM PST 24
Peak memory 198928 kb
Host smart-cb65798d-d032-406f-8e2a-b23c6a814f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856254627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.1856254627
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.1450521286
Short name T188
Test name
Test status
Simulation time 104953421 ps
CPU time 1.29 seconds
Started Jan 10 12:22:56 PM PST 24
Finished Jan 10 12:22:58 PM PST 24
Peak memory 199376 kb
Host smart-4c7870ac-2e44-4f38-b3f3-69a131aa041b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450521286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.1
450521286
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.386937027
Short name T215
Test name
Test status
Simulation time 1992258522 ps
CPU time 9.68 seconds
Started Jan 10 12:25:55 PM PST 24
Finished Jan 10 12:26:06 PM PST 24
Peak memory 199508 kb
Host smart-de2d74d5-0a6f-4e15-b344-e7e5408829df
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386937027 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.386937027
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.1090526204
Short name T200
Test name
Test status
Simulation time 152831804 ps
CPU time 1 seconds
Started Jan 10 12:27:40 PM PST 24
Finished Jan 10 12:27:50 PM PST 24
Peak memory 198360 kb
Host smart-d8471391-a384-4828-9384-c2178afdba26
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090526204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.1
090526204
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.2463305217
Short name T167
Test name
Test status
Simulation time 160066650 ps
CPU time 1.12 seconds
Started Jan 10 12:28:05 PM PST 24
Finished Jan 10 12:28:22 PM PST 24
Peak memory 199484 kb
Host smart-e2e58a92-abe8-489a-a670-e2deb5985f29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463305217 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.2463305217
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.768214843
Short name T181
Test name
Test status
Simulation time 55581140 ps
CPU time 0.74 seconds
Started Jan 10 12:28:30 PM PST 24
Finished Jan 10 12:28:42 PM PST 24
Peak memory 197928 kb
Host smart-f7311c54-4dbf-4249-93c3-e72a8753e257
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768214843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.768214843
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3710492891
Short name T211
Test name
Test status
Simulation time 261360550 ps
CPU time 1.44 seconds
Started Jan 10 12:23:32 PM PST 24
Finished Jan 10 12:23:34 PM PST 24
Peak memory 199516 kb
Host smart-f8d36516-421a-480c-afa7-4c57a0e7f0f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710492891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.3710492891
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.1531728449
Short name T126
Test name
Test status
Simulation time 233870016 ps
CPU time 1.78 seconds
Started Jan 10 12:29:54 PM PST 24
Finished Jan 10 12:30:41 PM PST 24
Peak memory 207508 kb
Host smart-5325ad17-f74e-4de6-85fe-ad0138f3d3e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531728449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.1531728449
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.4135363835
Short name T173
Test name
Test status
Simulation time 792702154 ps
CPU time 2.86 seconds
Started Jan 10 12:28:31 PM PST 24
Finished Jan 10 12:28:44 PM PST 24
Peak memory 198852 kb
Host smart-7e82dd2a-c5cd-4287-a5a1-a054fa708119
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135363835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.4135363835
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.2757806441
Short name T67
Test name
Test status
Simulation time 110278675 ps
CPU time 1.28 seconds
Started Jan 10 12:28:05 PM PST 24
Finished Jan 10 12:28:22 PM PST 24
Peak memory 199120 kb
Host smart-c754aa49-ffbf-44dd-a9a3-8049e0213538
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757806441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.2
757806441
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.4228846081
Short name T165
Test name
Test status
Simulation time 1183455317 ps
CPU time 5.56 seconds
Started Jan 10 12:28:02 PM PST 24
Finished Jan 10 12:28:23 PM PST 24
Peak memory 199824 kb
Host smart-edd4c154-7160-4ada-895a-e63420f08c0c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228846081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.4
228846081
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.2313865835
Short name T179
Test name
Test status
Simulation time 107070845 ps
CPU time 0.82 seconds
Started Jan 10 12:28:07 PM PST 24
Finished Jan 10 12:28:24 PM PST 24
Peak memory 199348 kb
Host smart-e6aaa129-35d6-43f0-b823-42b54a0709fa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313865835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.2
313865835
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.1293999645
Short name T226
Test name
Test status
Simulation time 66153485 ps
CPU time 0.74 seconds
Started Jan 10 12:28:05 PM PST 24
Finished Jan 10 12:28:21 PM PST 24
Peak memory 199284 kb
Host smart-8942defa-3191-4512-ac7e-abb868431392
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293999645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.1293999645
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.875658823
Short name T209
Test name
Test status
Simulation time 219654962 ps
CPU time 1.65 seconds
Started Jan 10 12:28:54 PM PST 24
Finished Jan 10 12:29:14 PM PST 24
Peak memory 199444 kb
Host smart-8761504f-c416-4491-89b6-4a26d51147f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875658823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.875658823
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3489832021
Short name T127
Test name
Test status
Simulation time 782826749 ps
CPU time 3.13 seconds
Started Jan 10 12:21:56 PM PST 24
Finished Jan 10 12:22:00 PM PST 24
Peak memory 199940 kb
Host smart-f4027b8f-621f-43e5-b3ec-f5b8bb21aae5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489832021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.3489832021
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1108667851
Short name T99
Test name
Test status
Simulation time 183776935 ps
CPU time 1.27 seconds
Started Jan 10 12:27:29 PM PST 24
Finished Jan 10 12:27:35 PM PST 24
Peak memory 199448 kb
Host smart-ce5f5c1f-af44-4150-813f-396fb9d4c7a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108667851 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.1108667851
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.3282223821
Short name T171
Test name
Test status
Simulation time 68998998 ps
CPU time 0.73 seconds
Started Jan 10 12:29:35 PM PST 24
Finished Jan 10 12:30:03 PM PST 24
Peak memory 199104 kb
Host smart-cff2add6-6dcf-4bf1-9e63-16c80f2b337f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282223821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.3282223821
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.223832045
Short name T195
Test name
Test status
Simulation time 216408224 ps
CPU time 1.45 seconds
Started Jan 10 12:26:59 PM PST 24
Finished Jan 10 12:27:08 PM PST 24
Peak memory 199564 kb
Host smart-01f9ed19-a853-471f-860e-3a50c2c1ec47
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223832045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_sa
me_csr_outstanding.223832045
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.1636655307
Short name T190
Test name
Test status
Simulation time 243663804 ps
CPU time 1.77 seconds
Started Jan 10 12:30:03 PM PST 24
Finished Jan 10 12:30:46 PM PST 24
Peak memory 197432 kb
Host smart-ca406109-bc2d-4532-8a65-48dc79708f4d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636655307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.1636655307
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.280513642
Short name T214
Test name
Test status
Simulation time 175611147 ps
CPU time 1.09 seconds
Started Jan 10 12:29:33 PM PST 24
Finished Jan 10 12:30:00 PM PST 24
Peak memory 199232 kb
Host smart-ff9a9a5b-be8b-43df-bb0f-13ee73683064
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280513642 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.280513642
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.3565563041
Short name T189
Test name
Test status
Simulation time 62064742 ps
CPU time 0.74 seconds
Started Jan 10 12:23:41 PM PST 24
Finished Jan 10 12:23:43 PM PST 24
Peak memory 199420 kb
Host smart-f2484ec3-332b-479d-98cf-ba6d1f0140a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565563041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.3565563041
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.2519572393
Short name T117
Test name
Test status
Simulation time 131156997 ps
CPU time 1.18 seconds
Started Jan 10 12:29:33 PM PST 24
Finished Jan 10 12:30:01 PM PST 24
Peak memory 199240 kb
Host smart-a832c59a-e439-4a07-94ea-5ce272430774
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519572393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.2519572393
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.3811859361
Short name T204
Test name
Test status
Simulation time 372077852 ps
CPU time 2.44 seconds
Started Jan 10 12:23:50 PM PST 24
Finished Jan 10 12:23:54 PM PST 24
Peak memory 198456 kb
Host smart-a50cd8c8-de66-438d-808d-30d486191290
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811859361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.3811859361
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1707830462
Short name T137
Test name
Test status
Simulation time 408566106 ps
CPU time 1.61 seconds
Started Jan 10 12:29:17 PM PST 24
Finished Jan 10 12:29:43 PM PST 24
Peak memory 198776 kb
Host smart-4e9ff2d5-afbd-4f23-a7f9-caa5733e9599
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707830462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.1707830462
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.2777055082
Short name T102
Test name
Test status
Simulation time 129983301 ps
CPU time 1.14 seconds
Started Jan 10 12:27:08 PM PST 24
Finished Jan 10 12:27:15 PM PST 24
Peak memory 199672 kb
Host smart-de444ec5-c797-4535-875a-cc0d96d05932
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777055082 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.2777055082
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.928020690
Short name T206
Test name
Test status
Simulation time 75690350 ps
CPU time 0.76 seconds
Started Jan 10 12:26:52 PM PST 24
Finished Jan 10 12:26:57 PM PST 24
Peak memory 199400 kb
Host smart-6dbe3c7b-0b69-46ab-8971-8a5d2a57f639
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928020690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.928020690
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.3531384882
Short name T224
Test name
Test status
Simulation time 101982060 ps
CPU time 1.3 seconds
Started Jan 10 12:26:53 PM PST 24
Finished Jan 10 12:27:00 PM PST 24
Peak memory 199576 kb
Host smart-3772400a-98b4-4e1d-8b7e-2f5bdfc2ca2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531384882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.3531384882
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.3841299696
Short name T97
Test name
Test status
Simulation time 111991855 ps
CPU time 1.55 seconds
Started Jan 10 12:26:51 PM PST 24
Finished Jan 10 12:26:58 PM PST 24
Peak memory 199600 kb
Host smart-c4188d32-a0a8-49f2-b8ee-134eae65be89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841299696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.3841299696
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.269881214
Short name T222
Test name
Test status
Simulation time 470124069 ps
CPU time 2 seconds
Started Jan 10 12:27:20 PM PST 24
Finished Jan 10 12:27:28 PM PST 24
Peak memory 199560 kb
Host smart-085ff3c4-a369-43bb-a9af-7791ee151b9b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269881214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_err
.269881214
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.2486251162
Short name T168
Test name
Test status
Simulation time 183325743 ps
CPU time 1.13 seconds
Started Jan 10 12:24:32 PM PST 24
Finished Jan 10 12:24:34 PM PST 24
Peak memory 199500 kb
Host smart-0af9a232-1978-4c53-bef4-540c56557e60
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486251162 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.2486251162
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.1056088146
Short name T180
Test name
Test status
Simulation time 64409155 ps
CPU time 0.83 seconds
Started Jan 10 12:30:03 PM PST 24
Finished Jan 10 12:30:45 PM PST 24
Peak memory 197180 kb
Host smart-34bd0c3f-1b1f-44d7-a891-98bbba9638db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056088146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.1056088146
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.1348385568
Short name T231
Test name
Test status
Simulation time 85573770 ps
CPU time 0.95 seconds
Started Jan 10 12:28:59 PM PST 24
Finished Jan 10 12:29:19 PM PST 24
Peak memory 198188 kb
Host smart-a7b45dab-3213-4244-be5f-2c9c4a55b344
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348385568 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.1348385568
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.3799648496
Short name T235
Test name
Test status
Simulation time 386108959 ps
CPU time 2.49 seconds
Started Jan 10 12:30:03 PM PST 24
Finished Jan 10 12:30:47 PM PST 24
Peak memory 198144 kb
Host smart-ab6369e5-49a9-45b1-9d70-da788b02e472
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799648496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.3799648496
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.2730020482
Short name T100
Test name
Test status
Simulation time 452747951 ps
CPU time 1.82 seconds
Started Jan 10 12:26:51 PM PST 24
Finished Jan 10 12:26:57 PM PST 24
Peak memory 199508 kb
Host smart-94bc540a-b7bb-4a0c-8c6c-4202a3b9fbcd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730020482 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.2730020482
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.4006199873
Short name T207
Test name
Test status
Simulation time 149117204 ps
CPU time 1.34 seconds
Started Jan 10 12:30:47 PM PST 24
Finished Jan 10 12:31:33 PM PST 24
Peak memory 199492 kb
Host smart-2fe5fb17-b006-4775-814f-9dd9bc5252a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006199873 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.4006199873
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.1128371701
Short name T114
Test name
Test status
Simulation time 66159461 ps
CPU time 0.77 seconds
Started Jan 10 12:30:44 PM PST 24
Finished Jan 10 12:31:28 PM PST 24
Peak memory 199284 kb
Host smart-2a1d9df7-95ad-42a4-9997-75d00daeb158
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128371701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.1128371701
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.964229807
Short name T175
Test name
Test status
Simulation time 124779162 ps
CPU time 1.17 seconds
Started Jan 10 12:27:46 PM PST 24
Finished Jan 10 12:28:00 PM PST 24
Peak memory 199644 kb
Host smart-234fcc7e-d3e8-49e7-be7a-5d807acabbdb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964229807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_sa
me_csr_outstanding.964229807
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.2294423552
Short name T125
Test name
Test status
Simulation time 271363606 ps
CPU time 2.32 seconds
Started Jan 10 12:26:24 PM PST 24
Finished Jan 10 12:26:27 PM PST 24
Peak memory 198748 kb
Host smart-26453fdd-28b4-452d-b4c6-460351cd1135
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294423552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.2294423552
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.1743335162
Short name T138
Test name
Test status
Simulation time 502614350 ps
CPU time 1.88 seconds
Started Jan 10 12:27:48 PM PST 24
Finished Jan 10 12:28:03 PM PST 24
Peak memory 199616 kb
Host smart-9484ccfb-f28c-4c39-bde0-bdea917b74b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743335162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.1743335162
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.1810809223
Short name T210
Test name
Test status
Simulation time 153450158 ps
CPU time 1.12 seconds
Started Jan 10 12:27:35 PM PST 24
Finished Jan 10 12:27:43 PM PST 24
Peak memory 199816 kb
Host smart-7ebf8297-866d-4bb7-b820-19540c05a80d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810809223 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.1810809223
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3372289426
Short name T184
Test name
Test status
Simulation time 68540955 ps
CPU time 0.73 seconds
Started Jan 10 12:26:51 PM PST 24
Finished Jan 10 12:26:56 PM PST 24
Peak memory 199364 kb
Host smart-d3cf0a67-3b00-42c4-b0ec-1fe10a5aaa9e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372289426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.3372289426
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.3106192273
Short name T225
Test name
Test status
Simulation time 238904047 ps
CPU time 1.5 seconds
Started Jan 10 12:27:17 PM PST 24
Finished Jan 10 12:27:24 PM PST 24
Peak memory 199548 kb
Host smart-f10cb169-10d1-4a6f-b8b5-522d100d6dab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106192273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.3106192273
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.2627407365
Short name T178
Test name
Test status
Simulation time 113281266 ps
CPU time 1.41 seconds
Started Jan 10 12:21:54 PM PST 24
Finished Jan 10 12:21:57 PM PST 24
Peak memory 199852 kb
Host smart-6e2eb9a1-d346-4a66-a105-12af4f460689
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627407365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.2627407365
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.2333752549
Short name T122
Test name
Test status
Simulation time 481452042 ps
CPU time 1.87 seconds
Started Jan 10 12:30:29 PM PST 24
Finished Jan 10 12:31:12 PM PST 24
Peak memory 198304 kb
Host smart-832a99b3-8bfd-4656-aec4-32e1fdd27018
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333752549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.2333752549
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.3074419918
Short name T80
Test name
Test status
Simulation time 96232433 ps
CPU time 0.94 seconds
Started Jan 10 12:27:23 PM PST 24
Finished Jan 10 12:27:30 PM PST 24
Peak memory 199536 kb
Host smart-18dc1415-65ba-4daa-ad59-98ece27f5b15
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074419918 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.3074419918
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.1264122837
Short name T101
Test name
Test status
Simulation time 55574356 ps
CPU time 0.78 seconds
Started Jan 10 12:27:02 PM PST 24
Finished Jan 10 12:27:10 PM PST 24
Peak memory 197572 kb
Host smart-858bcd70-3631-4497-8683-ee26900b4b2d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264122837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.1264122837
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3012394837
Short name T104
Test name
Test status
Simulation time 148665027 ps
CPU time 1.1 seconds
Started Jan 10 12:27:41 PM PST 24
Finished Jan 10 12:27:50 PM PST 24
Peak memory 199436 kb
Host smart-088fba12-f164-490e-a466-9c3da9d76212
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012394837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.3012394837
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3440241988
Short name T118
Test name
Test status
Simulation time 543195049 ps
CPU time 3.83 seconds
Started Jan 10 12:27:12 PM PST 24
Finished Jan 10 12:27:21 PM PST 24
Peak memory 215412 kb
Host smart-9152b55b-06bf-4275-8f1f-7fb8fc589796
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440241988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.3440241988
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.1886931000
Short name T124
Test name
Test status
Simulation time 868250306 ps
CPU time 3.23 seconds
Started Jan 10 12:26:05 PM PST 24
Finished Jan 10 12:26:15 PM PST 24
Peak memory 199528 kb
Host smart-dff3d6fc-c5d4-4ea8-a057-1227cde04814
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886931000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.1886931000
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3976284950
Short name T185
Test name
Test status
Simulation time 126823380 ps
CPU time 1.08 seconds
Started Jan 10 12:23:17 PM PST 24
Finished Jan 10 12:23:27 PM PST 24
Peak memory 199444 kb
Host smart-ad6af928-2110-4468-9732-b74293424421
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976284950 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.3976284950
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.1316096959
Short name T197
Test name
Test status
Simulation time 59369762 ps
CPU time 0.84 seconds
Started Jan 10 12:23:53 PM PST 24
Finished Jan 10 12:23:55 PM PST 24
Peak memory 199460 kb
Host smart-f64a072b-eb7c-451d-85b8-fcdf3eda32c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316096959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.1316096959
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.967983187
Short name T230
Test name
Test status
Simulation time 77493542 ps
CPU time 0.88 seconds
Started Jan 10 12:27:23 PM PST 24
Finished Jan 10 12:27:29 PM PST 24
Peak memory 199456 kb
Host smart-e2290716-5fdc-4f52-970f-6b4fc739c084
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967983187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_sa
me_csr_outstanding.967983187
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2819660122
Short name T199
Test name
Test status
Simulation time 86660106 ps
CPU time 1.19 seconds
Started Jan 10 12:23:51 PM PST 24
Finished Jan 10 12:23:53 PM PST 24
Peak memory 199508 kb
Host smart-1b4b682e-560b-4d92-b3c9-e32da8c09714
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819660122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.2819660122
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.2229503854
Short name T123
Test name
Test status
Simulation time 876403942 ps
CPU time 3.05 seconds
Started Jan 10 12:27:02 PM PST 24
Finished Jan 10 12:27:12 PM PST 24
Peak memory 197752 kb
Host smart-4d6a4ce2-9e2a-4552-b3e5-2dc6d2818d83
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229503854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.2229503854
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.737211792
Short name T227
Test name
Test status
Simulation time 123665845 ps
CPU time 0.95 seconds
Started Jan 10 12:22:06 PM PST 24
Finished Jan 10 12:22:08 PM PST 24
Peak memory 199484 kb
Host smart-2c72d897-56ed-4138-88a7-c9161378f6a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737211792 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.737211792
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.2887233612
Short name T191
Test name
Test status
Simulation time 86440848 ps
CPU time 0.81 seconds
Started Jan 10 12:32:21 PM PST 24
Finished Jan 10 12:33:00 PM PST 24
Peak memory 199176 kb
Host smart-5b91ed66-937b-4fc4-879d-300bd2295090
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887233612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.2887233612
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.2300833526
Short name T113
Test name
Test status
Simulation time 88865230 ps
CPU time 0.94 seconds
Started Jan 10 12:28:23 PM PST 24
Finished Jan 10 12:28:36 PM PST 24
Peak memory 198848 kb
Host smart-4b695953-f48e-4b6d-ab59-90ed8358390e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300833526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.2300833526
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.1553337968
Short name T208
Test name
Test status
Simulation time 228399782 ps
CPU time 1.69 seconds
Started Jan 10 12:28:07 PM PST 24
Finished Jan 10 12:28:25 PM PST 24
Peak memory 199512 kb
Host smart-b2744b45-0567-4aef-950b-74a871e6b364
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553337968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.1553337968
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.4205982126
Short name T96
Test name
Test status
Simulation time 162495632 ps
CPU time 1.55 seconds
Started Jan 10 12:21:57 PM PST 24
Finished Jan 10 12:21:59 PM PST 24
Peak memory 199948 kb
Host smart-364ba116-1c34-471b-ab7f-26efb4a537e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205982126 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.4205982126
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.3006177825
Short name T109
Test name
Test status
Simulation time 75826765 ps
CPU time 0.77 seconds
Started Jan 10 12:23:08 PM PST 24
Finished Jan 10 12:23:17 PM PST 24
Peak memory 199704 kb
Host smart-b9be98b6-3a8c-4e62-94cd-7516d52d4578
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006177825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.3006177825
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.3976836073
Short name T115
Test name
Test status
Simulation time 132649049 ps
CPU time 1.09 seconds
Started Jan 10 12:25:29 PM PST 24
Finished Jan 10 12:25:31 PM PST 24
Peak memory 199456 kb
Host smart-976c88f2-05ec-4010-b722-20366a56b6cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976836073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.3976836073
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.578414915
Short name T169
Test name
Test status
Simulation time 245743661 ps
CPU time 1.85 seconds
Started Jan 10 12:27:12 PM PST 24
Finished Jan 10 12:27:19 PM PST 24
Peak memory 199524 kb
Host smart-c5040fd8-c19e-41e1-9edd-ea6f3287fbef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578414915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.578414915
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.3015151708
Short name T74
Test name
Test status
Simulation time 788327913 ps
CPU time 2.74 seconds
Started Jan 10 12:22:28 PM PST 24
Finished Jan 10 12:22:32 PM PST 24
Peak memory 199504 kb
Host smart-c941c231-01ad-4f9e-a789-3f8c2c9f3e6b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015151708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.3015151708
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.2272246567
Short name T166
Test name
Test status
Simulation time 162203089 ps
CPU time 1.99 seconds
Started Jan 10 12:22:46 PM PST 24
Finished Jan 10 12:22:49 PM PST 24
Peak memory 199492 kb
Host smart-9bad67bc-711b-4bb7-a46e-358b7ff9c3ab
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272246567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.2
272246567
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.1889422298
Short name T68
Test name
Test status
Simulation time 1562840949 ps
CPU time 8.37 seconds
Started Jan 10 12:22:08 PM PST 24
Finished Jan 10 12:22:17 PM PST 24
Peak memory 199472 kb
Host smart-51a82721-4756-42e7-b8d5-dc8b38743451
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889422298 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.1
889422298
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1445968553
Short name T205
Test name
Test status
Simulation time 117859197 ps
CPU time 0.84 seconds
Started Jan 10 12:28:54 PM PST 24
Finished Jan 10 12:29:13 PM PST 24
Peak memory 199380 kb
Host smart-a7a2e263-3d77-4db1-b4cd-fe7000ab4ffe
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445968553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.1
445968553
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.525360105
Short name T213
Test name
Test status
Simulation time 186829290 ps
CPU time 1.43 seconds
Started Jan 10 12:28:07 PM PST 24
Finished Jan 10 12:28:25 PM PST 24
Peak memory 199248 kb
Host smart-73ece511-4be4-4e5f-91d1-5ca2f068a8d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525360105 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.525360105
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.1771553247
Short name T217
Test name
Test status
Simulation time 71289333 ps
CPU time 0.82 seconds
Started Jan 10 12:26:06 PM PST 24
Finished Jan 10 12:26:13 PM PST 24
Peak memory 199192 kb
Host smart-19e9ec5d-9e7a-4798-8824-a6fdc2e3a9c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771553247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.1771553247
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.1091160660
Short name T228
Test name
Test status
Simulation time 249620159 ps
CPU time 1.59 seconds
Started Jan 10 12:22:34 PM PST 24
Finished Jan 10 12:22:36 PM PST 24
Peak memory 199580 kb
Host smart-647ba5a4-30ad-41ed-a5b7-4cd5bc16efbe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091160660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.1091160660
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3512464515
Short name T92
Test name
Test status
Simulation time 493083237 ps
CPU time 2.02 seconds
Started Jan 10 12:28:05 PM PST 24
Finished Jan 10 12:28:23 PM PST 24
Peak memory 199212 kb
Host smart-1b079adf-e927-483f-88dd-7b98f062339e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512464515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.3512464515
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.1101632271
Short name T187
Test name
Test status
Simulation time 163241096 ps
CPU time 2 seconds
Started Jan 10 12:28:52 PM PST 24
Finished Jan 10 12:29:11 PM PST 24
Peak memory 197904 kb
Host smart-8bd8bd2b-204f-41ea-8b65-e6190cfb4bb4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101632271 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.1
101632271
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.1379169374
Short name T186
Test name
Test status
Simulation time 483323031 ps
CPU time 5.62 seconds
Started Jan 10 12:27:43 PM PST 24
Finished Jan 10 12:28:01 PM PST 24
Peak memory 199536 kb
Host smart-b67dc18b-11d7-44aa-8a0e-c5856baff617
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379169374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.1
379169374
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1963173916
Short name T236
Test name
Test status
Simulation time 147039885 ps
CPU time 1.13 seconds
Started Jan 10 12:28:52 PM PST 24
Finished Jan 10 12:29:11 PM PST 24
Peak memory 197740 kb
Host smart-d13fbe89-e51d-4357-a1de-479f9c1a740d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963173916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.1
963173916
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.3783935670
Short name T229
Test name
Test status
Simulation time 112233208 ps
CPU time 0.89 seconds
Started Jan 10 12:27:40 PM PST 24
Finished Jan 10 12:27:50 PM PST 24
Peak memory 199496 kb
Host smart-a077f5f9-18c6-4fd6-a190-323cac36ec57
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783935670 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.3783935670
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.252072767
Short name T193
Test name
Test status
Simulation time 70902139 ps
CPU time 0.81 seconds
Started Jan 10 12:23:29 PM PST 24
Finished Jan 10 12:23:31 PM PST 24
Peak memory 199244 kb
Host smart-43c68868-4a59-4fe1-81b6-836cedb333ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252072767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.252072767
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.3454474483
Short name T201
Test name
Test status
Simulation time 212490740 ps
CPU time 1.62 seconds
Started Jan 10 12:26:56 PM PST 24
Finished Jan 10 12:27:04 PM PST 24
Peak memory 197636 kb
Host smart-7f4f67a2-718e-4738-aa06-86333f155009
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454474483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.3454474483
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.285695982
Short name T196
Test name
Test status
Simulation time 339406483 ps
CPU time 2.53 seconds
Started Jan 10 12:26:56 PM PST 24
Finished Jan 10 12:27:05 PM PST 24
Peak memory 197708 kb
Host smart-0ee87d12-0a6f-495b-8012-8fb54a4151a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285695982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.285695982
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.1103735455
Short name T119
Test name
Test status
Simulation time 474076574 ps
CPU time 2 seconds
Started Jan 10 12:27:46 PM PST 24
Finished Jan 10 12:28:02 PM PST 24
Peak memory 198840 kb
Host smart-fd4af772-734b-4407-827a-e8ce155d7668
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103735455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.1103735455
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.1581129970
Short name T182
Test name
Test status
Simulation time 264028548 ps
CPU time 1.65 seconds
Started Jan 10 12:27:41 PM PST 24
Finished Jan 10 12:27:51 PM PST 24
Peak memory 199416 kb
Host smart-3b650c88-62e1-48a1-ab0f-da9a91a00e80
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581129970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.1
581129970
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.907400371
Short name T69
Test name
Test status
Simulation time 1180205554 ps
CPU time 5.13 seconds
Started Jan 10 12:27:40 PM PST 24
Finished Jan 10 12:27:54 PM PST 24
Peak memory 199444 kb
Host smart-cdd9811e-56fa-4d88-a547-37d7a2796088
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907400371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.907400371
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1412284196
Short name T194
Test name
Test status
Simulation time 89790933 ps
CPU time 0.88 seconds
Started Jan 10 12:22:06 PM PST 24
Finished Jan 10 12:22:08 PM PST 24
Peak memory 198248 kb
Host smart-8994cec1-fc73-41c6-a7d0-257eba10d6ab
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412284196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.1
412284196
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.2808480404
Short name T192
Test name
Test status
Simulation time 139774472 ps
CPU time 1.22 seconds
Started Jan 10 12:23:50 PM PST 24
Finished Jan 10 12:23:52 PM PST 24
Peak memory 199564 kb
Host smart-3d80d4ee-4ad1-4d93-94db-705dad01fd29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808480404 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.2808480404
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1695511751
Short name T65
Test name
Test status
Simulation time 68707593 ps
CPU time 0.76 seconds
Started Jan 10 12:28:28 PM PST 24
Finished Jan 10 12:28:40 PM PST 24
Peak memory 198320 kb
Host smart-921adab6-5ef7-499f-a358-a0c4033fd50d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695511751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.1695511751
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.3955079586
Short name T176
Test name
Test status
Simulation time 100274416 ps
CPU time 1.18 seconds
Started Jan 10 12:27:40 PM PST 24
Finished Jan 10 12:27:50 PM PST 24
Peak memory 199484 kb
Host smart-f47b39e9-6558-453e-b1f0-a3a5113879a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955079586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.3955079586
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.2603253548
Short name T198
Test name
Test status
Simulation time 320109164 ps
CPU time 2.42 seconds
Started Jan 10 12:26:56 PM PST 24
Finished Jan 10 12:27:05 PM PST 24
Peak memory 206020 kb
Host smart-c3c98cb1-8dc2-4b27-9c4d-88b741ebb7af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603253548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.2603253548
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.531119089
Short name T121
Test name
Test status
Simulation time 475237202 ps
CPU time 1.87 seconds
Started Jan 10 12:27:40 PM PST 24
Finished Jan 10 12:27:56 PM PST 24
Peak memory 199488 kb
Host smart-5ac54e13-530b-46b4-b8ae-62dba1e270d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531119089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err.
531119089
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.4279729572
Short name T237
Test name
Test status
Simulation time 149814275 ps
CPU time 0.98 seconds
Started Jan 10 12:28:42 PM PST 24
Finished Jan 10 12:28:57 PM PST 24
Peak memory 199496 kb
Host smart-7094543f-1dcc-4816-9f29-00daf20662da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279729572 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.4279729572
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.719971027
Short name T212
Test name
Test status
Simulation time 58026037 ps
CPU time 0.78 seconds
Started Jan 10 12:22:40 PM PST 24
Finished Jan 10 12:22:41 PM PST 24
Peak memory 199416 kb
Host smart-501f7746-0a8e-4267-9fef-b3a939c1d21f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719971027 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.719971027
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.1142202292
Short name T172
Test name
Test status
Simulation time 148980646 ps
CPU time 1.19 seconds
Started Jan 10 12:28:28 PM PST 24
Finished Jan 10 12:28:40 PM PST 24
Peak memory 198544 kb
Host smart-1b188c8c-a689-4b82-8bfb-e5c7a0ddb790
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142202292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.1142202292
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.1757570906
Short name T98
Test name
Test status
Simulation time 106539676 ps
CPU time 1.52 seconds
Started Jan 10 12:27:44 PM PST 24
Finished Jan 10 12:28:00 PM PST 24
Peak memory 199472 kb
Host smart-f7c5ae0b-a22e-4694-844d-e03297fbf16f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757570906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.1757570906
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.1604724296
Short name T232
Test name
Test status
Simulation time 468651445 ps
CPU time 1.87 seconds
Started Jan 10 12:27:49 PM PST 24
Finished Jan 10 12:28:06 PM PST 24
Peak memory 199564 kb
Host smart-e640d74b-0459-4630-95c3-199f0c385197
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604724296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.1604724296
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.859768663
Short name T112
Test name
Test status
Simulation time 73705178 ps
CPU time 0.87 seconds
Started Jan 10 12:28:30 PM PST 24
Finished Jan 10 12:28:42 PM PST 24
Peak memory 197880 kb
Host smart-35ba1710-6175-4495-afba-3260e3db5800
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859768663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.859768663
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.50629930
Short name T221
Test name
Test status
Simulation time 89488372 ps
CPU time 0.91 seconds
Started Jan 10 12:28:27 PM PST 24
Finished Jan 10 12:28:39 PM PST 24
Peak memory 199284 kb
Host smart-f5018b74-e580-41de-8738-46a93c71d385
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50629930 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_same
_csr_outstanding.50629930
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.3160516381
Short name T219
Test name
Test status
Simulation time 201481957 ps
CPU time 1.84 seconds
Started Jan 10 12:26:48 PM PST 24
Finished Jan 10 12:26:55 PM PST 24
Peak memory 198124 kb
Host smart-6d88ebba-8cef-45c7-afa9-5c237ee59232
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160516381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.3160516381
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.3258413519
Short name T220
Test name
Test status
Simulation time 440918446 ps
CPU time 1.66 seconds
Started Jan 10 12:26:29 PM PST 24
Finished Jan 10 12:26:33 PM PST 24
Peak memory 199216 kb
Host smart-907c11be-55ca-4064-bee2-9640716bbe83
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258413519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.3258413519
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.2634009784
Short name T223
Test name
Test status
Simulation time 128487971 ps
CPU time 1.06 seconds
Started Jan 10 12:22:02 PM PST 24
Finished Jan 10 12:22:04 PM PST 24
Peak memory 199868 kb
Host smart-8b876634-4840-4726-9e5c-eba2af69ead5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634009784 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.2634009784
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.744102159
Short name T170
Test name
Test status
Simulation time 64944547 ps
CPU time 0.73 seconds
Started Jan 10 12:29:33 PM PST 24
Finished Jan 10 12:30:00 PM PST 24
Peak memory 199100 kb
Host smart-963e7b62-4562-4f9c-86e1-f8065225e6af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744102159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.744102159
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.6766039
Short name T116
Test name
Test status
Simulation time 71814772 ps
CPU time 0.89 seconds
Started Jan 10 12:29:35 PM PST 24
Finished Jan 10 12:30:03 PM PST 24
Peak memory 198932 kb
Host smart-6b20de23-503d-4aa6-af72-b71e755416fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6766039 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_same_
csr_outstanding.6766039
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.3606785884
Short name T73
Test name
Test status
Simulation time 203744759 ps
CPU time 1.56 seconds
Started Jan 10 12:26:58 PM PST 24
Finished Jan 10 12:27:07 PM PST 24
Peak memory 198740 kb
Host smart-95172e34-1260-4bb0-a0ad-3869f37799e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606785884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.3606785884
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.1755087664
Short name T136
Test name
Test status
Simulation time 477792043 ps
CPU time 2.13 seconds
Started Jan 10 12:26:36 PM PST 24
Finished Jan 10 12:26:43 PM PST 24
Peak memory 199568 kb
Host smart-f1555671-705f-447e-929a-463e12a2815e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755087664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.1755087664
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1175361308
Short name T177
Test name
Test status
Simulation time 106238348 ps
CPU time 0.87 seconds
Started Jan 10 12:27:00 PM PST 24
Finished Jan 10 12:27:08 PM PST 24
Peak memory 199492 kb
Host smart-47aaa224-fc9e-4bf8-af5a-239fbaa45e94
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175361308 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.1175361308
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.3564212634
Short name T183
Test name
Test status
Simulation time 68991219 ps
CPU time 0.72 seconds
Started Jan 10 12:27:00 PM PST 24
Finished Jan 10 12:27:07 PM PST 24
Peak memory 199364 kb
Host smart-99b09e8f-f2bf-4482-ae46-13b4d2067edf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564212634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.3564212634
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.1583000978
Short name T234
Test name
Test status
Simulation time 236038885 ps
CPU time 1.48 seconds
Started Jan 10 12:29:03 PM PST 24
Finished Jan 10 12:29:24 PM PST 24
Peak memory 199436 kb
Host smart-a77ba9d4-5f38-4517-9c6a-9c182237b292
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583000978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.1583000978
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3755734225
Short name T233
Test name
Test status
Simulation time 424234926 ps
CPU time 1.83 seconds
Started Jan 10 12:26:51 PM PST 24
Finished Jan 10 12:26:57 PM PST 24
Peak memory 199504 kb
Host smart-737f7164-1add-4693-b9d9-a2931bd46f29
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755734225 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.3755734225
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.1920753012
Short name T216
Test name
Test status
Simulation time 166699553 ps
CPU time 1.7 seconds
Started Jan 10 12:30:03 PM PST 24
Finished Jan 10 12:30:46 PM PST 24
Peak memory 213756 kb
Host smart-622fa197-14cd-45e0-96e1-dbb3f2c4913a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920753012 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.1920753012
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.870201618
Short name T174
Test name
Test status
Simulation time 77361435 ps
CPU time 0.85 seconds
Started Jan 10 12:25:59 PM PST 24
Finished Jan 10 12:26:11 PM PST 24
Peak memory 199428 kb
Host smart-676e5b85-0aab-40bd-8a6d-fa657b242cf9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870201618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.870201618
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.1065001540
Short name T203
Test name
Test status
Simulation time 125532888 ps
CPU time 1 seconds
Started Jan 10 12:29:35 PM PST 24
Finished Jan 10 12:30:03 PM PST 24
Peak memory 199168 kb
Host smart-91f7b940-f3bd-4079-bc38-729cf4f23831
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065001540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.1065001540
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.3869569993
Short name T128
Test name
Test status
Simulation time 93027377 ps
CPU time 1.25 seconds
Started Jan 10 12:29:01 PM PST 24
Finished Jan 10 12:29:22 PM PST 24
Peak memory 199264 kb
Host smart-1b4fcf7e-71aa-4e25-a4d5-39ed68995ee5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869569993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.3869569993
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.2428826929
Short name T218
Test name
Test status
Simulation time 425785018 ps
CPU time 1.94 seconds
Started Jan 10 12:26:26 PM PST 24
Finished Jan 10 12:26:30 PM PST 24
Peak memory 198188 kb
Host smart-92f0b3a3-2d44-4f1c-9bce-112a4d748218
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428826929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.2428826929
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.1349069542
Short name T259
Test name
Test status
Simulation time 95735050 ps
CPU time 0.81 seconds
Started Jan 10 12:25:20 PM PST 24
Finished Jan 10 12:25:21 PM PST 24
Peak memory 199100 kb
Host smart-47cbf695-003f-4e3e-b95d-125cf98c04c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349069542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.1349069542
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.2477112756
Short name T34
Test name
Test status
Simulation time 1220407592 ps
CPU time 5.18 seconds
Started Jan 10 12:29:39 PM PST 24
Finished Jan 10 12:30:15 PM PST 24
Peak memory 215660 kb
Host smart-576dedac-5ab5-458b-b0ee-414350772e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477112756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.2477112756
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.2620122934
Short name T424
Test name
Test status
Simulation time 244206053 ps
CPU time 1.04 seconds
Started Jan 10 12:31:41 PM PST 24
Finished Jan 10 12:32:32 PM PST 24
Peak memory 214912 kb
Host smart-02daf457-fd26-4d85-82df-a7897f624c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620122934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.2620122934
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.4287025822
Short name T461
Test name
Test status
Simulation time 144533014 ps
CPU time 0.81 seconds
Started Jan 10 12:28:04 PM PST 24
Finished Jan 10 12:28:20 PM PST 24
Peak memory 198992 kb
Host smart-239fd9df-07a6-4b26-9ea7-233f2092b516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287025822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.4287025822
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.560873946
Short name T289
Test name
Test status
Simulation time 1615460104 ps
CPU time 5.96 seconds
Started Jan 10 12:38:49 PM PST 24
Finished Jan 10 12:39:28 PM PST 24
Peak memory 199452 kb
Host smart-1a2ac824-0bfb-4a12-b8d5-3eaa5b2888f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560873946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.560873946
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.2017636882
Short name T77
Test name
Test status
Simulation time 16607536616 ps
CPU time 25.89 seconds
Started Jan 10 12:49:37 PM PST 24
Finished Jan 10 12:51:31 PM PST 24
Peak memory 217460 kb
Host smart-66b30cbb-4490-47fd-8e02-ee6fb2a0d581
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017636882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.2017636882
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.1828532334
Short name T141
Test name
Test status
Simulation time 108980169 ps
CPU time 1.05 seconds
Started Jan 10 01:14:30 PM PST 24
Finished Jan 10 01:15:10 PM PST 24
Peak memory 199344 kb
Host smart-f6205af1-da9b-4226-8168-73e61ffb1fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828532334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.1828532334
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.1827314638
Short name T579
Test name
Test status
Simulation time 262280323 ps
CPU time 1.45 seconds
Started Jan 10 12:48:26 PM PST 24
Finished Jan 10 12:49:51 PM PST 24
Peak memory 199500 kb
Host smart-7b9d5792-9327-42ed-8db3-995fafc341f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827314638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.1827314638
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.4213115508
Short name T438
Test name
Test status
Simulation time 262815219 ps
CPU time 1.81 seconds
Started Jan 10 12:40:32 PM PST 24
Finished Jan 10 12:41:18 PM PST 24
Peak memory 199292 kb
Host smart-0fac883a-bf11-4ea1-8b8d-b721529f82a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213115508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.4213115508
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.3106136431
Short name T285
Test name
Test status
Simulation time 66076589 ps
CPU time 0.72 seconds
Started Jan 10 12:35:16 PM PST 24
Finished Jan 10 12:35:49 PM PST 24
Peak memory 199320 kb
Host smart-3699bc15-a5da-43ed-a88b-0d16cf1a2712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106136431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.3106136431
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.2426792775
Short name T611
Test name
Test status
Simulation time 70355220 ps
CPU time 0.72 seconds
Started Jan 10 12:45:58 PM PST 24
Finished Jan 10 12:47:20 PM PST 24
Peak memory 199184 kb
Host smart-bfbeb997-13b7-4238-b8a3-2549351fe275
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426792775 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.2426792775
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.2321393383
Short name T57
Test name
Test status
Simulation time 1229911762 ps
CPU time 5.38 seconds
Started Jan 10 12:50:39 PM PST 24
Finished Jan 10 12:52:01 PM PST 24
Peak memory 220628 kb
Host smart-71a79b58-20ae-4d11-8107-9297d5af463d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321393383 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.2321393383
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.912585292
Short name T429
Test name
Test status
Simulation time 254319824 ps
CPU time 1.02 seconds
Started Jan 10 12:39:31 PM PST 24
Finished Jan 10 12:40:01 PM PST 24
Peak memory 215608 kb
Host smart-90048f91-6dbc-4dc2-a686-d9c6a9d76843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912585292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.912585292
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_reset.4248849988
Short name T344
Test name
Test status
Simulation time 774289933 ps
CPU time 3.84 seconds
Started Jan 10 12:41:24 PM PST 24
Finished Jan 10 12:42:34 PM PST 24
Peak memory 199484 kb
Host smart-784d1ef9-a482-46c0-8617-a963eff3f57d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248849988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.4248849988
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.3778014349
Short name T81
Test name
Test status
Simulation time 16523863052 ps
CPU time 31.56 seconds
Started Jan 10 12:25:18 PM PST 24
Finished Jan 10 12:25:50 PM PST 24
Peak memory 217256 kb
Host smart-066528c0-c86d-49e4-8627-9a570dda1ebc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778014349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.3778014349
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.1203109929
Short name T132
Test name
Test status
Simulation time 186196658 ps
CPU time 1.17 seconds
Started Jan 10 12:37:30 PM PST 24
Finished Jan 10 12:38:07 PM PST 24
Peak memory 199272 kb
Host smart-dedcfd29-6712-4694-beb6-665b37c9fdc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203109929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.1203109929
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.3496133669
Short name T375
Test name
Test status
Simulation time 252367107 ps
CPU time 1.61 seconds
Started Jan 10 12:50:58 PM PST 24
Finished Jan 10 12:52:24 PM PST 24
Peak memory 199444 kb
Host smart-1ddc58ce-33ee-474f-8fd5-8b025e7624f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496133669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.3496133669
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.1850767638
Short name T426
Test name
Test status
Simulation time 15856907329 ps
CPU time 51.6 seconds
Started Jan 10 12:31:51 PM PST 24
Finished Jan 10 12:33:29 PM PST 24
Peak memory 199196 kb
Host smart-eb883797-d614-4216-9d54-17ca11f01de5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850767638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.1850767638
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.3429411694
Short name T249
Test name
Test status
Simulation time 368245075 ps
CPU time 2.23 seconds
Started Jan 10 12:45:20 PM PST 24
Finished Jan 10 12:46:44 PM PST 24
Peak memory 199252 kb
Host smart-f88e3844-99d9-4293-88eb-9ea1cf54ffbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429411694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.3429411694
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.1502371584
Short name T45
Test name
Test status
Simulation time 110821169 ps
CPU time 0.92 seconds
Started Jan 10 12:34:42 PM PST 24
Finished Jan 10 12:35:24 PM PST 24
Peak memory 199256 kb
Host smart-15f0f304-4cc2-4718-b97f-045405fce5e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502371584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.1502371584
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.3934887609
Short name T616
Test name
Test status
Simulation time 77205760 ps
CPU time 0.76 seconds
Started Jan 10 12:29:04 PM PST 24
Finished Jan 10 12:29:25 PM PST 24
Peak memory 199096 kb
Host smart-17ad1b52-777d-4462-bd20-dea97799a989
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934887609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.3934887609
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.4226301867
Short name T264
Test name
Test status
Simulation time 1223417673 ps
CPU time 5.19 seconds
Started Jan 10 12:31:19 PM PST 24
Finished Jan 10 12:32:09 PM PST 24
Peak memory 216308 kb
Host smart-3b6e45d4-72a3-427e-af2e-0bac4a1ac947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226301867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.4226301867
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.1039980500
Short name T362
Test name
Test status
Simulation time 248445501 ps
CPU time 1.02 seconds
Started Jan 10 12:40:11 PM PST 24
Finished Jan 10 12:40:59 PM PST 24
Peak memory 216496 kb
Host smart-1dfa7378-b358-464a-83a2-34af2010c18a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039980500 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.1039980500
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.1292353270
Short name T273
Test name
Test status
Simulation time 210075443 ps
CPU time 0.95 seconds
Started Jan 10 12:40:10 PM PST 24
Finished Jan 10 12:40:57 PM PST 24
Peak memory 199120 kb
Host smart-0a7081d8-0ee1-4569-84f7-200ac3eec45a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292353270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.1292353270
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.2925495232
Short name T316
Test name
Test status
Simulation time 619123148 ps
CPU time 3.3 seconds
Started Jan 10 12:50:10 PM PST 24
Finished Jan 10 12:51:36 PM PST 24
Peak memory 199436 kb
Host smart-7e801ca0-86a3-40ac-9539-3734dd90ad4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925495232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.2925495232
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.4176295878
Short name T110
Test name
Test status
Simulation time 181705041 ps
CPU time 1.15 seconds
Started Jan 10 12:37:19 PM PST 24
Finished Jan 10 12:37:51 PM PST 24
Peak memory 199232 kb
Host smart-80e02b6b-a5fd-4665-9076-947894db3a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176295878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.4176295878
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.1929222248
Short name T558
Test name
Test status
Simulation time 255533605 ps
CPU time 1.51 seconds
Started Jan 10 12:28:43 PM PST 24
Finished Jan 10 12:28:59 PM PST 24
Peak memory 199356 kb
Host smart-ae9a2a74-6c2b-424e-9252-0b3c55e642ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929222248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.1929222248
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.2206315531
Short name T255
Test name
Test status
Simulation time 2002000780 ps
CPU time 10.06 seconds
Started Jan 10 12:45:45 PM PST 24
Finished Jan 10 12:47:15 PM PST 24
Peak memory 199488 kb
Host smart-128757e2-b403-4ebf-88e1-9966d3f89676
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206315531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.2206315531
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.58252398
Short name T315
Test name
Test status
Simulation time 457246843 ps
CPU time 2.39 seconds
Started Jan 10 12:37:57 PM PST 24
Finished Jan 10 12:38:31 PM PST 24
Peak memory 199276 kb
Host smart-2061851d-727a-4452-a39e-13405dd9bb4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58252398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.58252398
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.3160363193
Short name T567
Test name
Test status
Simulation time 76775365 ps
CPU time 0.83 seconds
Started Jan 10 12:29:13 PM PST 24
Finished Jan 10 12:29:36 PM PST 24
Peak memory 199572 kb
Host smart-b9a7a349-8237-4460-8492-ed1cb440f75f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160363193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.3160363193
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.2257214460
Short name T28
Test name
Test status
Simulation time 1225198892 ps
CPU time 5.47 seconds
Started Jan 10 01:11:34 PM PST 24
Finished Jan 10 01:12:59 PM PST 24
Peak memory 221400 kb
Host smart-94584fbf-57ab-4184-baea-bfa808cb0516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257214460 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.2257214460
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.3941967857
Short name T559
Test name
Test status
Simulation time 244081966 ps
CPU time 1.05 seconds
Started Jan 10 12:29:04 PM PST 24
Finished Jan 10 12:29:25 PM PST 24
Peak memory 216504 kb
Host smart-925bc254-32ef-4954-b44a-d9d66e052588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941967857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.3941967857
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.25800918
Short name T553
Test name
Test status
Simulation time 143857530 ps
CPU time 0.82 seconds
Started Jan 10 12:28:39 PM PST 24
Finished Jan 10 12:28:52 PM PST 24
Peak memory 198912 kb
Host smart-10851c3a-dfbb-4d96-93c9-eb240f30b15f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25800918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.25800918
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.3126206464
Short name T418
Test name
Test status
Simulation time 1674968457 ps
CPU time 6.03 seconds
Started Jan 10 12:51:34 PM PST 24
Finished Jan 10 12:52:55 PM PST 24
Peak memory 199448 kb
Host smart-71859e5a-a63b-4538-8df3-45955f0343df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126206464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.3126206464
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.2463518242
Short name T325
Test name
Test status
Simulation time 141370004 ps
CPU time 1.09 seconds
Started Jan 10 12:26:13 PM PST 24
Finished Jan 10 12:26:19 PM PST 24
Peak memory 199196 kb
Host smart-4c1065ba-3d4b-4b8d-b86e-2e4c850b7a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463518242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.2463518242
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.1962368461
Short name T323
Test name
Test status
Simulation time 191822049 ps
CPU time 1.33 seconds
Started Jan 10 12:49:48 PM PST 24
Finished Jan 10 12:51:54 PM PST 24
Peak memory 199384 kb
Host smart-00f07669-f8f0-4879-a8ca-16d48334d968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962368461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.1962368461
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.3488832094
Short name T391
Test name
Test status
Simulation time 11904786674 ps
CPU time 42.04 seconds
Started Jan 10 12:28:59 PM PST 24
Finished Jan 10 12:30:00 PM PST 24
Peak memory 199504 kb
Host smart-400db348-79c5-480e-a9cd-ec252108c372
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488832094 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.3488832094
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.3881454975
Short name T286
Test name
Test status
Simulation time 404614226 ps
CPU time 2.03 seconds
Started Jan 10 01:02:16 PM PST 24
Finished Jan 10 01:03:56 PM PST 24
Peak memory 199212 kb
Host smart-cfdfe259-9ff7-4210-994e-51107eec498d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881454975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.3881454975
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.3044287075
Short name T406
Test name
Test status
Simulation time 200525023 ps
CPU time 1.17 seconds
Started Jan 10 12:36:23 PM PST 24
Finished Jan 10 12:36:58 PM PST 24
Peak memory 199304 kb
Host smart-ae19db09-ecb9-43ad-b966-108f3fd4653f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044287075 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.3044287075
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.1388930072
Short name T158
Test name
Test status
Simulation time 73486695 ps
CPU time 0.72 seconds
Started Jan 10 12:31:20 PM PST 24
Finished Jan 10 12:32:07 PM PST 24
Peak memory 198916 kb
Host smart-7471e0ca-1151-45ca-a93f-22530e1241b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388930072 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.1388930072
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.332517301
Short name T54
Test name
Test status
Simulation time 1211781870 ps
CPU time 5.81 seconds
Started Jan 10 12:45:06 PM PST 24
Finished Jan 10 12:46:35 PM PST 24
Peak memory 216684 kb
Host smart-9287b269-f9f1-4128-82e6-94bb33a0c216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332517301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.332517301
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.2710688466
Short name T314
Test name
Test status
Simulation time 244956262 ps
CPU time 1.09 seconds
Started Jan 10 12:28:53 PM PST 24
Finished Jan 10 12:29:12 PM PST 24
Peak memory 216288 kb
Host smart-15e22d2f-70b5-4755-aab8-56ce515b41fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710688466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.2710688466
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.1784169980
Short name T501
Test name
Test status
Simulation time 167080828 ps
CPU time 0.79 seconds
Started Jan 10 12:46:20 PM PST 24
Finished Jan 10 12:47:40 PM PST 24
Peak memory 199076 kb
Host smart-2ae5345d-31ba-49c7-8d74-8e2517eafcf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784169980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.1784169980
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.2983236648
Short name T490
Test name
Test status
Simulation time 1346251608 ps
CPU time 5.07 seconds
Started Jan 10 12:36:08 PM PST 24
Finished Jan 10 12:36:43 PM PST 24
Peak memory 199552 kb
Host smart-71292ef1-d774-495c-9b25-997f6d42a25d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983236648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.2983236648
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.2818326485
Short name T552
Test name
Test status
Simulation time 144205413 ps
CPU time 1.15 seconds
Started Jan 10 12:38:42 PM PST 24
Finished Jan 10 12:39:16 PM PST 24
Peak memory 199304 kb
Host smart-b6322f08-ac66-41bf-988e-25c99f459d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818326485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.2818326485
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.2484243005
Short name T492
Test name
Test status
Simulation time 240321520 ps
CPU time 1.52 seconds
Started Jan 10 12:54:37 PM PST 24
Finished Jan 10 12:55:44 PM PST 24
Peak memory 199420 kb
Host smart-fd0dcf24-5597-42f9-854a-af2714dc3981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484243005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.2484243005
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.1724325194
Short name T298
Test name
Test status
Simulation time 1982122846 ps
CPU time 7.43 seconds
Started Jan 10 12:28:38 PM PST 24
Finished Jan 10 12:28:58 PM PST 24
Peak memory 199224 kb
Host smart-6dfba169-dcef-40ba-9dba-97270929ebe5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724325194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.1724325194
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.1921308787
Short name T440
Test name
Test status
Simulation time 385152923 ps
CPU time 2.18 seconds
Started Jan 10 12:54:51 PM PST 24
Finished Jan 10 12:55:59 PM PST 24
Peak memory 199220 kb
Host smart-a6dc275c-7272-4dbb-a788-fc07e144f73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921308787 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.1921308787
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.3643183018
Short name T352
Test name
Test status
Simulation time 130492709 ps
CPU time 0.92 seconds
Started Jan 10 12:31:14 PM PST 24
Finished Jan 10 12:32:00 PM PST 24
Peak memory 198972 kb
Host smart-8fce5716-a707-4a9c-bc90-e05e15568487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643183018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.3643183018
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.1780518253
Short name T454
Test name
Test status
Simulation time 73492521 ps
CPU time 0.73 seconds
Started Jan 10 12:28:21 PM PST 24
Finished Jan 10 12:28:34 PM PST 24
Peak memory 198120 kb
Host smart-39fc140b-28a7-48df-8880-6d819e99770d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780518253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.1780518253
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.3490605733
Short name T38
Test name
Test status
Simulation time 1230199797 ps
CPU time 5.51 seconds
Started Jan 10 12:28:38 PM PST 24
Finished Jan 10 12:28:56 PM PST 24
Peak memory 220964 kb
Host smart-2ba00b5e-97fd-449d-a221-1965fcced1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490605733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.3490605733
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.1018735828
Short name T75
Test name
Test status
Simulation time 243900047 ps
CPU time 1.19 seconds
Started Jan 10 12:29:00 PM PST 24
Finished Jan 10 12:29:20 PM PST 24
Peak memory 216448 kb
Host smart-a5b1511e-7125-4bac-9011-81923a390bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018735828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.1018735828
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.2006899293
Short name T581
Test name
Test status
Simulation time 155780117 ps
CPU time 0.81 seconds
Started Jan 10 12:28:38 PM PST 24
Finished Jan 10 12:28:51 PM PST 24
Peak memory 198844 kb
Host smart-25001921-de17-4cf0-a770-ddc5ceab41e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006899293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.2006899293
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.716419918
Short name T393
Test name
Test status
Simulation time 1850753974 ps
CPU time 6.49 seconds
Started Jan 10 12:55:02 PM PST 24
Finished Jan 10 12:56:13 PM PST 24
Peak memory 199376 kb
Host smart-f28c90f6-aeef-4c70-ade3-68a1a53ab66d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716419918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.716419918
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.1102454746
Short name T538
Test name
Test status
Simulation time 139494939 ps
CPU time 1.04 seconds
Started Jan 10 12:44:59 PM PST 24
Finished Jan 10 12:46:22 PM PST 24
Peak memory 199308 kb
Host smart-1e4d96d1-e7ad-4b05-babc-3c748a13b1ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102454746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.1102454746
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.630510461
Short name T427
Test name
Test status
Simulation time 117997686 ps
CPU time 1.07 seconds
Started Jan 10 12:28:36 PM PST 24
Finished Jan 10 12:28:48 PM PST 24
Peak memory 199212 kb
Host smart-2b7bbed2-0c9b-4567-acdd-62593d7fed85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630510461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.630510461
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.231574070
Short name T133
Test name
Test status
Simulation time 175568979 ps
CPU time 1.09 seconds
Started Jan 10 12:35:11 PM PST 24
Finished Jan 10 12:35:46 PM PST 24
Peak memory 199344 kb
Host smart-1a9218fd-e809-420f-8dd9-fab8e90074b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231574070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.231574070
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.2081746789
Short name T51
Test name
Test status
Simulation time 147622952 ps
CPU time 1.73 seconds
Started Jan 10 12:43:50 PM PST 24
Finished Jan 10 12:45:05 PM PST 24
Peak memory 199184 kb
Host smart-c0fdf941-f01f-4d67-97fc-1234ed13ea1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081746789 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.2081746789
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.1189993844
Short name T156
Test name
Test status
Simulation time 82240483 ps
CPU time 0.77 seconds
Started Jan 10 12:31:15 PM PST 24
Finished Jan 10 12:32:00 PM PST 24
Peak memory 198976 kb
Host smart-7fc59574-ddbe-4431-9a2c-bbafc2f91b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189993844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.1189993844
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.1058738749
Short name T263
Test name
Test status
Simulation time 57248576 ps
CPU time 0.67 seconds
Started Jan 10 12:46:05 PM PST 24
Finished Jan 10 12:47:25 PM PST 24
Peak memory 199128 kb
Host smart-8103676c-900d-4e0c-8c6c-590c02c53c91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058738749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.1058738749
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.1327699056
Short name T35
Test name
Test status
Simulation time 1240287461 ps
CPU time 5.16 seconds
Started Jan 10 12:34:29 PM PST 24
Finished Jan 10 12:35:13 PM PST 24
Peak memory 216000 kb
Host smart-68f097b9-6163-4060-8182-40c636245364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327699056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.1327699056
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.3893781573
Short name T333
Test name
Test status
Simulation time 244247341 ps
CPU time 1.11 seconds
Started Jan 10 12:40:40 PM PST 24
Finished Jan 10 12:41:26 PM PST 24
Peak memory 216536 kb
Host smart-38ec815d-205d-4e2e-9565-f9cfb31b9fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893781573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.3893781573
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.2696951051
Short name T587
Test name
Test status
Simulation time 235582636 ps
CPU time 0.88 seconds
Started Jan 10 12:41:01 PM PST 24
Finished Jan 10 12:41:59 PM PST 24
Peak memory 199068 kb
Host smart-65152eae-4943-408a-bb69-ec8a23ba5602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696951051 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.2696951051
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.3111264302
Short name T337
Test name
Test status
Simulation time 862695191 ps
CPU time 4.46 seconds
Started Jan 10 12:34:58 PM PST 24
Finished Jan 10 12:35:43 PM PST 24
Peak memory 199380 kb
Host smart-0063a965-2f73-4e66-b108-5d60dc5f8c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111264302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.3111264302
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.710760757
Short name T572
Test name
Test status
Simulation time 166570247 ps
CPU time 1.07 seconds
Started Jan 10 12:28:37 PM PST 24
Finished Jan 10 12:28:50 PM PST 24
Peak memory 199068 kb
Host smart-f5a3a35c-ac0e-4329-bc9b-45fe8b909601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710760757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.710760757
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.1217676387
Short name T533
Test name
Test status
Simulation time 202536170 ps
CPU time 1.33 seconds
Started Jan 10 12:44:07 PM PST 24
Finished Jan 10 12:45:34 PM PST 24
Peak memory 199332 kb
Host smart-cf2a4d8e-71f8-4aad-aea8-18cd16ba4875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217676387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.1217676387
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.3992341775
Short name T134
Test name
Test status
Simulation time 2047506911 ps
CPU time 7.91 seconds
Started Jan 10 12:44:42 PM PST 24
Finished Jan 10 12:46:07 PM PST 24
Peak memory 199460 kb
Host smart-b94facc6-3fb9-4952-a92d-911b6e72532f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992341775 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.3992341775
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.435284375
Short name T247
Test name
Test status
Simulation time 117457325 ps
CPU time 1.46 seconds
Started Jan 10 01:11:15 PM PST 24
Finished Jan 10 01:12:42 PM PST 24
Peak memory 199392 kb
Host smart-84856563-5105-4640-a3f7-38fd8894b268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435284375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.435284375
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.3102477936
Short name T504
Test name
Test status
Simulation time 112570904 ps
CPU time 0.86 seconds
Started Jan 10 12:31:19 PM PST 24
Finished Jan 10 12:32:05 PM PST 24
Peak memory 199020 kb
Host smart-cfa006a7-feeb-4fb5-81ad-274b1e916976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102477936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.3102477936
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.3125726618
Short name T294
Test name
Test status
Simulation time 77022589 ps
CPU time 0.73 seconds
Started Jan 10 12:52:40 PM PST 24
Finished Jan 10 12:53:52 PM PST 24
Peak memory 199172 kb
Host smart-84659ae7-ea21-45d6-8ea8-06544c78353e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125726618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.3125726618
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.2517818985
Short name T355
Test name
Test status
Simulation time 1884007894 ps
CPU time 6.85 seconds
Started Jan 10 12:44:05 PM PST 24
Finished Jan 10 12:45:27 PM PST 24
Peak memory 228892 kb
Host smart-0826ae7e-291a-45b3-89d9-a3449b681aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517818985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.2517818985
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.3159358247
Short name T405
Test name
Test status
Simulation time 244082731 ps
CPU time 1.18 seconds
Started Jan 10 12:39:36 PM PST 24
Finished Jan 10 12:40:07 PM PST 24
Peak memory 216456 kb
Host smart-14197e81-ab31-42b8-9024-1fb2aeb9ba95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159358247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.3159358247
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.1471782903
Short name T163
Test name
Test status
Simulation time 238481542 ps
CPU time 1.11 seconds
Started Jan 10 12:44:48 PM PST 24
Finished Jan 10 12:46:07 PM PST 24
Peak memory 199084 kb
Host smart-9551b26e-6fa5-4540-934e-f7f7a34b5e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471782903 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.1471782903
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.2981078100
Short name T586
Test name
Test status
Simulation time 1006326719 ps
CPU time 4.94 seconds
Started Jan 10 01:05:41 PM PST 24
Finished Jan 10 01:07:39 PM PST 24
Peak memory 199524 kb
Host smart-aea037ef-731d-4a40-a3f5-09ec269cba07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981078100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.2981078100
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.1284625234
Short name T560
Test name
Test status
Simulation time 142081051 ps
CPU time 1.13 seconds
Started Jan 10 12:42:42 PM PST 24
Finished Jan 10 12:43:58 PM PST 24
Peak memory 199244 kb
Host smart-45409228-1f2a-4a2e-a5fa-ed6e9cc65765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284625234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.1284625234
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.991023032
Short name T64
Test name
Test status
Simulation time 231199073 ps
CPU time 1.38 seconds
Started Jan 10 12:35:15 PM PST 24
Finished Jan 10 12:35:49 PM PST 24
Peak memory 199452 kb
Host smart-b40636be-9a8b-4b87-b88f-217c28a32fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991023032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.991023032
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.2743914740
Short name T442
Test name
Test status
Simulation time 389903709 ps
CPU time 1.76 seconds
Started Jan 10 12:35:40 PM PST 24
Finished Jan 10 12:36:07 PM PST 24
Peak memory 199404 kb
Host smart-6775e68b-7b35-4c1c-a9d6-e366fb899f04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743914740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.2743914740
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.2169070365
Short name T395
Test name
Test status
Simulation time 484450191 ps
CPU time 2.71 seconds
Started Jan 10 12:30:12 PM PST 24
Finished Jan 10 12:30:55 PM PST 24
Peak memory 199224 kb
Host smart-9026f05c-0af0-4616-8103-0d24f3d7046b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169070365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.2169070365
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.3970445746
Short name T515
Test name
Test status
Simulation time 130040304 ps
CPU time 1.03 seconds
Started Jan 10 12:29:46 PM PST 24
Finished Jan 10 12:30:20 PM PST 24
Peak memory 199284 kb
Host smart-366b08d4-ef64-45f4-a263-620fd06c9e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970445746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.3970445746
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.79221917
Short name T240
Test name
Test status
Simulation time 80492630 ps
CPU time 0.81 seconds
Started Jan 10 12:49:24 PM PST 24
Finished Jan 10 12:51:10 PM PST 24
Peak memory 199140 kb
Host smart-9adad6b3-242c-4431-ac2d-f3c03d8186c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79221917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.79221917
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.2968278611
Short name T595
Test name
Test status
Simulation time 1220124055 ps
CPU time 5.95 seconds
Started Jan 10 01:06:34 PM PST 24
Finished Jan 10 01:07:58 PM PST 24
Peak memory 216484 kb
Host smart-f56e423c-e54a-4400-8ecf-63a9aca7565e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968278611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.2968278611
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.2846227060
Short name T87
Test name
Test status
Simulation time 243527353 ps
CPU time 1.24 seconds
Started Jan 10 12:40:10 PM PST 24
Finished Jan 10 12:40:58 PM PST 24
Peak memory 216588 kb
Host smart-f2cc2f20-e968-46b2-9ed0-87d3dccdf62b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846227060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.2846227060
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.3129912143
Short name T361
Test name
Test status
Simulation time 189405157 ps
CPU time 0.88 seconds
Started Jan 10 12:52:14 PM PST 24
Finished Jan 10 12:53:27 PM PST 24
Peak memory 199084 kb
Host smart-334622c4-5fc5-4e78-8554-022f99a893b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129912143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.3129912143
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.3538189539
Short name T91
Test name
Test status
Simulation time 685161160 ps
CPU time 3.8 seconds
Started Jan 10 12:47:27 PM PST 24
Finished Jan 10 12:48:50 PM PST 24
Peak memory 199464 kb
Host smart-98a8d9f9-ce22-4240-80b1-ef51616cacb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538189539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.3538189539
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.1807387373
Short name T446
Test name
Test status
Simulation time 104698216 ps
CPU time 0.95 seconds
Started Jan 10 12:29:57 PM PST 24
Finished Jan 10 12:30:42 PM PST 24
Peak memory 199188 kb
Host smart-45113f51-3119-4300-8b88-6060fbf712e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807387373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.1807387373
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.3744605144
Short name T589
Test name
Test status
Simulation time 226073919 ps
CPU time 1.38 seconds
Started Jan 10 12:46:32 PM PST 24
Finished Jan 10 12:47:51 PM PST 24
Peak memory 199356 kb
Host smart-e4e8594d-584c-4a31-91f3-480a3d2dc9a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744605144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.3744605144
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.1570294902
Short name T278
Test name
Test status
Simulation time 2010914637 ps
CPU time 7.08 seconds
Started Jan 10 12:37:44 PM PST 24
Finished Jan 10 12:38:26 PM PST 24
Peak memory 199476 kb
Host smart-d7cd27ad-baf9-4640-bc69-97304405ea6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570294902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.1570294902
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.364769192
Short name T537
Test name
Test status
Simulation time 467198665 ps
CPU time 2.45 seconds
Started Jan 10 12:35:29 PM PST 24
Finished Jan 10 12:35:59 PM PST 24
Peak memory 199248 kb
Host smart-e1985a48-f270-436f-a3c0-8c515c906aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364769192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.364769192
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.1223079138
Short name T394
Test name
Test status
Simulation time 144239021 ps
CPU time 1.05 seconds
Started Jan 10 12:43:48 PM PST 24
Finished Jan 10 12:45:04 PM PST 24
Peak memory 199236 kb
Host smart-51699a11-d81d-4eb8-9077-bd4935048e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223079138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.1223079138
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.2188467675
Short name T555
Test name
Test status
Simulation time 56687986 ps
CPU time 0.74 seconds
Started Jan 10 12:28:06 PM PST 24
Finished Jan 10 12:28:22 PM PST 24
Peak memory 199096 kb
Host smart-aac52c5a-0fef-41f1-8cb5-01fbb426cc65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188467675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.2188467675
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.1298070890
Short name T609
Test name
Test status
Simulation time 1893835433 ps
CPU time 8.02 seconds
Started Jan 10 01:00:49 PM PST 24
Finished Jan 10 01:02:35 PM PST 24
Peak memory 217328 kb
Host smart-6ae1f2e0-8d0b-4ecf-a535-7d9f75f79e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298070890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.1298070890
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.1212952741
Short name T481
Test name
Test status
Simulation time 246816015 ps
CPU time 1.03 seconds
Started Jan 10 12:58:29 PM PST 24
Finished Jan 10 12:59:50 PM PST 24
Peak memory 216448 kb
Host smart-6cb52a94-04a8-479a-a7e3-27b6bb2fee65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212952741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.1212952741
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.3491671805
Short name T7
Test name
Test status
Simulation time 121118440 ps
CPU time 0.76 seconds
Started Jan 10 12:29:16 PM PST 24
Finished Jan 10 12:29:40 PM PST 24
Peak memory 199092 kb
Host smart-45d65369-dc94-45a4-b920-42c39b70c86e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491671805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.3491671805
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.3811663505
Short name T597
Test name
Test status
Simulation time 1513536649 ps
CPU time 5.67 seconds
Started Jan 10 12:59:47 PM PST 24
Finished Jan 10 01:01:20 PM PST 24
Peak memory 199432 kb
Host smart-4c462d9b-443d-4d8b-9ba4-aa99babf2d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811663505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.3811663505
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.3039701837
Short name T507
Test name
Test status
Simulation time 104413521 ps
CPU time 1.01 seconds
Started Jan 10 12:57:17 PM PST 24
Finished Jan 10 12:58:31 PM PST 24
Peak memory 199284 kb
Host smart-ceec395a-3b3d-485b-9bbc-1b008c7a3a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039701837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.3039701837
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.3499559814
Short name T131
Test name
Test status
Simulation time 220915314 ps
CPU time 1.48 seconds
Started Jan 10 12:40:58 PM PST 24
Finished Jan 10 12:41:56 PM PST 24
Peak memory 199416 kb
Host smart-0febec4a-db8c-4bcc-8609-ebc8fd40bcfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499559814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.3499559814
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.155664947
Short name T328
Test name
Test status
Simulation time 4618944829 ps
CPU time 19.62 seconds
Started Jan 10 01:04:45 PM PST 24
Finished Jan 10 01:06:36 PM PST 24
Peak memory 198608 kb
Host smart-d33b1c4e-661b-4f3f-b9fa-3c8e6c40cae0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155664947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.155664947
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.1453534469
Short name T463
Test name
Test status
Simulation time 444951045 ps
CPU time 2.22 seconds
Started Jan 10 01:20:50 PM PST 24
Finished Jan 10 01:20:57 PM PST 24
Peak memory 199208 kb
Host smart-412669a8-02f1-42a7-9700-ac09fd0c5975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453534469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.1453534469
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.1352010871
Short name T598
Test name
Test status
Simulation time 156574678 ps
CPU time 1.21 seconds
Started Jan 10 12:40:02 PM PST 24
Finished Jan 10 12:40:47 PM PST 24
Peak memory 199472 kb
Host smart-df169e61-9713-4672-8b09-ac3934f696e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352010871 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.1352010871
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.1408875642
Short name T561
Test name
Test status
Simulation time 69154661 ps
CPU time 0.72 seconds
Started Jan 10 12:29:55 PM PST 24
Finished Jan 10 12:30:34 PM PST 24
Peak memory 198852 kb
Host smart-596b1d0f-5340-41a7-8eef-bebddf2a2a82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408875642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.1408875642
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.2870305861
Short name T31
Test name
Test status
Simulation time 2165006636 ps
CPU time 8.25 seconds
Started Jan 10 12:40:22 PM PST 24
Finished Jan 10 12:41:17 PM PST 24
Peak memory 220428 kb
Host smart-f34893f5-e123-4d18-8b4b-0f12ea29aaf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870305861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.2870305861
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.1756588400
Short name T353
Test name
Test status
Simulation time 244693986 ps
CPU time 1.04 seconds
Started Jan 10 12:34:27 PM PST 24
Finished Jan 10 12:35:05 PM PST 24
Peak memory 216308 kb
Host smart-86d6e702-1b95-4b5d-9bcd-af249c400ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756588400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.1756588400
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.2818916956
Short name T460
Test name
Test status
Simulation time 82665188 ps
CPU time 0.8 seconds
Started Jan 10 01:51:26 PM PST 24
Finished Jan 10 01:51:28 PM PST 24
Peak memory 199168 kb
Host smart-b56bce09-0b8d-4d38-ae32-47c7ce8ca57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818916956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.2818916956
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.403647448
Short name T335
Test name
Test status
Simulation time 989459133 ps
CPU time 4.33 seconds
Started Jan 10 12:30:10 PM PST 24
Finished Jan 10 12:30:55 PM PST 24
Peak memory 199344 kb
Host smart-62c7c637-662d-41f8-9f40-78365ffd28fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403647448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.403647448
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.3172327959
Short name T403
Test name
Test status
Simulation time 108783789 ps
CPU time 0.98 seconds
Started Jan 10 12:42:56 PM PST 24
Finished Jan 10 12:44:11 PM PST 24
Peak memory 199264 kb
Host smart-8b52680a-83ec-403d-859d-9abda37f7e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172327959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.3172327959
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.985890618
Short name T585
Test name
Test status
Simulation time 109571125 ps
CPU time 1.18 seconds
Started Jan 10 12:39:15 PM PST 24
Finished Jan 10 12:39:45 PM PST 24
Peak memory 199456 kb
Host smart-eb08d469-9178-427b-bbb9-83f084c1bb19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985890618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.985890618
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.414761291
Short name T603
Test name
Test status
Simulation time 3203297689 ps
CPU time 13.62 seconds
Started Jan 10 12:35:08 PM PST 24
Finished Jan 10 12:35:57 PM PST 24
Peak memory 199476 kb
Host smart-c2bd1d90-9ada-487c-b6f7-e9c09f03ff01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414761291 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.414761291
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.2036059812
Short name T526
Test name
Test status
Simulation time 390162149 ps
CPU time 2.11 seconds
Started Jan 10 12:52:13 PM PST 24
Finished Jan 10 12:53:30 PM PST 24
Peak memory 199268 kb
Host smart-db9bf82a-75c8-4c7d-b04b-2a0c0a097280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036059812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.2036059812
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.3254756880
Short name T485
Test name
Test status
Simulation time 220483734 ps
CPU time 1.2 seconds
Started Jan 10 12:28:33 PM PST 24
Finished Jan 10 12:28:46 PM PST 24
Peak memory 199256 kb
Host smart-712faa4d-6f3f-4597-ac66-1913c23eacc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254756880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.3254756880
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.742560876
Short name T383
Test name
Test status
Simulation time 76647511 ps
CPU time 0.75 seconds
Started Jan 10 12:31:04 PM PST 24
Finished Jan 10 12:31:52 PM PST 24
Peak memory 198840 kb
Host smart-6c530595-3218-4b30-91b5-bc80dbb0ef41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742560876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.742560876
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.2688626895
Short name T29
Test name
Test status
Simulation time 2364967486 ps
CPU time 7.98 seconds
Started Jan 10 12:27:48 PM PST 24
Finished Jan 10 12:28:09 PM PST 24
Peak memory 216388 kb
Host smart-5e97cf47-26a2-422c-ba78-a3bb56bd5d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688626895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.2688626895
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.901083792
Short name T425
Test name
Test status
Simulation time 244495457 ps
CPU time 1.12 seconds
Started Jan 10 12:46:35 PM PST 24
Finished Jan 10 12:47:50 PM PST 24
Peak memory 216564 kb
Host smart-4a59fe0f-5340-4262-97d8-ea1ada567100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901083792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.901083792
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.1023594527
Short name T376
Test name
Test status
Simulation time 130070834 ps
CPU time 0.76 seconds
Started Jan 10 12:36:08 PM PST 24
Finished Jan 10 12:36:38 PM PST 24
Peak memory 199080 kb
Host smart-d9d2647a-8789-41e5-baa3-7ef4fe244c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023594527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.1023594527
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.2386353430
Short name T160
Test name
Test status
Simulation time 917705621 ps
CPU time 4.56 seconds
Started Jan 10 12:29:20 PM PST 24
Finished Jan 10 12:29:49 PM PST 24
Peak memory 199384 kb
Host smart-c499caee-9c3d-499f-9947-4e4689440114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386353430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.2386353430
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.3273645891
Short name T143
Test name
Test status
Simulation time 97453602 ps
CPU time 0.95 seconds
Started Jan 10 12:56:09 PM PST 24
Finished Jan 10 12:57:19 PM PST 24
Peak memory 199332 kb
Host smart-da1916ee-0a9e-41b1-be11-b7f0f4fe42be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273645891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.3273645891
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.3126101450
Short name T573
Test name
Test status
Simulation time 259109571 ps
CPU time 1.4 seconds
Started Jan 10 12:46:24 PM PST 24
Finished Jan 10 12:47:44 PM PST 24
Peak memory 199452 kb
Host smart-f85c6f0f-b4ab-4bff-8d02-c5754de5c9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126101450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.3126101450
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.3654754322
Short name T63
Test name
Test status
Simulation time 4018893756 ps
CPU time 13.88 seconds
Started Jan 10 12:30:48 PM PST 24
Finished Jan 10 12:31:47 PM PST 24
Peak memory 199096 kb
Host smart-24f65071-6835-4e55-b2d4-75df5bbf8c6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654754322 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.3654754322
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.418428100
Short name T447
Test name
Test status
Simulation time 127454139 ps
CPU time 1.71 seconds
Started Jan 10 12:28:33 PM PST 24
Finished Jan 10 12:28:47 PM PST 24
Peak memory 199272 kb
Host smart-d05c45b7-901d-4a74-8510-e128c70a83f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418428100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.418428100
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.3364735706
Short name T536
Test name
Test status
Simulation time 123705560 ps
CPU time 1.02 seconds
Started Jan 10 12:30:48 PM PST 24
Finished Jan 10 12:31:34 PM PST 24
Peak memory 197480 kb
Host smart-d4526cda-428b-47e5-9dd5-66d84e0ff971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364735706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.3364735706
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.1563392577
Short name T305
Test name
Test status
Simulation time 71438434 ps
CPU time 0.75 seconds
Started Jan 10 12:41:16 PM PST 24
Finished Jan 10 12:42:24 PM PST 24
Peak memory 199204 kb
Host smart-12bf9f5c-5fdd-463d-8e1f-cc4b776e2c69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563392577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.1563392577
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.1166618746
Short name T534
Test name
Test status
Simulation time 1228088043 ps
CPU time 6.25 seconds
Started Jan 10 12:49:06 PM PST 24
Finished Jan 10 12:50:43 PM PST 24
Peak memory 217248 kb
Host smart-68684a71-2d50-45bb-beda-824c65c811ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166618746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.1166618746
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.2190044621
Short name T367
Test name
Test status
Simulation time 244200121 ps
CPU time 1.12 seconds
Started Jan 10 12:40:52 PM PST 24
Finished Jan 10 12:41:44 PM PST 24
Peak memory 216468 kb
Host smart-64a6756e-938d-485a-b10b-188ec62dd87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190044621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.2190044621
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.3385667441
Short name T477
Test name
Test status
Simulation time 176899852 ps
CPU time 0.86 seconds
Started Jan 10 12:29:21 PM PST 24
Finished Jan 10 12:29:47 PM PST 24
Peak memory 198780 kb
Host smart-6a53742d-444e-4f57-b9bd-edbde9ed4e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385667441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.3385667441
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.511256465
Short name T23
Test name
Test status
Simulation time 953455865 ps
CPU time 4.52 seconds
Started Jan 10 12:30:03 PM PST 24
Finished Jan 10 12:30:49 PM PST 24
Peak memory 197552 kb
Host smart-40eacbd4-1ee4-4412-a02f-ec9c42a15cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511256465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.511256465
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.2600181667
Short name T82
Test name
Test status
Simulation time 16568362510 ps
CPU time 28.39 seconds
Started Jan 10 12:36:16 PM PST 24
Finished Jan 10 12:37:19 PM PST 24
Peak memory 217396 kb
Host smart-2aeaad3c-499d-47bd-baaf-bf13bc5d5963
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600181667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.2600181667
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.3641293082
Short name T605
Test name
Test status
Simulation time 143915089 ps
CPU time 1.11 seconds
Started Jan 10 12:28:02 PM PST 24
Finished Jan 10 12:28:18 PM PST 24
Peak memory 199576 kb
Host smart-44b0cc43-f940-4550-8111-09d90e1f8887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641293082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.3641293082
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.3905062949
Short name T389
Test name
Test status
Simulation time 246570222 ps
CPU time 1.42 seconds
Started Jan 10 12:39:23 PM PST 24
Finished Jan 10 12:39:53 PM PST 24
Peak memory 199492 kb
Host smart-d6b834d4-42ee-4ed2-8321-c18f40bcd8b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905062949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.3905062949
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.3856890645
Short name T369
Test name
Test status
Simulation time 8050092311 ps
CPU time 25.47 seconds
Started Jan 10 12:44:07 PM PST 24
Finished Jan 10 12:46:00 PM PST 24
Peak memory 199544 kb
Host smart-70e95ccd-ef3a-4924-b5f9-ce5b643b5e3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856890645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.3856890645
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.3059446555
Short name T304
Test name
Test status
Simulation time 278326630 ps
CPU time 1.77 seconds
Started Jan 10 02:09:13 PM PST 24
Finished Jan 10 02:09:19 PM PST 24
Peak memory 199332 kb
Host smart-ed5db66d-3e7e-4c6b-b00b-68fc985fd374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059446555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.3059446555
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.2593360942
Short name T130
Test name
Test status
Simulation time 175772763 ps
CPU time 1.1 seconds
Started Jan 10 12:34:52 PM PST 24
Finished Jan 10 12:35:35 PM PST 24
Peak memory 199292 kb
Host smart-c67ce5ce-ccda-41a9-9fcc-895fd610970f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593360942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.2593360942
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.2363883683
Short name T330
Test name
Test status
Simulation time 80953128 ps
CPU time 0.75 seconds
Started Jan 10 12:28:43 PM PST 24
Finished Jan 10 12:28:58 PM PST 24
Peak memory 199064 kb
Host smart-869d52f5-43d4-41cf-9cb6-9f6fd7aad6a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363883683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.2363883683
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.3652548219
Short name T467
Test name
Test status
Simulation time 248943800 ps
CPU time 1.06 seconds
Started Jan 10 12:39:12 PM PST 24
Finished Jan 10 12:39:43 PM PST 24
Peak memory 216580 kb
Host smart-8838f10e-5a23-4c42-abe7-926a0b4ccbfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652548219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.3652548219
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.2014526056
Short name T277
Test name
Test status
Simulation time 106788063 ps
CPU time 0.74 seconds
Started Jan 10 12:25:47 PM PST 24
Finished Jan 10 12:25:48 PM PST 24
Peak memory 199076 kb
Host smart-4c3df417-4570-4a0d-b632-e782a06cff11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014526056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.2014526056
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.4283854667
Short name T441
Test name
Test status
Simulation time 902914742 ps
CPU time 4.24 seconds
Started Jan 10 12:30:22 PM PST 24
Finished Jan 10 12:31:07 PM PST 24
Peak memory 199128 kb
Host smart-7ba3a3a3-07d1-46d6-9e8c-b9be806457f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283854667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.4283854667
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.2083167403
Short name T358
Test name
Test status
Simulation time 102156283 ps
CPU time 0.99 seconds
Started Jan 10 12:26:18 PM PST 24
Finished Jan 10 12:26:21 PM PST 24
Peak memory 199604 kb
Host smart-e6e7711b-44ab-4b87-b95c-20bec124ccb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083167403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.2083167403
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.897729173
Short name T84
Test name
Test status
Simulation time 222497171 ps
CPU time 1.32 seconds
Started Jan 10 12:31:04 PM PST 24
Finished Jan 10 12:31:52 PM PST 24
Peak memory 199168 kb
Host smart-deab8947-e8e6-4738-a144-e53bdabf3f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897729173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.897729173
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.1383508713
Short name T61
Test name
Test status
Simulation time 1156575908 ps
CPU time 4.8 seconds
Started Jan 10 12:29:57 PM PST 24
Finished Jan 10 12:30:42 PM PST 24
Peak memory 198552 kb
Host smart-9f1c8a19-1b37-4e62-aa38-6533e0d0c56f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383508713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.1383508713
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.3355691492
Short name T422
Test name
Test status
Simulation time 116704590 ps
CPU time 1.42 seconds
Started Jan 10 12:40:55 PM PST 24
Finished Jan 10 12:41:48 PM PST 24
Peak memory 199324 kb
Host smart-dc0fb50c-6477-4dda-9eb4-331d18dfc33c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355691492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.3355691492
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.1225168793
Short name T583
Test name
Test status
Simulation time 105033857 ps
CPU time 0.91 seconds
Started Jan 10 12:34:26 PM PST 24
Finished Jan 10 12:35:04 PM PST 24
Peak memory 199148 kb
Host smart-7550a891-b443-48be-afaa-85cdf757e2c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225168793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.1225168793
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.3820789370
Short name T496
Test name
Test status
Simulation time 63736185 ps
CPU time 0.71 seconds
Started Jan 10 01:12:52 PM PST 24
Finished Jan 10 01:14:16 PM PST 24
Peak memory 199216 kb
Host smart-d683d147-bfe5-4c16-b359-69449be6922d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820789370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.3820789370
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.50147371
Short name T520
Test name
Test status
Simulation time 1237007110 ps
CPU time 5.75 seconds
Started Jan 10 12:28:38 PM PST 24
Finished Jan 10 12:28:56 PM PST 24
Peak memory 221336 kb
Host smart-02da95ed-9a2e-417c-91f4-43647248d45a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50147371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.50147371
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.4092939547
Short name T151
Test name
Test status
Simulation time 244201368 ps
CPU time 1.09 seconds
Started Jan 10 12:50:51 PM PST 24
Finished Jan 10 12:52:24 PM PST 24
Peak memory 216512 kb
Host smart-dae00bc6-c9bd-41e8-81e7-d03055a3c799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092939547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.4092939547
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.2670081870
Short name T494
Test name
Test status
Simulation time 84872825 ps
CPU time 0.69 seconds
Started Jan 10 12:30:30 PM PST 24
Finished Jan 10 12:31:13 PM PST 24
Peak memory 198776 kb
Host smart-4fe0c345-627d-4cf4-91ea-d6d04430cf4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670081870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.2670081870
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.2888533097
Short name T268
Test name
Test status
Simulation time 1334750076 ps
CPU time 5.7 seconds
Started Jan 10 12:58:45 PM PST 24
Finished Jan 10 01:00:14 PM PST 24
Peak memory 199468 kb
Host smart-2ee3d480-4f54-439e-b964-08e6304fb79e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888533097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.2888533097
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.3239307737
Short name T262
Test name
Test status
Simulation time 107608774 ps
CPU time 1.01 seconds
Started Jan 10 12:39:55 PM PST 24
Finished Jan 10 12:40:33 PM PST 24
Peak memory 199284 kb
Host smart-561dace0-13a5-40e4-aee5-06ce12f42e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239307737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.3239307737
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.2530084371
Short name T321
Test name
Test status
Simulation time 115563913 ps
CPU time 1.15 seconds
Started Jan 10 12:30:48 PM PST 24
Finished Jan 10 12:31:34 PM PST 24
Peak memory 198164 kb
Host smart-d28161b3-1ab0-4b6d-9f8d-3877ee1a29cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530084371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.2530084371
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.2359292416
Short name T272
Test name
Test status
Simulation time 2134086648 ps
CPU time 10.39 seconds
Started Jan 10 01:07:45 PM PST 24
Finished Jan 10 01:09:16 PM PST 24
Peak memory 199468 kb
Host smart-d1ad9c6a-7b8d-415a-91b7-1ea85338c948
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359292416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.2359292416
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.4016058815
Short name T464
Test name
Test status
Simulation time 319077908 ps
CPU time 2.14 seconds
Started Jan 10 12:37:42 PM PST 24
Finished Jan 10 12:38:20 PM PST 24
Peak memory 199260 kb
Host smart-03e633a6-8e9a-45e0-a92d-a30b2f5c0715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016058815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.4016058815
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.3132553280
Short name T327
Test name
Test status
Simulation time 99279126 ps
CPU time 0.9 seconds
Started Jan 10 12:39:25 PM PST 24
Finished Jan 10 12:39:56 PM PST 24
Peak memory 199348 kb
Host smart-70d9446b-b46d-49c0-84aa-707129e9f282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132553280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.3132553280
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.4121299736
Short name T144
Test name
Test status
Simulation time 54122023 ps
CPU time 0.68 seconds
Started Jan 10 12:36:19 PM PST 24
Finished Jan 10 12:36:54 PM PST 24
Peak memory 199204 kb
Host smart-8e3ac32d-dc0e-4084-92bd-22edce8b3475
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121299736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.4121299736
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.1899851523
Short name T55
Test name
Test status
Simulation time 1227214168 ps
CPU time 5.8 seconds
Started Jan 10 12:40:14 PM PST 24
Finished Jan 10 12:41:07 PM PST 24
Peak memory 217740 kb
Host smart-f0aef33b-9945-4cdd-b390-6f35aa7433c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899851523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.1899851523
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.648692753
Short name T290
Test name
Test status
Simulation time 243613972 ps
CPU time 1.06 seconds
Started Jan 10 12:29:20 PM PST 24
Finished Jan 10 12:29:45 PM PST 24
Peak memory 216488 kb
Host smart-f767e432-e683-4d29-957e-fae19062884a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648692753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.648692753
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.1310439706
Short name T370
Test name
Test status
Simulation time 196243833 ps
CPU time 0.83 seconds
Started Jan 10 12:56:30 PM PST 24
Finished Jan 10 12:57:41 PM PST 24
Peak memory 199140 kb
Host smart-4a543df0-91ef-4d76-be8d-51d451760183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310439706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.1310439706
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.445959469
Short name T42
Test name
Test status
Simulation time 1507164055 ps
CPU time 5.53 seconds
Started Jan 10 12:50:07 PM PST 24
Finished Jan 10 12:51:35 PM PST 24
Peak memory 199492 kb
Host smart-d0f67996-c9d5-4f5b-be54-16ac125a78df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445959469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.445959469
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.1663727351
Short name T575
Test name
Test status
Simulation time 181571219 ps
CPU time 1.13 seconds
Started Jan 10 12:40:39 PM PST 24
Finished Jan 10 12:41:25 PM PST 24
Peak memory 199252 kb
Host smart-07eca6e3-3611-4f7f-b880-3b6d27dd4932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663727351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.1663727351
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.1329266901
Short name T448
Test name
Test status
Simulation time 258666419 ps
CPU time 1.46 seconds
Started Jan 10 12:52:55 PM PST 24
Finished Jan 10 12:54:09 PM PST 24
Peak memory 199396 kb
Host smart-685a218d-4dac-4fb5-ae56-86595b395d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329266901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.1329266901
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.4103293308
Short name T347
Test name
Test status
Simulation time 2082090222 ps
CPU time 10.39 seconds
Started Jan 10 12:44:06 PM PST 24
Finished Jan 10 12:45:32 PM PST 24
Peak memory 199388 kb
Host smart-8737e0a8-48b8-4e24-a05d-17b768e46b77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103293308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.4103293308
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.423097131
Short name T283
Test name
Test status
Simulation time 109612354 ps
CPU time 1.37 seconds
Started Jan 10 12:53:15 PM PST 24
Finished Jan 10 12:54:29 PM PST 24
Peak memory 199264 kb
Host smart-26fce6a7-b530-40ec-8e49-d9b3bb438ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423097131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.423097131
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.622860788
Short name T541
Test name
Test status
Simulation time 67897647 ps
CPU time 0.73 seconds
Started Jan 10 12:44:53 PM PST 24
Finished Jan 10 12:46:15 PM PST 24
Peak memory 199120 kb
Host smart-95547f97-a6e5-49d4-b2ef-db796caeabb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622860788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.622860788
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.3175875352
Short name T503
Test name
Test status
Simulation time 1895132669 ps
CPU time 6.49 seconds
Started Jan 10 12:47:04 PM PST 24
Finished Jan 10 12:48:31 PM PST 24
Peak memory 221268 kb
Host smart-594c8fb1-2d5e-4ea5-b19c-a29eff21b15e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175875352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.3175875352
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.3616114445
Short name T512
Test name
Test status
Simulation time 244407183 ps
CPU time 1.06 seconds
Started Jan 10 12:37:53 PM PST 24
Finished Jan 10 12:38:27 PM PST 24
Peak memory 216488 kb
Host smart-89f670c4-0285-43bd-8121-2646006e3081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616114445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.3616114445
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.3527285151
Short name T258
Test name
Test status
Simulation time 119569251 ps
CPU time 0.78 seconds
Started Jan 10 12:55:49 PM PST 24
Finished Jan 10 12:56:57 PM PST 24
Peak memory 199116 kb
Host smart-b530c5ad-73e5-4f0f-b136-8443c4225960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527285151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.3527285151
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.2970683298
Short name T4
Test name
Test status
Simulation time 1384789103 ps
CPU time 5.74 seconds
Started Jan 10 12:36:06 PM PST 24
Finished Jan 10 12:36:38 PM PST 24
Peak memory 199392 kb
Host smart-7e9fd2eb-4e54-4538-8e93-6157dcf7dd4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970683298 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.2970683298
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.1035212605
Short name T311
Test name
Test status
Simulation time 139982749 ps
CPU time 1 seconds
Started Jan 10 12:45:41 PM PST 24
Finished Jan 10 12:47:01 PM PST 24
Peak memory 199276 kb
Host smart-639c98b9-3dbf-4e52-9062-43c7132f5f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035212605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.1035212605
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.1412275672
Short name T505
Test name
Test status
Simulation time 117455374 ps
CPU time 1.13 seconds
Started Jan 10 12:47:26 PM PST 24
Finished Jan 10 12:48:49 PM PST 24
Peak memory 199480 kb
Host smart-8b22b0fb-c2ce-4e2a-b99c-fcd64773cd8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412275672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.1412275672
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.691397995
Short name T380
Test name
Test status
Simulation time 6837002508 ps
CPU time 22.95 seconds
Started Jan 10 12:34:53 PM PST 24
Finished Jan 10 12:35:57 PM PST 24
Peak memory 199536 kb
Host smart-264a0798-0812-4996-94ce-c48450ecd587
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691397995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.691397995
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.2849712991
Short name T578
Test name
Test status
Simulation time 288291181 ps
CPU time 1.92 seconds
Started Jan 10 12:40:11 PM PST 24
Finished Jan 10 12:41:00 PM PST 24
Peak memory 199196 kb
Host smart-1cbd1b17-0dae-4c0d-9525-e2f1b7ee1e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849712991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.2849712991
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.3706824155
Short name T351
Test name
Test status
Simulation time 192125609 ps
CPU time 1.27 seconds
Started Jan 10 12:54:03 PM PST 24
Finished Jan 10 12:55:12 PM PST 24
Peak memory 199328 kb
Host smart-08e06d6e-2c39-4401-a852-b96455a5b041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706824155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.3706824155
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.1708751929
Short name T423
Test name
Test status
Simulation time 78901264 ps
CPU time 0.73 seconds
Started Jan 10 12:35:09 PM PST 24
Finished Jan 10 12:35:45 PM PST 24
Peak memory 199116 kb
Host smart-a5ad76f7-51ad-4597-a983-8b633a11b586
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708751929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.1708751929
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.4136935721
Short name T386
Test name
Test status
Simulation time 244445093 ps
CPU time 1.15 seconds
Started Jan 10 12:28:08 PM PST 24
Finished Jan 10 12:28:25 PM PST 24
Peak memory 214840 kb
Host smart-388d753f-0ce8-4a98-847e-10f2b17c1d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136935721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.4136935721
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.544703509
Short name T397
Test name
Test status
Simulation time 136320353 ps
CPU time 0.8 seconds
Started Jan 10 12:40:00 PM PST 24
Finished Jan 10 12:40:42 PM PST 24
Peak memory 198984 kb
Host smart-1c846d40-cf6d-4384-86a3-1d38f8763e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544703509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.544703509
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.2835624237
Short name T256
Test name
Test status
Simulation time 861444911 ps
CPU time 4.23 seconds
Started Jan 10 12:28:08 PM PST 24
Finished Jan 10 12:28:28 PM PST 24
Peak memory 197980 kb
Host smart-8e655f02-736c-4866-a371-4b2ef5b808f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835624237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.2835624237
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.4138680950
Short name T411
Test name
Test status
Simulation time 174941236 ps
CPU time 1.22 seconds
Started Jan 10 12:58:21 PM PST 24
Finished Jan 10 12:59:41 PM PST 24
Peak memory 199288 kb
Host smart-f6aea2d7-7ca3-4849-a863-70cf59a83161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138680950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.4138680950
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.2521617180
Short name T404
Test name
Test status
Simulation time 199151603 ps
CPU time 1.46 seconds
Started Jan 10 12:36:28 PM PST 24
Finished Jan 10 12:37:03 PM PST 24
Peak memory 199412 kb
Host smart-615511ee-06fb-4f3a-82a2-52f8e9f4cd80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521617180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.2521617180
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.2124546245
Short name T326
Test name
Test status
Simulation time 926203842 ps
CPU time 4.22 seconds
Started Jan 10 12:46:52 PM PST 24
Finished Jan 10 12:48:13 PM PST 24
Peak memory 199484 kb
Host smart-86a9fb7c-69f2-4768-a37a-eb9a30a6983e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124546245 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.2124546245
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.2781944030
Short name T152
Test name
Test status
Simulation time 424540747 ps
CPU time 2.12 seconds
Started Jan 10 12:28:10 PM PST 24
Finished Jan 10 12:28:27 PM PST 24
Peak memory 198916 kb
Host smart-ab1f548f-a91b-4ca7-b4bb-2250760201c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781944030 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.2781944030
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.2125670461
Short name T238
Test name
Test status
Simulation time 142987672 ps
CPU time 1.06 seconds
Started Jan 10 12:49:24 PM PST 24
Finished Jan 10 12:50:56 PM PST 24
Peak memory 199288 kb
Host smart-da297a7a-e249-4e8e-be6a-a07a3ea39f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125670461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.2125670461
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.2975803771
Short name T89
Test name
Test status
Simulation time 62289717 ps
CPU time 0.7 seconds
Started Jan 10 12:40:18 PM PST 24
Finished Jan 10 12:41:06 PM PST 24
Peak memory 199052 kb
Host smart-521242b3-0f59-40b8-9405-8c746ec4fcbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975803771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.2975803771
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.149464279
Short name T41
Test name
Test status
Simulation time 1233998847 ps
CPU time 5.18 seconds
Started Jan 10 12:27:44 PM PST 24
Finished Jan 10 12:28:02 PM PST 24
Peak memory 216516 kb
Host smart-37337125-674f-4913-869d-8f0d7eda6b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149464279 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.149464279
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.1911983861
Short name T473
Test name
Test status
Simulation time 244623011 ps
CPU time 1.11 seconds
Started Jan 10 12:36:06 PM PST 24
Finished Jan 10 12:36:34 PM PST 24
Peak memory 216392 kb
Host smart-13fa431a-1642-4235-9e7a-9bc557a5e062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911983861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.1911983861
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.2497219197
Short name T385
Test name
Test status
Simulation time 138064084 ps
CPU time 0.79 seconds
Started Jan 10 12:28:01 PM PST 24
Finished Jan 10 12:28:16 PM PST 24
Peak memory 199008 kb
Host smart-02fc78fb-49a8-4f2d-bc87-fb8bb3177f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497219197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.2497219197
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.3767377064
Short name T540
Test name
Test status
Simulation time 1732453171 ps
CPU time 6.28 seconds
Started Jan 10 12:34:49 PM PST 24
Finished Jan 10 12:35:37 PM PST 24
Peak memory 199516 kb
Host smart-677977a5-a17e-470d-94bb-e66e60989aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767377064 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.3767377064
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.956507705
Short name T522
Test name
Test status
Simulation time 145866283 ps
CPU time 1.1 seconds
Started Jan 10 12:28:28 PM PST 24
Finished Jan 10 12:28:40 PM PST 24
Peak memory 198732 kb
Host smart-a32bb128-34f4-4bc2-90e5-d0de0696f286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956507705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.956507705
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.557516247
Short name T591
Test name
Test status
Simulation time 206332238 ps
CPU time 1.45 seconds
Started Jan 10 12:29:07 PM PST 24
Finished Jan 10 12:29:30 PM PST 24
Peak memory 199424 kb
Host smart-d0d56cd4-9f20-45b2-87c5-9bd8fe906d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557516247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.557516247
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.1724998899
Short name T432
Test name
Test status
Simulation time 8181186302 ps
CPU time 30.93 seconds
Started Jan 10 12:38:45 PM PST 24
Finished Jan 10 12:39:49 PM PST 24
Peak memory 199476 kb
Host smart-d6cb8811-678c-4ec2-948a-124ee3ead533
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724998899 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.1724998899
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.1789418705
Short name T582
Test name
Test status
Simulation time 268785565 ps
CPU time 1.89 seconds
Started Jan 10 01:04:36 PM PST 24
Finished Jan 10 01:06:00 PM PST 24
Peak memory 199340 kb
Host smart-25aafd6b-61a4-40d2-b75a-f69378140612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789418705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.1789418705
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.1659137572
Short name T570
Test name
Test status
Simulation time 229619999 ps
CPU time 1.28 seconds
Started Jan 10 12:49:57 PM PST 24
Finished Jan 10 12:51:40 PM PST 24
Peak memory 199324 kb
Host smart-1fb4916d-c70c-463a-aef8-6dbe2fff8242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659137572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.1659137572
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.499260581
Short name T308
Test name
Test status
Simulation time 87158149 ps
CPU time 0.75 seconds
Started Jan 10 12:44:10 PM PST 24
Finished Jan 10 12:45:27 PM PST 24
Peak memory 199088 kb
Host smart-ff413d02-1cd0-4045-9226-14aad68f1a4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499260581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.499260581
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.706310087
Short name T592
Test name
Test status
Simulation time 1897923145 ps
CPU time 7.58 seconds
Started Jan 10 12:38:05 PM PST 24
Finished Jan 10 12:38:47 PM PST 24
Peak memory 216672 kb
Host smart-ced9d4f2-e5a8-405f-ac8a-9c941cc9aa10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706310087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.706310087
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.1277369664
Short name T284
Test name
Test status
Simulation time 244859327 ps
CPU time 1.15 seconds
Started Jan 10 12:29:25 PM PST 24
Finished Jan 10 12:29:53 PM PST 24
Peak memory 216404 kb
Host smart-e25f1c25-c63c-4771-a4a7-a9ec38a017f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277369664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.1277369664
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.935169018
Short name T18
Test name
Test status
Simulation time 80949533 ps
CPU time 0.68 seconds
Started Jan 10 12:38:53 PM PST 24
Finished Jan 10 12:39:27 PM PST 24
Peak memory 199032 kb
Host smart-8ded4c1a-bb65-41db-a59d-d49fcf7b776f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935169018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.935169018
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.2613609691
Short name T437
Test name
Test status
Simulation time 880072934 ps
CPU time 4.04 seconds
Started Jan 10 12:34:26 PM PST 24
Finished Jan 10 12:35:07 PM PST 24
Peak memory 199452 kb
Host smart-3a744d40-6a88-4abe-b5b5-9a33baa2da56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613609691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.2613609691
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.1601445650
Short name T549
Test name
Test status
Simulation time 165829919 ps
CPU time 1.18 seconds
Started Jan 10 12:46:11 PM PST 24
Finished Jan 10 12:47:31 PM PST 24
Peak memory 199344 kb
Host smart-44936e6a-6e6c-4ced-8fa0-153a0d77a365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601445650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.1601445650
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.1781640982
Short name T250
Test name
Test status
Simulation time 257619640 ps
CPU time 1.52 seconds
Started Jan 10 12:49:00 PM PST 24
Finished Jan 10 12:50:37 PM PST 24
Peak memory 199404 kb
Host smart-db4b4efe-2a5d-4567-8774-b4809afadacc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781640982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.1781640982
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.330076452
Short name T338
Test name
Test status
Simulation time 1495619957 ps
CPU time 5.26 seconds
Started Jan 10 12:30:03 PM PST 24
Finished Jan 10 12:30:50 PM PST 24
Peak memory 199384 kb
Host smart-ea03dfee-89b6-4258-8910-23f9ec7f5873
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330076452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.330076452
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.3063448848
Short name T596
Test name
Test status
Simulation time 137821257 ps
CPU time 1.65 seconds
Started Jan 10 01:02:28 PM PST 24
Finished Jan 10 01:03:57 PM PST 24
Peak memory 199232 kb
Host smart-c3d39cc4-40ea-4bc3-a8f3-33c1fd1db14e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063448848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.3063448848
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.3101611490
Short name T514
Test name
Test status
Simulation time 173073079 ps
CPU time 1.22 seconds
Started Jan 10 12:41:14 PM PST 24
Finished Jan 10 12:42:16 PM PST 24
Peak memory 199368 kb
Host smart-169b49bb-9948-40c3-a803-2c6144d222d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101611490 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.3101611490
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.4174907396
Short name T484
Test name
Test status
Simulation time 60827268 ps
CPU time 0.69 seconds
Started Jan 10 12:28:50 PM PST 24
Finished Jan 10 12:29:07 PM PST 24
Peak memory 199096 kb
Host smart-79834af1-703d-4a18-9fa0-569cb82f3aa4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174907396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.4174907396
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.285644468
Short name T531
Test name
Test status
Simulation time 1221503656 ps
CPU time 5.12 seconds
Started Jan 10 12:29:02 PM PST 24
Finished Jan 10 12:29:26 PM PST 24
Peak memory 220476 kb
Host smart-9ec0b3be-57f1-4856-b64a-b99f9737436f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285644468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.285644468
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.3464091494
Short name T556
Test name
Test status
Simulation time 247910206 ps
CPU time 1.02 seconds
Started Jan 10 12:28:25 PM PST 24
Finished Jan 10 12:28:37 PM PST 24
Peak memory 216288 kb
Host smart-80a02b65-d95b-47d0-a1bb-a0b53f71ac42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464091494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.3464091494
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.2655250665
Short name T19
Test name
Test status
Simulation time 73982271 ps
CPU time 0.66 seconds
Started Jan 10 12:31:15 PM PST 24
Finished Jan 10 12:32:00 PM PST 24
Peak memory 198820 kb
Host smart-19a4d859-c20e-442c-9a1b-beceaef74d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655250665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.2655250665
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.2849262727
Short name T535
Test name
Test status
Simulation time 1643553383 ps
CPU time 5.79 seconds
Started Jan 10 12:28:17 PM PST 24
Finished Jan 10 12:28:36 PM PST 24
Peak memory 199124 kb
Host smart-6c8f2de4-b7a7-4080-822c-afaf97b0c506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849262727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.2849262727
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.1029866743
Short name T8
Test name
Test status
Simulation time 159033593 ps
CPU time 1.08 seconds
Started Jan 10 12:28:50 PM PST 24
Finished Jan 10 12:29:07 PM PST 24
Peak memory 199228 kb
Host smart-3706abff-6143-4b7b-bb09-77fb31db36ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029866743 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.1029866743
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.1864140308
Short name T539
Test name
Test status
Simulation time 197787847 ps
CPU time 1.3 seconds
Started Jan 10 12:30:48 PM PST 24
Finished Jan 10 12:31:35 PM PST 24
Peak memory 198996 kb
Host smart-e7368dae-e27d-4411-b645-f5927c4c0f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864140308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.1864140308
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.736108210
Short name T366
Test name
Test status
Simulation time 4708608538 ps
CPU time 20.4 seconds
Started Jan 10 12:28:50 PM PST 24
Finished Jan 10 12:29:27 PM PST 24
Peak memory 199452 kb
Host smart-4ef4e90a-7559-486a-9e43-647834fa9000
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736108210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.736108210
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.3600082809
Short name T511
Test name
Test status
Simulation time 113166129 ps
CPU time 1.35 seconds
Started Jan 10 12:28:16 PM PST 24
Finished Jan 10 12:28:31 PM PST 24
Peak memory 198888 kb
Host smart-87106b35-e784-4b6f-b4dd-dbb368094c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600082809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.3600082809
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.660157684
Short name T509
Test name
Test status
Simulation time 121491819 ps
CPU time 1.05 seconds
Started Jan 10 12:28:59 PM PST 24
Finished Jan 10 12:29:19 PM PST 24
Peak memory 197868 kb
Host smart-fd5917e7-4535-45e7-b4ba-b00b2b4f8109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660157684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.660157684
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.207644236
Short name T287
Test name
Test status
Simulation time 72533499 ps
CPU time 0.73 seconds
Started Jan 10 12:28:02 PM PST 24
Finished Jan 10 12:28:18 PM PST 24
Peak memory 198908 kb
Host smart-178051d4-b267-4200-9fdd-fd0f366cecde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207644236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.207644236
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.1193287078
Short name T359
Test name
Test status
Simulation time 2364136799 ps
CPU time 7.41 seconds
Started Jan 10 12:28:42 PM PST 24
Finished Jan 10 12:29:03 PM PST 24
Peak memory 217164 kb
Host smart-95a01899-4372-49de-b2b0-12289e7f6e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193287078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.1193287078
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.3622409806
Short name T524
Test name
Test status
Simulation time 246199396 ps
CPU time 1.01 seconds
Started Jan 10 12:28:48 PM PST 24
Finished Jan 10 12:29:04 PM PST 24
Peak memory 216380 kb
Host smart-774150b1-b8ed-4ae3-9a98-2b519fe15698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622409806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.3622409806
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.5235428
Short name T413
Test name
Test status
Simulation time 137868118 ps
CPU time 0.78 seconds
Started Jan 10 12:29:01 PM PST 24
Finished Jan 10 12:29:22 PM PST 24
Peak memory 198756 kb
Host smart-15b90396-e971-45c9-98a8-7e8ffa84e22d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5235428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.5235428
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.3580027789
Short name T498
Test name
Test status
Simulation time 1673952864 ps
CPU time 6.5 seconds
Started Jan 10 12:28:49 PM PST 24
Finished Jan 10 12:29:11 PM PST 24
Peak memory 199408 kb
Host smart-b1c9bf39-2bc4-4f5f-9d49-ccca5a2f507b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580027789 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.3580027789
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.2558381601
Short name T577
Test name
Test status
Simulation time 148407161 ps
CPU time 1.07 seconds
Started Jan 10 01:04:02 PM PST 24
Finished Jan 10 01:05:25 PM PST 24
Peak memory 199352 kb
Host smart-07d91f8d-c2a2-4de2-a307-f0d8033eefbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558381601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.2558381601
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.3622677012
Short name T396
Test name
Test status
Simulation time 228991558 ps
CPU time 1.38 seconds
Started Jan 10 12:28:50 PM PST 24
Finished Jan 10 12:29:08 PM PST 24
Peak memory 199408 kb
Host smart-4a1c4bb1-7be2-4c70-b1eb-5ceca4811253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622677012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.3622677012
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.3086390544
Short name T52
Test name
Test status
Simulation time 4998853481 ps
CPU time 16.52 seconds
Started Jan 10 12:30:54 PM PST 24
Finished Jan 10 12:31:57 PM PST 24
Peak memory 199236 kb
Host smart-5840459f-5d6a-4331-84cb-f7365ef70c34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086390544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.3086390544
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.611629469
Short name T159
Test name
Test status
Simulation time 114615766 ps
CPU time 1.39 seconds
Started Jan 10 12:28:50 PM PST 24
Finished Jan 10 12:29:08 PM PST 24
Peak memory 199272 kb
Host smart-10b0d3ce-470c-41dc-9922-156384e44fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611629469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.611629469
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.165815262
Short name T554
Test name
Test status
Simulation time 158907819 ps
CPU time 1.01 seconds
Started Jan 10 12:30:59 PM PST 24
Finished Jan 10 12:31:48 PM PST 24
Peak memory 199028 kb
Host smart-f95449fc-f340-4536-a0de-b26002cb201e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165815262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.165815262
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.2693307262
Short name T280
Test name
Test status
Simulation time 77327200 ps
CPU time 0.74 seconds
Started Jan 10 12:27:51 PM PST 24
Finished Jan 10 12:28:07 PM PST 24
Peak memory 199048 kb
Host smart-9d7d6f43-d2f7-4e4a-8191-34a5997f1a57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693307262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.2693307262
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.842293586
Short name T471
Test name
Test status
Simulation time 244499752 ps
CPU time 1.01 seconds
Started Jan 10 12:54:30 PM PST 24
Finished Jan 10 12:55:35 PM PST 24
Peak memory 216492 kb
Host smart-503fdf56-9560-4fc9-bf03-23b86a8230d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842293586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.842293586
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.2781743739
Short name T266
Test name
Test status
Simulation time 133820316 ps
CPU time 0.77 seconds
Started Jan 10 12:34:45 PM PST 24
Finished Jan 10 12:35:28 PM PST 24
Peak memory 199068 kb
Host smart-eb066ee5-e8f1-4eda-a3a8-aedd24b8e0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781743739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.2781743739
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.2035629578
Short name T324
Test name
Test status
Simulation time 1161667641 ps
CPU time 4.69 seconds
Started Jan 10 12:35:18 PM PST 24
Finished Jan 10 12:35:54 PM PST 24
Peak memory 199420 kb
Host smart-161a3009-1142-43be-b20f-55649f112916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035629578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.2035629578
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.1116925644
Short name T548
Test name
Test status
Simulation time 99700440 ps
CPU time 0.97 seconds
Started Jan 10 12:44:04 PM PST 24
Finished Jan 10 12:45:31 PM PST 24
Peak memory 199272 kb
Host smart-9fbd80f7-de8a-458d-91fa-308b46488e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116925644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.1116925644
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.3987377290
Short name T47
Test name
Test status
Simulation time 197159329 ps
CPU time 1.3 seconds
Started Jan 10 12:36:22 PM PST 24
Finished Jan 10 12:36:57 PM PST 24
Peak memory 199428 kb
Host smart-327b2692-a04f-46b5-b3b1-73289c4ce219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987377290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.3987377290
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.214428751
Short name T257
Test name
Test status
Simulation time 136576519 ps
CPU time 1.59 seconds
Started Jan 10 12:50:58 PM PST 24
Finished Jan 10 12:52:22 PM PST 24
Peak memory 199308 kb
Host smart-25996603-16ec-4015-b40d-5e57ad3dcb63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214428751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.214428751
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.3329866238
Short name T557
Test name
Test status
Simulation time 230624856 ps
CPU time 1.29 seconds
Started Jan 10 12:49:07 PM PST 24
Finished Jan 10 12:50:45 PM PST 24
Peak memory 199268 kb
Host smart-fce614e4-24ed-4e25-9c95-40ed77210e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329866238 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.3329866238
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.3748761943
Short name T384
Test name
Test status
Simulation time 84533624 ps
CPU time 0.74 seconds
Started Jan 10 12:48:26 PM PST 24
Finished Jan 10 12:50:01 PM PST 24
Peak memory 199124 kb
Host smart-9a9ddc59-7be9-4620-9634-7d062ab2c7ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748761943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.3748761943
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.3596376072
Short name T600
Test name
Test status
Simulation time 2373003293 ps
CPU time 9.42 seconds
Started Jan 10 12:28:00 PM PST 24
Finished Jan 10 12:28:24 PM PST 24
Peak memory 217204 kb
Host smart-5e31e185-ebd5-4f08-906f-6b19e564e341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596376072 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.3596376072
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.3654753285
Short name T373
Test name
Test status
Simulation time 244733207 ps
CPU time 1.07 seconds
Started Jan 10 12:49:51 PM PST 24
Finished Jan 10 12:51:23 PM PST 24
Peak memory 216412 kb
Host smart-d4c145e6-177e-413b-8f97-ad24956bd1e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654753285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.3654753285
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.607446805
Short name T398
Test name
Test status
Simulation time 80290987 ps
CPU time 0.7 seconds
Started Jan 10 12:52:40 PM PST 24
Finished Jan 10 12:53:51 PM PST 24
Peak memory 199124 kb
Host smart-8fc24f65-3141-456f-9d8c-086f5078d439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607446805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.607446805
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.722484812
Short name T500
Test name
Test status
Simulation time 1286462643 ps
CPU time 5.23 seconds
Started Jan 10 12:26:22 PM PST 24
Finished Jan 10 12:26:29 PM PST 24
Peak memory 199428 kb
Host smart-b4b83689-aaca-481a-8600-1c63742c7b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722484812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.722484812
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.3544876754
Short name T78
Test name
Test status
Simulation time 8350346623 ps
CPU time 12.9 seconds
Started Jan 10 12:32:03 PM PST 24
Finished Jan 10 12:33:02 PM PST 24
Peak memory 216696 kb
Host smart-0d421b3f-dbe6-4612-9d14-effb2b5179a2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544876754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.3544876754
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.1230589089
Short name T312
Test name
Test status
Simulation time 167163888 ps
CPU time 1.11 seconds
Started Jan 10 12:34:32 PM PST 24
Finished Jan 10 12:35:14 PM PST 24
Peak memory 199604 kb
Host smart-4ae30bd3-1ffc-4adf-83fd-13bffc0e2f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230589089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.1230589089
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.2120319277
Short name T135
Test name
Test status
Simulation time 192524131 ps
CPU time 1.25 seconds
Started Jan 10 12:29:19 PM PST 24
Finished Jan 10 12:29:44 PM PST 24
Peak memory 199144 kb
Host smart-166d9b69-cbb6-47ac-9dd4-8ae7b897f6ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120319277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.2120319277
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.2136173606
Short name T111
Test name
Test status
Simulation time 10431157540 ps
CPU time 36.99 seconds
Started Jan 10 12:29:25 PM PST 24
Finished Jan 10 12:30:28 PM PST 24
Peak memory 199196 kb
Host smart-b647a57a-2030-4d66-ae13-fb6ac8e1cf20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136173606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.2136173606
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.3595578915
Short name T164
Test name
Test status
Simulation time 110066229 ps
CPU time 1.36 seconds
Started Jan 10 01:14:49 PM PST 24
Finished Jan 10 01:15:12 PM PST 24
Peak memory 199408 kb
Host smart-cfc88546-2b03-49aa-bb54-a8e9785d81c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595578915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.3595578915
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.3015539867
Short name T245
Test name
Test status
Simulation time 92826602 ps
CPU time 0.85 seconds
Started Jan 10 12:36:12 PM PST 24
Finished Jan 10 12:36:43 PM PST 24
Peak memory 199320 kb
Host smart-1b89a7d5-185d-4aef-8cb3-4b1b126385b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015539867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.3015539867
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.2161533386
Short name T279
Test name
Test status
Simulation time 74453553 ps
CPU time 0.76 seconds
Started Jan 10 12:28:07 PM PST 24
Finished Jan 10 12:28:24 PM PST 24
Peak memory 199100 kb
Host smart-527dd084-1eb8-40e4-8390-8ed8e35956ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161533386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.2161533386
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.3037946859
Short name T39
Test name
Test status
Simulation time 2342583847 ps
CPU time 7.64 seconds
Started Jan 10 12:28:23 PM PST 24
Finished Jan 10 12:28:44 PM PST 24
Peak memory 217392 kb
Host smart-efa9b3db-57e3-4d5d-9f20-95f73e48b6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037946859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.3037946859
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.2070328182
Short name T145
Test name
Test status
Simulation time 246115413 ps
CPU time 0.99 seconds
Started Jan 10 12:27:38 PM PST 24
Finished Jan 10 12:27:48 PM PST 24
Peak memory 216372 kb
Host smart-ceba8b5a-394a-4af1-89c5-3aa0990b2062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070328182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.2070328182
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.3341435495
Short name T462
Test name
Test status
Simulation time 179237925 ps
CPU time 0.85 seconds
Started Jan 10 12:28:36 PM PST 24
Finished Jan 10 12:28:49 PM PST 24
Peak memory 199056 kb
Host smart-8c0dbf56-0b6a-4b6a-8d96-c3b566c184cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341435495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.3341435495
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.2760982915
Short name T456
Test name
Test status
Simulation time 1511466023 ps
CPU time 6.27 seconds
Started Jan 10 12:28:27 PM PST 24
Finished Jan 10 12:28:44 PM PST 24
Peak memory 199404 kb
Host smart-2b7247ab-765f-4cce-bc20-807b70f02a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760982915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.2760982915
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.2114247638
Short name T399
Test name
Test status
Simulation time 169454216 ps
CPU time 1.19 seconds
Started Jan 10 12:29:45 PM PST 24
Finished Jan 10 12:30:20 PM PST 24
Peak memory 198240 kb
Host smart-84a572ef-9078-486b-b60d-0b07e9bfb4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114247638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.2114247638
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.2749759426
Short name T430
Test name
Test status
Simulation time 253041868 ps
CPU time 1.48 seconds
Started Jan 10 12:30:24 PM PST 24
Finished Jan 10 12:31:07 PM PST 24
Peak memory 199132 kb
Host smart-541b6fae-71ca-4664-92ec-b36a50db59b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749759426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.2749759426
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.3516378148
Short name T486
Test name
Test status
Simulation time 4680976841 ps
CPU time 15.9 seconds
Started Jan 10 12:27:37 PM PST 24
Finished Jan 10 12:28:01 PM PST 24
Peak memory 199372 kb
Host smart-bf1708aa-b57a-4433-a75f-0d8f1cfa6124
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516378148 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.3516378148
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.857940291
Short name T474
Test name
Test status
Simulation time 126906393 ps
CPU time 1.51 seconds
Started Jan 10 12:30:00 PM PST 24
Finished Jan 10 12:30:44 PM PST 24
Peak memory 198372 kb
Host smart-7f358f9b-e7c0-4edd-9df6-9ecd0dbdc9c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857940291 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.857940291
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.2303908290
Short name T444
Test name
Test status
Simulation time 209108676 ps
CPU time 1.28 seconds
Started Jan 10 12:26:24 PM PST 24
Finished Jan 10 12:26:26 PM PST 24
Peak memory 199256 kb
Host smart-15bfe5db-cbf4-4c2c-bac1-12d359025170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303908290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.2303908290
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.2388370914
Short name T243
Test name
Test status
Simulation time 71605674 ps
CPU time 0.8 seconds
Started Jan 10 12:27:16 PM PST 24
Finished Jan 10 12:27:22 PM PST 24
Peak memory 199396 kb
Host smart-c51412d2-86fd-4dde-bac0-8b03a40801af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388370914 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.2388370914
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.1679056149
Short name T331
Test name
Test status
Simulation time 1221655814 ps
CPU time 5.22 seconds
Started Jan 10 12:31:54 PM PST 24
Finished Jan 10 12:32:45 PM PST 24
Peak memory 220968 kb
Host smart-86a775c4-f2a5-48c2-8294-9e06b8a30647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679056149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.1679056149
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.3535591063
Short name T390
Test name
Test status
Simulation time 243997722 ps
CPU time 1.14 seconds
Started Jan 10 12:28:21 PM PST 24
Finished Jan 10 12:28:35 PM PST 24
Peak memory 216300 kb
Host smart-2b2348d2-e95b-482d-b88b-d596d72c3164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535591063 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.3535591063
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.994620727
Short name T317
Test name
Test status
Simulation time 169564827 ps
CPU time 0.81 seconds
Started Jan 10 12:27:41 PM PST 24
Finished Jan 10 12:27:50 PM PST 24
Peak memory 199036 kb
Host smart-24798a28-0863-41fa-94ea-eaa96c3db440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994620727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.994620727
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.1846841971
Short name T129
Test name
Test status
Simulation time 1732331805 ps
CPU time 5.99 seconds
Started Jan 10 12:30:00 PM PST 24
Finished Jan 10 12:30:48 PM PST 24
Peak memory 199068 kb
Host smart-c2c1b217-165d-4bab-9ce0-cde4bb196745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846841971 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.1846841971
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.2867573994
Short name T149
Test name
Test status
Simulation time 182119085 ps
CPU time 1.11 seconds
Started Jan 10 12:30:48 PM PST 24
Finished Jan 10 12:31:34 PM PST 24
Peak memory 198932 kb
Host smart-baf1e392-3b7f-49f4-80a2-a64e41af42d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867573994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.2867573994
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.2386677754
Short name T332
Test name
Test status
Simulation time 241833970 ps
CPU time 1.48 seconds
Started Jan 10 12:27:51 PM PST 24
Finished Jan 10 12:28:08 PM PST 24
Peak memory 199404 kb
Host smart-56b2037c-2b9e-4466-80e1-30b57c41fb91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386677754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.2386677754
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.3425091000
Short name T459
Test name
Test status
Simulation time 273357649 ps
CPU time 1.97 seconds
Started Jan 10 12:35:52 PM PST 24
Finished Jan 10 12:36:18 PM PST 24
Peak memory 199224 kb
Host smart-b240a7c5-f4d6-40fc-b4a1-2c63b15c8464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425091000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.3425091000
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.356509937
Short name T86
Test name
Test status
Simulation time 99614730 ps
CPU time 0.84 seconds
Started Jan 10 12:27:38 PM PST 24
Finished Jan 10 12:27:48 PM PST 24
Peak memory 199172 kb
Host smart-f3a70192-dcf5-48e1-9208-77272157443e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356509937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.356509937
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.2733106103
Short name T594
Test name
Test status
Simulation time 73072775 ps
CPU time 0.75 seconds
Started Jan 10 12:47:04 PM PST 24
Finished Jan 10 12:48:26 PM PST 24
Peak memory 199096 kb
Host smart-bc396b46-56a1-4585-9a7f-648198d9ddd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733106103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.2733106103
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.2075873536
Short name T414
Test name
Test status
Simulation time 2360224633 ps
CPU time 7.95 seconds
Started Jan 10 12:32:17 PM PST 24
Finished Jan 10 12:33:05 PM PST 24
Peak memory 217080 kb
Host smart-67897272-dee6-4649-a8f1-455c2287a334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075873536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.2075873536
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.1371275917
Short name T543
Test name
Test status
Simulation time 243444625 ps
CPU time 1.11 seconds
Started Jan 10 12:30:47 PM PST 24
Finished Jan 10 12:31:33 PM PST 24
Peak memory 214520 kb
Host smart-4591b227-ea9f-4724-83ff-b6edbb12706f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371275917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.1371275917
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.1276767395
Short name T292
Test name
Test status
Simulation time 90411840 ps
CPU time 0.76 seconds
Started Jan 10 12:55:10 PM PST 24
Finished Jan 10 12:56:15 PM PST 24
Peak memory 199108 kb
Host smart-9bde255d-2090-4d3a-8dfa-bb278b096fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276767395 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.1276767395
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.3835369991
Short name T161
Test name
Test status
Simulation time 1081458851 ps
CPU time 4.72 seconds
Started Jan 10 12:25:57 PM PST 24
Finished Jan 10 12:26:04 PM PST 24
Peak memory 199708 kb
Host smart-333a2128-a578-449e-a1a1-d6618a36c804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835369991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.3835369991
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.1336509363
Short name T513
Test name
Test status
Simulation time 102314960 ps
CPU time 0.93 seconds
Started Jan 10 12:27:34 PM PST 24
Finished Jan 10 12:27:41 PM PST 24
Peak memory 199256 kb
Host smart-710534c7-9216-47ae-aa2b-ad0819176c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336509363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.1336509363
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.1051954048
Short name T341
Test name
Test status
Simulation time 114364586 ps
CPU time 1.13 seconds
Started Jan 10 12:28:11 PM PST 24
Finished Jan 10 12:28:26 PM PST 24
Peak memory 199368 kb
Host smart-6303ed0c-bdc2-4915-ad98-e76f86b16ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051954048 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.1051954048
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.3645881196
Short name T476
Test name
Test status
Simulation time 1846430402 ps
CPU time 9.1 seconds
Started Jan 10 12:30:48 PM PST 24
Finished Jan 10 12:31:42 PM PST 24
Peak memory 199012 kb
Host smart-1e09104a-f2ef-48e6-a176-7ad90798baff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645881196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.3645881196
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.2791049962
Short name T615
Test name
Test status
Simulation time 367817712 ps
CPU time 2.15 seconds
Started Jan 10 12:28:24 PM PST 24
Finished Jan 10 12:28:37 PM PST 24
Peak memory 199048 kb
Host smart-b8531c9b-4cf2-48bd-bfe7-01c52006929e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791049962 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.2791049962
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.399347356
Short name T295
Test name
Test status
Simulation time 167321848 ps
CPU time 1.09 seconds
Started Jan 10 12:25:55 PM PST 24
Finished Jan 10 12:25:57 PM PST 24
Peak memory 199284 kb
Host smart-82c7cd95-69d1-4e92-9061-088e52172b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399347356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.399347356
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.2230552979
Short name T2
Test name
Test status
Simulation time 70903992 ps
CPU time 0.74 seconds
Started Jan 10 12:27:34 PM PST 24
Finished Jan 10 12:27:41 PM PST 24
Peak memory 199080 kb
Host smart-bfaa9b1b-6609-4568-b094-ca3e6bf85417
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230552979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.2230552979
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.2381379315
Short name T574
Test name
Test status
Simulation time 1214090509 ps
CPU time 5.07 seconds
Started Jan 10 12:29:17 PM PST 24
Finished Jan 10 12:29:46 PM PST 24
Peak memory 220320 kb
Host smart-e85ac771-5f1d-4460-842c-00c4281f5cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381379315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.2381379315
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.2282882374
Short name T155
Test name
Test status
Simulation time 243742386 ps
CPU time 1.24 seconds
Started Jan 10 12:39:32 PM PST 24
Finished Jan 10 12:40:02 PM PST 24
Peak memory 216324 kb
Host smart-38cb4a65-350a-4c6b-82ec-551144a0655c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282882374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.2282882374
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.4254635475
Short name T15
Test name
Test status
Simulation time 102522034 ps
CPU time 0.77 seconds
Started Jan 10 12:25:58 PM PST 24
Finished Jan 10 12:26:04 PM PST 24
Peak memory 199052 kb
Host smart-d8e42de0-3005-4402-950b-76bed38976cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254635475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.4254635475
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.4003062037
Short name T85
Test name
Test status
Simulation time 1909715903 ps
CPU time 7.42 seconds
Started Jan 10 12:31:24 PM PST 24
Finished Jan 10 12:32:20 PM PST 24
Peak memory 198572 kb
Host smart-b4fabf07-2942-4106-a82e-597bafaeda5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003062037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.4003062037
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.6917664
Short name T499
Test name
Test status
Simulation time 147069167 ps
CPU time 1.1 seconds
Started Jan 10 12:40:18 PM PST 24
Finished Jan 10 12:41:06 PM PST 24
Peak memory 199324 kb
Host smart-2b98546e-1cca-486e-be0c-bb44fe1b0653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6917664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.6917664
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.1769714033
Short name T11
Test name
Test status
Simulation time 119314336 ps
CPU time 1.13 seconds
Started Jan 10 12:25:58 PM PST 24
Finished Jan 10 12:26:04 PM PST 24
Peak memory 199404 kb
Host smart-c8c0d7da-723c-4041-ac68-bf3fa02b6560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769714033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.1769714033
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.1637325262
Short name T468
Test name
Test status
Simulation time 5901531699 ps
CPU time 20.87 seconds
Started Jan 10 12:29:34 PM PST 24
Finished Jan 10 12:30:21 PM PST 24
Peak memory 199248 kb
Host smart-7e7b44d3-e383-45c4-8345-9710e1de5bc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637325262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.1637325262
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.1848282330
Short name T550
Test name
Test status
Simulation time 151022125 ps
CPU time 1.96 seconds
Started Jan 10 12:36:18 PM PST 24
Finished Jan 10 12:36:55 PM PST 24
Peak memory 199604 kb
Host smart-ac80f180-e73a-4117-b0ad-b35a39e34856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848282330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.1848282330
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.3400610186
Short name T60
Test name
Test status
Simulation time 119360929 ps
CPU time 0.89 seconds
Started Jan 10 12:28:22 PM PST 24
Finished Jan 10 12:28:35 PM PST 24
Peak memory 199112 kb
Host smart-3e35e5e7-cadb-4844-a5d3-c8a76658c875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400610186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.3400610186
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.4229972480
Short name T402
Test name
Test status
Simulation time 83358387 ps
CPU time 0.8 seconds
Started Jan 10 12:26:39 PM PST 24
Finished Jan 10 12:26:45 PM PST 24
Peak memory 199104 kb
Host smart-87258fd2-a9c9-4e3f-bf2b-26309086d8e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229972480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.4229972480
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.950659405
Short name T53
Test name
Test status
Simulation time 2166182885 ps
CPU time 7.07 seconds
Started Jan 10 12:29:33 PM PST 24
Finished Jan 10 12:30:06 PM PST 24
Peak memory 221056 kb
Host smart-d72fc762-7404-4f6d-a1dc-608110ab1cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950659405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.950659405
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.1322990960
Short name T244
Test name
Test status
Simulation time 244530578 ps
CPU time 1.07 seconds
Started Jan 10 12:27:58 PM PST 24
Finished Jan 10 12:28:12 PM PST 24
Peak memory 216316 kb
Host smart-a796e4e7-43b6-47fe-b391-c5331c305726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322990960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.1322990960
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.1094066974
Short name T547
Test name
Test status
Simulation time 188953457 ps
CPU time 0.83 seconds
Started Jan 10 12:50:06 PM PST 24
Finished Jan 10 12:51:30 PM PST 24
Peak memory 199084 kb
Host smart-16bd3398-3c0f-4129-8a40-663f340901b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094066974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.1094066974
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.4038346803
Short name T276
Test name
Test status
Simulation time 1072457823 ps
CPU time 4.93 seconds
Started Jan 10 12:47:32 PM PST 24
Finished Jan 10 12:48:56 PM PST 24
Peak memory 199424 kb
Host smart-a928036d-a100-4d80-83c6-c5cbccd18e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038346803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.4038346803
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.812767821
Short name T142
Test name
Test status
Simulation time 111196712 ps
CPU time 0.96 seconds
Started Jan 10 12:29:34 PM PST 24
Finished Jan 10 12:30:02 PM PST 24
Peak memory 199092 kb
Host smart-09eb0ef4-6027-4e74-8244-65e50c3259a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812767821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.812767821
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.2162513525
Short name T584
Test name
Test status
Simulation time 118074550 ps
CPU time 1.1 seconds
Started Jan 10 12:36:05 PM PST 24
Finished Jan 10 12:36:33 PM PST 24
Peak memory 199492 kb
Host smart-0e1960d0-c3f0-4589-9960-b5d91896edcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162513525 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.2162513525
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.3491776910
Short name T487
Test name
Test status
Simulation time 5054154401 ps
CPU time 15.8 seconds
Started Jan 10 12:29:31 PM PST 24
Finished Jan 10 12:30:12 PM PST 24
Peak memory 199184 kb
Host smart-b772d811-2458-45e1-8054-d2d6dbec4676
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491776910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.3491776910
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.4251922443
Short name T302
Test name
Test status
Simulation time 368407696 ps
CPU time 1.92 seconds
Started Jan 10 12:39:26 PM PST 24
Finished Jan 10 12:39:58 PM PST 24
Peak memory 199312 kb
Host smart-0404d310-44a3-43bc-aec7-439d385b50a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251922443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.4251922443
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.691028060
Short name T610
Test name
Test status
Simulation time 216734305 ps
CPU time 1.24 seconds
Started Jan 10 12:40:36 PM PST 24
Finished Jan 10 12:41:20 PM PST 24
Peak memory 199284 kb
Host smart-f7a922f5-e331-4ffc-a48e-cd0fc38cdeca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691028060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.691028060
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.3922851121
Short name T465
Test name
Test status
Simulation time 71240903 ps
CPU time 0.82 seconds
Started Jan 10 12:31:22 PM PST 24
Finished Jan 10 12:32:09 PM PST 24
Peak memory 198244 kb
Host smart-78065a6d-abd3-477a-8959-09e42b8498cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922851121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.3922851121
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.1988721842
Short name T419
Test name
Test status
Simulation time 2379291763 ps
CPU time 8.94 seconds
Started Jan 10 12:28:04 PM PST 24
Finished Jan 10 12:28:28 PM PST 24
Peak memory 216076 kb
Host smart-1b75ca69-c5d9-4265-b9e2-9105036cdbd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988721842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.1988721842
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.3139648542
Short name T576
Test name
Test status
Simulation time 244192872 ps
CPU time 1.07 seconds
Started Jan 10 12:28:55 PM PST 24
Finished Jan 10 12:29:15 PM PST 24
Peak memory 215436 kb
Host smart-8c30ef19-0e1c-48aa-bed2-a541f40e2f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139648542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.3139648542
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.2337867392
Short name T14
Test name
Test status
Simulation time 244000412 ps
CPU time 0.99 seconds
Started Jan 10 12:27:21 PM PST 24
Finished Jan 10 12:27:28 PM PST 24
Peak memory 199024 kb
Host smart-d349aa6d-bb0b-45d2-a922-1f6fc1eef95a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337867392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.2337867392
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.3751818333
Short name T530
Test name
Test status
Simulation time 1846136021 ps
CPU time 5.87 seconds
Started Jan 10 12:29:31 PM PST 24
Finished Jan 10 12:30:02 PM PST 24
Peak memory 199112 kb
Host smart-5088fd43-4d98-4db7-819d-3cf6b582efca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751818333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.3751818333
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.1991666845
Short name T306
Test name
Test status
Simulation time 97701603 ps
CPU time 0.99 seconds
Started Jan 10 12:29:52 PM PST 24
Finished Jan 10 12:30:29 PM PST 24
Peak memory 198196 kb
Host smart-ccd67587-aed5-4625-b6fc-c9371d12aebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991666845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.1991666845
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.1576468851
Short name T506
Test name
Test status
Simulation time 253405316 ps
CPU time 1.49 seconds
Started Jan 10 12:29:52 PM PST 24
Finished Jan 10 12:30:30 PM PST 24
Peak memory 198988 kb
Host smart-aff8e566-d8dd-4d76-a00e-20367ee04079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576468851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.1576468851
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.2133476473
Short name T248
Test name
Test status
Simulation time 4866610876 ps
CPU time 21.49 seconds
Started Jan 10 12:28:07 PM PST 24
Finished Jan 10 12:28:45 PM PST 24
Peak memory 199456 kb
Host smart-1cb2421f-d581-4502-ad98-44e14527397b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133476473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.2133476473
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.1964076773
Short name T360
Test name
Test status
Simulation time 380742328 ps
CPU time 1.95 seconds
Started Jan 10 12:27:30 PM PST 24
Finished Jan 10 12:27:37 PM PST 24
Peak memory 199208 kb
Host smart-116b08ee-7db7-4b03-93e9-821545239e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964076773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.1964076773
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.4087289363
Short name T450
Test name
Test status
Simulation time 143451344 ps
CPU time 1.15 seconds
Started Jan 10 12:27:13 PM PST 24
Finished Jan 10 12:27:19 PM PST 24
Peak memory 199256 kb
Host smart-53485816-945a-4180-8a52-ac1d03c0b5b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087289363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.4087289363
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.3304834614
Short name T162
Test name
Test status
Simulation time 65162721 ps
CPU time 0.68 seconds
Started Jan 10 12:31:58 PM PST 24
Finished Jan 10 12:32:45 PM PST 24
Peak memory 198892 kb
Host smart-8c39cbd6-83fd-49fb-9d10-06bb55b9df5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304834614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.3304834614
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.2295238500
Short name T593
Test name
Test status
Simulation time 2364516561 ps
CPU time 7.54 seconds
Started Jan 10 12:31:59 PM PST 24
Finished Jan 10 12:32:53 PM PST 24
Peak memory 217836 kb
Host smart-ccb198d8-d391-4c80-b1c1-c6c5225d45c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295238500 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.2295238500
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.647764991
Short name T580
Test name
Test status
Simulation time 243499094 ps
CPU time 1.09 seconds
Started Jan 10 12:26:13 PM PST 24
Finished Jan 10 12:26:19 PM PST 24
Peak memory 216280 kb
Host smart-89c05d7d-1df4-41b0-8c5c-847b87bcec98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647764991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.647764991
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.3729770544
Short name T301
Test name
Test status
Simulation time 131372542 ps
CPU time 0.77 seconds
Started Jan 10 12:27:52 PM PST 24
Finished Jan 10 12:28:07 PM PST 24
Peak memory 199016 kb
Host smart-9f3002bd-dafa-4106-8be3-0785e0bf8824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729770544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.3729770544
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.2646860000
Short name T293
Test name
Test status
Simulation time 1726584476 ps
CPU time 6.54 seconds
Started Jan 10 12:27:50 PM PST 24
Finished Jan 10 12:28:12 PM PST 24
Peak memory 199444 kb
Host smart-f4cb002a-1b34-46e0-a068-db65460e8903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646860000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.2646860000
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.1814003083
Short name T479
Test name
Test status
Simulation time 174486537 ps
CPU time 1.16 seconds
Started Jan 10 12:27:50 PM PST 24
Finished Jan 10 12:28:07 PM PST 24
Peak memory 199300 kb
Host smart-75554e99-eccf-4da1-9145-cf6b2bc8835f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814003083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.1814003083
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.2241695792
Short name T564
Test name
Test status
Simulation time 232608230 ps
CPU time 1.36 seconds
Started Jan 10 12:28:56 PM PST 24
Finished Jan 10 12:29:16 PM PST 24
Peak memory 199128 kb
Host smart-60fb4d5f-b54e-4058-bcb9-8508baea971d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241695792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.2241695792
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.1147534112
Short name T590
Test name
Test status
Simulation time 3304591683 ps
CPU time 13.21 seconds
Started Jan 10 12:26:16 PM PST 24
Finished Jan 10 12:26:32 PM PST 24
Peak memory 199484 kb
Host smart-396faff6-6509-4453-96fa-ebebc404759b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147534112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.1147534112
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.3482071199
Short name T502
Test name
Test status
Simulation time 121230301 ps
CPU time 1.48 seconds
Started Jan 10 12:32:03 PM PST 24
Finished Jan 10 12:32:50 PM PST 24
Peak memory 198980 kb
Host smart-9c64e6a0-62a4-466b-b6b1-5bcc5487ad6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482071199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.3482071199
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.1798126065
Short name T139
Test name
Test status
Simulation time 281533300 ps
CPU time 1.5 seconds
Started Jan 10 12:26:37 PM PST 24
Finished Jan 10 12:26:44 PM PST 24
Peak memory 199428 kb
Host smart-2152efbd-9800-45a4-afe5-68b6f65d177c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798126065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.1798126065
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.3474834283
Short name T303
Test name
Test status
Simulation time 77203852 ps
CPU time 0.76 seconds
Started Jan 10 12:29:02 PM PST 24
Finished Jan 10 12:29:22 PM PST 24
Peak memory 199096 kb
Host smart-cff29574-fbdb-4b08-a144-30c64273558c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474834283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.3474834283
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.3419201415
Short name T613
Test name
Test status
Simulation time 1887757273 ps
CPU time 6.28 seconds
Started Jan 10 12:31:43 PM PST 24
Finished Jan 10 12:32:38 PM PST 24
Peak memory 215780 kb
Host smart-8af9ed1c-cbd7-4356-b3b5-248ef783ceff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419201415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.3419201415
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.4066597667
Short name T451
Test name
Test status
Simulation time 244166268 ps
CPU time 1.17 seconds
Started Jan 10 12:31:33 PM PST 24
Finished Jan 10 12:32:24 PM PST 24
Peak memory 215520 kb
Host smart-e422285d-617e-45f3-baf6-a239e478a72c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066597667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.4066597667
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.645282151
Short name T521
Test name
Test status
Simulation time 170655103 ps
CPU time 0.78 seconds
Started Jan 10 12:28:19 PM PST 24
Finished Jan 10 12:28:33 PM PST 24
Peak memory 199008 kb
Host smart-7b55d335-8b61-44e8-8ffc-1406de2e62de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645282151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.645282151
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.1683493751
Short name T378
Test name
Test status
Simulation time 1507874176 ps
CPU time 5.85 seconds
Started Jan 10 12:28:21 PM PST 24
Finished Jan 10 12:28:39 PM PST 24
Peak memory 199360 kb
Host smart-52b3accf-08e7-4d7f-8146-3396ebef27f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683493751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.1683493751
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.980017105
Short name T320
Test name
Test status
Simulation time 153399225 ps
CPU time 1.06 seconds
Started Jan 10 12:32:03 PM PST 24
Finished Jan 10 12:32:50 PM PST 24
Peak memory 199052 kb
Host smart-3fe0c02e-ff69-4572-a430-0babea623536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980017105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.980017105
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.1844180116
Short name T364
Test name
Test status
Simulation time 191072459 ps
CPU time 1.26 seconds
Started Jan 10 12:31:53 PM PST 24
Finished Jan 10 12:32:41 PM PST 24
Peak memory 199208 kb
Host smart-dbd11fe1-a631-4b54-abc0-592c56bbd804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844180116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.1844180116
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.1178304010
Short name T469
Test name
Test status
Simulation time 3628727008 ps
CPU time 16.86 seconds
Started Jan 10 12:27:14 PM PST 24
Finished Jan 10 12:27:35 PM PST 24
Peak memory 199472 kb
Host smart-dd28eeff-8348-49e8-b8fb-9620358d6a37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178304010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.1178304010
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.2969588494
Short name T291
Test name
Test status
Simulation time 326035120 ps
CPU time 1.81 seconds
Started Jan 10 12:29:02 PM PST 24
Finished Jan 10 12:29:23 PM PST 24
Peak memory 199228 kb
Host smart-c33b974c-6368-4416-a584-cf2437a1628c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969588494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.2969588494
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.942308750
Short name T618
Test name
Test status
Simulation time 146705273 ps
CPU time 1.17 seconds
Started Jan 10 12:27:29 PM PST 24
Finished Jan 10 12:27:35 PM PST 24
Peak memory 199384 kb
Host smart-ddd6bdfd-4738-4472-840f-6239bc77c4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942308750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.942308750
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.27078788
Short name T607
Test name
Test status
Simulation time 64775887 ps
CPU time 0.74 seconds
Started Jan 10 12:27:08 PM PST 24
Finished Jan 10 12:27:15 PM PST 24
Peak memory 199188 kb
Host smart-4c043622-1201-430b-8e80-d2334b355b08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27078788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.27078788
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.1309660717
Short name T27
Test name
Test status
Simulation time 1898501801 ps
CPU time 6.95 seconds
Started Jan 10 12:28:00 PM PST 24
Finished Jan 10 12:28:21 PM PST 24
Peak memory 216688 kb
Host smart-d24ed578-af73-48ea-b91d-df8202c69f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309660717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.1309660717
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.998690746
Short name T563
Test name
Test status
Simulation time 244081893 ps
CPU time 1.11 seconds
Started Jan 10 12:27:27 PM PST 24
Finished Jan 10 12:27:33 PM PST 24
Peak memory 216468 kb
Host smart-89662712-8aea-45e6-8099-8c7619bedf78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998690746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.998690746
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.3942983891
Short name T354
Test name
Test status
Simulation time 118939315 ps
CPU time 0.73 seconds
Started Jan 10 12:28:20 PM PST 24
Finished Jan 10 12:28:33 PM PST 24
Peak memory 199004 kb
Host smart-d223c886-3643-43d4-a938-19d8e6eb04af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942983891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.3942983891
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.1061024518
Short name T408
Test name
Test status
Simulation time 755659228 ps
CPU time 3.62 seconds
Started Jan 10 12:31:03 PM PST 24
Finished Jan 10 12:31:53 PM PST 24
Peak memory 198120 kb
Host smart-a3691eab-d74e-438e-b4a6-5833797c8de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061024518 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.1061024518
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.2763788134
Short name T10
Test name
Test status
Simulation time 106535848 ps
CPU time 0.93 seconds
Started Jan 10 12:31:26 PM PST 24
Finished Jan 10 12:32:15 PM PST 24
Peak memory 199000 kb
Host smart-e5616bd1-ad23-42e0-bcf4-79f29d57f3bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763788134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.2763788134
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.4228090589
Short name T612
Test name
Test status
Simulation time 120829383 ps
CPU time 1.06 seconds
Started Jan 10 12:30:02 PM PST 24
Finished Jan 10 12:30:45 PM PST 24
Peak memory 199120 kb
Host smart-2d330eff-c1d6-495a-a028-45f744a79cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228090589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.4228090589
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.560331418
Short name T372
Test name
Test status
Simulation time 7185044890 ps
CPU time 28.58 seconds
Started Jan 10 12:27:18 PM PST 24
Finished Jan 10 12:27:52 PM PST 24
Peak memory 199448 kb
Host smart-83b35088-6f1b-4533-b7ea-839197dd4cef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560331418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.560331418
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.256980863
Short name T274
Test name
Test status
Simulation time 386983115 ps
CPU time 2.13 seconds
Started Jan 10 12:31:56 PM PST 24
Finished Jan 10 12:32:44 PM PST 24
Peak memory 198380 kb
Host smart-22781be5-b2e2-4541-914d-301ede6e4694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256980863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.256980863
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.1754391983
Short name T601
Test name
Test status
Simulation time 211289341 ps
CPU time 1.33 seconds
Started Jan 10 12:31:03 PM PST 24
Finished Jan 10 12:31:51 PM PST 24
Peak memory 198028 kb
Host smart-e64645fc-4b98-428c-898a-4a1feb7de0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754391983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.1754391983
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.1496366615
Short name T518
Test name
Test status
Simulation time 63742604 ps
CPU time 0.67 seconds
Started Jan 10 12:30:29 PM PST 24
Finished Jan 10 12:31:11 PM PST 24
Peak memory 198892 kb
Host smart-f705a34e-6cc0-47ce-ae5c-56c325eae57a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496366615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.1496366615
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.2594256373
Short name T336
Test name
Test status
Simulation time 1218618036 ps
CPU time 5.06 seconds
Started Jan 10 12:30:01 PM PST 24
Finished Jan 10 12:30:48 PM PST 24
Peak memory 214988 kb
Host smart-780b34b1-a914-420e-b057-3a8dcd1a4abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594256373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.2594256373
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.3603996041
Short name T551
Test name
Test status
Simulation time 250071251 ps
CPU time 1.05 seconds
Started Jan 10 12:27:38 PM PST 24
Finished Jan 10 12:27:47 PM PST 24
Peak memory 216404 kb
Host smart-20505a83-8e51-4f5f-9b5f-e205e8c3a282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603996041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.3603996041
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.1621706161
Short name T251
Test name
Test status
Simulation time 224951871 ps
CPU time 0.91 seconds
Started Jan 10 12:27:46 PM PST 24
Finished Jan 10 12:27:59 PM PST 24
Peak memory 199076 kb
Host smart-64c24906-cc20-44a2-a13b-70643d27f207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621706161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.1621706161
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.4276163450
Short name T105
Test name
Test status
Simulation time 784362505 ps
CPU time 3.77 seconds
Started Jan 10 12:31:03 PM PST 24
Finished Jan 10 12:31:54 PM PST 24
Peak memory 199140 kb
Host smart-2f6a564f-96d4-4dea-956c-1822f7b93151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276163450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.4276163450
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.3774332790
Short name T544
Test name
Test status
Simulation time 154952820 ps
CPU time 1.1 seconds
Started Jan 10 12:28:01 PM PST 24
Finished Jan 10 12:28:18 PM PST 24
Peak memory 199240 kb
Host smart-868c62d0-185b-4d3b-8c68-d33a80dd687f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774332790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.3774332790
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.1129993792
Short name T348
Test name
Test status
Simulation time 111446093 ps
CPU time 1.06 seconds
Started Jan 10 12:31:23 PM PST 24
Finished Jan 10 12:32:12 PM PST 24
Peak memory 199148 kb
Host smart-8c9fd6d1-8509-4ca3-b5bb-5a08397627ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129993792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.1129993792
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.2197150084
Short name T356
Test name
Test status
Simulation time 6188754525 ps
CPU time 25.46 seconds
Started Jan 10 12:30:25 PM PST 24
Finished Jan 10 12:31:32 PM PST 24
Peak memory 199252 kb
Host smart-b061f9a8-4c13-4f8a-a244-79d01a7e97c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197150084 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.2197150084
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.108104882
Short name T457
Test name
Test status
Simulation time 321780906 ps
CPU time 2.29 seconds
Started Jan 10 12:27:18 PM PST 24
Finished Jan 10 12:27:26 PM PST 24
Peak memory 199208 kb
Host smart-40892860-517f-45f6-831a-716f9910b212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108104882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.108104882
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.3461674915
Short name T345
Test name
Test status
Simulation time 154244425 ps
CPU time 1.02 seconds
Started Jan 10 12:30:27 PM PST 24
Finished Jan 10 12:31:09 PM PST 24
Peak memory 198876 kb
Host smart-056f4dd0-4995-408d-941f-0f60479f7bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461674915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.3461674915
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.2358387720
Short name T5
Test name
Test status
Simulation time 67748350 ps
CPU time 0.74 seconds
Started Jan 10 12:49:06 PM PST 24
Finished Jan 10 12:50:38 PM PST 24
Peak memory 199088 kb
Host smart-35049930-18ff-43ed-8354-d316f35b1003
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358387720 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.2358387720
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.855289617
Short name T617
Test name
Test status
Simulation time 2163010310 ps
CPU time 7.51 seconds
Started Jan 10 12:54:15 PM PST 24
Finished Jan 10 12:55:29 PM PST 24
Peak memory 220948 kb
Host smart-065f6845-b393-4b7b-93dc-fe465316bcf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855289617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.855289617
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.3873397131
Short name T297
Test name
Test status
Simulation time 245111175 ps
CPU time 1.1 seconds
Started Jan 10 01:17:21 PM PST 24
Finished Jan 10 01:18:00 PM PST 24
Peak memory 216456 kb
Host smart-1c41a9ae-4ee3-4f34-a9e1-a44f37611603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873397131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.3873397131
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.215875476
Short name T599
Test name
Test status
Simulation time 212323541 ps
CPU time 0.92 seconds
Started Jan 10 12:31:41 PM PST 24
Finished Jan 10 12:32:32 PM PST 24
Peak memory 198776 kb
Host smart-24a7ddad-4eb8-4fec-b805-6d01f1c4531f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215875476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.215875476
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.2684038331
Short name T412
Test name
Test status
Simulation time 1488625919 ps
CPU time 5.62 seconds
Started Jan 10 12:30:03 PM PST 24
Finished Jan 10 12:30:50 PM PST 24
Peak memory 197568 kb
Host smart-82f6028c-fc41-4c2e-acf6-93e0042e51d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684038331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.2684038331
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.2409541419
Short name T346
Test name
Test status
Simulation time 142776987 ps
CPU time 1.02 seconds
Started Jan 10 12:31:51 PM PST 24
Finished Jan 10 12:32:39 PM PST 24
Peak memory 198992 kb
Host smart-3f8df9a2-0e60-467a-8592-000746f6af0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409541419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.2409541419
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.3731973029
Short name T43
Test name
Test status
Simulation time 244705000 ps
CPU time 1.4 seconds
Started Jan 10 01:08:06 PM PST 24
Finished Jan 10 01:09:32 PM PST 24
Peak memory 199500 kb
Host smart-feb66055-5f65-4cff-9bf6-fa767ea5b901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731973029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.3731973029
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.2820673746
Short name T431
Test name
Test status
Simulation time 1404038727 ps
CPU time 5.84 seconds
Started Jan 10 12:31:54 PM PST 24
Finished Jan 10 12:32:46 PM PST 24
Peak memory 199132 kb
Host smart-c1fbb60c-c0ac-449d-a176-dbe146107ed7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820673746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.2820673746
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.2190328565
Short name T58
Test name
Test status
Simulation time 153282762 ps
CPU time 1.86 seconds
Started Jan 10 12:31:48 PM PST 24
Finished Jan 10 12:32:37 PM PST 24
Peak memory 199004 kb
Host smart-1a8a1a2d-d02a-4d9a-88dc-c7728f5b865e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190328565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.2190328565
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.1954592902
Short name T140
Test name
Test status
Simulation time 200148666 ps
CPU time 1.23 seconds
Started Jan 10 12:45:48 PM PST 24
Finished Jan 10 12:47:09 PM PST 24
Peak memory 199272 kb
Host smart-b7990dda-4be4-455b-8710-d114bcb69be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954592902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.1954592902
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.3441262592
Short name T379
Test name
Test status
Simulation time 68658499 ps
CPU time 0.71 seconds
Started Jan 10 12:27:39 PM PST 24
Finished Jan 10 12:27:48 PM PST 24
Peak memory 199044 kb
Host smart-f324aaaf-16c3-45ef-9daa-6a2dcea4b69e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441262592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.3441262592
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.2000505634
Short name T26
Test name
Test status
Simulation time 1230780807 ps
CPU time 5.2 seconds
Started Jan 10 12:30:06 PM PST 24
Finished Jan 10 12:30:52 PM PST 24
Peak memory 220056 kb
Host smart-9246b5d2-cb9f-43be-8c6f-e7c58e591a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000505634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.2000505634
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.463546554
Short name T569
Test name
Test status
Simulation time 244074448 ps
CPU time 1.07 seconds
Started Jan 10 12:30:28 PM PST 24
Finished Jan 10 12:31:11 PM PST 24
Peak memory 216248 kb
Host smart-923ccd59-7fcd-4a28-b35b-4021c4c879eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463546554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.463546554
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.2528585163
Short name T16
Test name
Test status
Simulation time 136819521 ps
CPU time 0.82 seconds
Started Jan 10 12:27:12 PM PST 24
Finished Jan 10 12:27:18 PM PST 24
Peak memory 199396 kb
Host smart-c3c55ea0-0380-4d60-8395-d0796d6b6dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528585163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.2528585163
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.853315061
Short name T568
Test name
Test status
Simulation time 1911841004 ps
CPU time 7.2 seconds
Started Jan 10 12:27:37 PM PST 24
Finished Jan 10 12:27:51 PM PST 24
Peak memory 199432 kb
Host smart-272ef810-06ee-4c17-a959-09b914713129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853315061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.853315061
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.1598482078
Short name T322
Test name
Test status
Simulation time 161032999 ps
CPU time 1.15 seconds
Started Jan 10 12:30:55 PM PST 24
Finished Jan 10 12:31:42 PM PST 24
Peak memory 198144 kb
Host smart-ec2416af-d15d-4fcf-b805-212ddee23d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598482078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.1598482078
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.2492651841
Short name T350
Test name
Test status
Simulation time 188789036 ps
CPU time 1.27 seconds
Started Jan 10 12:28:07 PM PST 24
Finished Jan 10 12:28:24 PM PST 24
Peak memory 199388 kb
Host smart-e65e3df9-0240-4bbb-938e-bfbdaa7aed63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492651841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.2492651841
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.1406166396
Short name T443
Test name
Test status
Simulation time 6412324493 ps
CPU time 27.46 seconds
Started Jan 10 12:27:18 PM PST 24
Finished Jan 10 12:27:51 PM PST 24
Peak memory 199440 kb
Host smart-faabaa24-a5a2-4f46-b40d-ee4568d0c683
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406166396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.1406166396
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.2256118849
Short name T516
Test name
Test status
Simulation time 267998886 ps
CPU time 1.3 seconds
Started Jan 10 12:30:28 PM PST 24
Finished Jan 10 12:31:10 PM PST 24
Peak memory 199004 kb
Host smart-13a1c764-5b51-460a-a98c-fadf0bf4e537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256118849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.2256118849
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.908659625
Short name T46
Test name
Test status
Simulation time 65981832 ps
CPU time 0.7 seconds
Started Jan 10 12:30:15 PM PST 24
Finished Jan 10 12:30:55 PM PST 24
Peak memory 198824 kb
Host smart-f42f8653-93b5-4ae5-8dc2-80d1de00dc33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908659625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.908659625
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.789318593
Short name T416
Test name
Test status
Simulation time 2348515628 ps
CPU time 7.76 seconds
Started Jan 10 12:30:43 PM PST 24
Finished Jan 10 12:31:34 PM PST 24
Peak memory 220992 kb
Host smart-bb39689f-9ca7-41f0-8397-42ebad2c1fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789318593 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.789318593
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.4100690072
Short name T497
Test name
Test status
Simulation time 244820621 ps
CPU time 0.99 seconds
Started Jan 10 12:30:46 PM PST 24
Finished Jan 10 12:31:31 PM PST 24
Peak memory 216224 kb
Host smart-dd2b25e5-0cd2-4b24-811b-4ae834c96149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100690072 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.4100690072
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.1091390334
Short name T310
Test name
Test status
Simulation time 107749127 ps
CPU time 0.72 seconds
Started Jan 10 12:30:26 PM PST 24
Finished Jan 10 12:31:08 PM PST 24
Peak memory 198616 kb
Host smart-06332148-9383-4cec-b94b-fb576e2dc6f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091390334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.1091390334
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.878421753
Short name T381
Test name
Test status
Simulation time 676985493 ps
CPU time 3.38 seconds
Started Jan 10 12:30:35 PM PST 24
Finished Jan 10 12:31:20 PM PST 24
Peak memory 199244 kb
Host smart-15aef629-d9fe-42d6-95da-d9b6f5d15d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878421753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.878421753
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.3157075059
Short name T299
Test name
Test status
Simulation time 163530153 ps
CPU time 1.12 seconds
Started Jan 10 12:30:29 PM PST 24
Finished Jan 10 12:31:12 PM PST 24
Peak memory 197920 kb
Host smart-8f171678-f88d-4f87-893a-789c567b4dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157075059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.3157075059
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.2316996334
Short name T329
Test name
Test status
Simulation time 112523000 ps
CPU time 1.18 seconds
Started Jan 10 12:30:26 PM PST 24
Finished Jan 10 12:31:08 PM PST 24
Peak memory 197892 kb
Host smart-35fad907-9e42-4d26-8be9-b6fff8358e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316996334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.2316996334
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.2641002557
Short name T510
Test name
Test status
Simulation time 6844716552 ps
CPU time 26.48 seconds
Started Jan 10 12:30:27 PM PST 24
Finished Jan 10 12:31:35 PM PST 24
Peak memory 199108 kb
Host smart-b5c93e60-27a9-4349-8c48-b1b4c0533b56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641002557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.2641002557
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.861907763
Short name T495
Test name
Test status
Simulation time 311572404 ps
CPU time 2.04 seconds
Started Jan 10 12:28:19 PM PST 24
Finished Jan 10 12:28:34 PM PST 24
Peak memory 199276 kb
Host smart-b0ebf0fe-58e8-41ef-bb41-ea61fa6d0a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861907763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.861907763
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.1948848085
Short name T421
Test name
Test status
Simulation time 100031425 ps
CPU time 0.85 seconds
Started Jan 10 12:30:26 PM PST 24
Finished Jan 10 12:31:08 PM PST 24
Peak memory 198832 kb
Host smart-440e1d5f-0766-473c-909c-d0d9aef1211d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948848085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.1948848085
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.449030443
Short name T565
Test name
Test status
Simulation time 74399665 ps
CPU time 0.69 seconds
Started Jan 10 12:30:32 PM PST 24
Finished Jan 10 12:31:15 PM PST 24
Peak memory 198828 kb
Host smart-e03a3ca5-d316-48c7-9976-ba019095d5ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449030443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.449030443
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.2617286799
Short name T30
Test name
Test status
Simulation time 1880882319 ps
CPU time 6.87 seconds
Started Jan 10 12:28:06 PM PST 24
Finished Jan 10 12:28:28 PM PST 24
Peak memory 220716 kb
Host smart-127cb610-8293-4884-9e16-d5c02e4a6071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617286799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.2617286799
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.828531203
Short name T150
Test name
Test status
Simulation time 245702717 ps
CPU time 1.14 seconds
Started Jan 10 12:30:47 PM PST 24
Finished Jan 10 12:31:33 PM PST 24
Peak memory 214384 kb
Host smart-6ecc67dd-e0de-4ee1-aa99-c9377cde13c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828531203 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.828531203
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.3757832750
Short name T21
Test name
Test status
Simulation time 201325941 ps
CPU time 0.89 seconds
Started Jan 10 12:30:47 PM PST 24
Finished Jan 10 12:31:33 PM PST 24
Peak memory 197188 kb
Host smart-8de3e8cd-f5f3-4c7b-904c-f9fde1661983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757832750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.3757832750
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.3267438950
Short name T482
Test name
Test status
Simulation time 1807505711 ps
CPU time 6.52 seconds
Started Jan 10 12:30:48 PM PST 24
Finished Jan 10 12:31:40 PM PST 24
Peak memory 199104 kb
Host smart-17838970-1666-4444-a62e-45e824d4101a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267438950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.3267438950
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.197716582
Short name T83
Test name
Test status
Simulation time 160197679 ps
CPU time 1.09 seconds
Started Jan 10 12:29:18 PM PST 24
Finished Jan 10 12:29:44 PM PST 24
Peak memory 198100 kb
Host smart-4192341d-9fc4-41b8-852a-df01ff94cac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197716582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.197716582
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.2570103589
Short name T59
Test name
Test status
Simulation time 188030986 ps
CPU time 1.26 seconds
Started Jan 10 12:29:45 PM PST 24
Finished Jan 10 12:30:20 PM PST 24
Peak memory 199180 kb
Host smart-ef408ba9-c954-4077-87d3-643d648930cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570103589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.2570103589
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.2105159459
Short name T148
Test name
Test status
Simulation time 8382713254 ps
CPU time 32.4 seconds
Started Jan 10 12:30:48 PM PST 24
Finished Jan 10 12:32:06 PM PST 24
Peak memory 199108 kb
Host smart-3250cec8-a2da-4f8a-bd06-b0b1dacab95d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105159459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.2105159459
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.3440973487
Short name T95
Test name
Test status
Simulation time 133314909 ps
CPU time 1.62 seconds
Started Jan 10 12:29:54 PM PST 24
Finished Jan 10 12:30:33 PM PST 24
Peak memory 198332 kb
Host smart-0313cd60-c0b9-428d-811d-d6643aa34bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440973487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.3440973487
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.2545974424
Short name T470
Test name
Test status
Simulation time 71029480 ps
CPU time 0.73 seconds
Started Jan 10 12:30:47 PM PST 24
Finished Jan 10 12:31:33 PM PST 24
Peak memory 198840 kb
Host smart-6e0eb4bc-2f1b-4996-be1f-6683ae8149ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545974424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.2545974424
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.439844021
Short name T491
Test name
Test status
Simulation time 62576759 ps
CPU time 0.71 seconds
Started Jan 10 12:31:51 PM PST 24
Finished Jan 10 12:32:38 PM PST 24
Peak memory 198888 kb
Host smart-6e1241e8-e6d0-4cf0-b4fa-ba23b3332126
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439844021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.439844021
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.4218319653
Short name T40
Test name
Test status
Simulation time 1871703818 ps
CPU time 8.09 seconds
Started Jan 10 12:27:12 PM PST 24
Finished Jan 10 12:27:25 PM PST 24
Peak memory 216108 kb
Host smart-34c3dd8f-b0e0-441d-aacd-8214fd2c8afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218319653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.4218319653
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.36926706
Short name T24
Test name
Test status
Simulation time 243910697 ps
CPU time 1.17 seconds
Started Jan 10 12:28:08 PM PST 24
Finished Jan 10 12:28:25 PM PST 24
Peak memory 216516 kb
Host smart-440f0d8a-b80e-4a14-9ddd-d7d6ab7b3c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36926706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.36926706
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.1476644995
Short name T20
Test name
Test status
Simulation time 103611113 ps
CPU time 0.72 seconds
Started Jan 10 12:30:33 PM PST 24
Finished Jan 10 12:31:16 PM PST 24
Peak memory 198784 kb
Host smart-90cd70d1-ab21-4e64-8e12-8e7020c7c96a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476644995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.1476644995
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.1925662232
Short name T523
Test name
Test status
Simulation time 847820756 ps
CPU time 4.14 seconds
Started Jan 10 12:32:04 PM PST 24
Finished Jan 10 12:32:54 PM PST 24
Peak memory 199188 kb
Host smart-f8238613-1ac1-4e5b-82b7-74c0375415ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925662232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.1925662232
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.3526457230
Short name T472
Test name
Test status
Simulation time 150316872 ps
CPU time 1.04 seconds
Started Jan 10 12:30:36 PM PST 24
Finished Jan 10 12:31:19 PM PST 24
Peak memory 199060 kb
Host smart-88531ee6-cd2a-422d-b9d8-beb50df2ae62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526457230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.3526457230
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.1525674463
Short name T400
Test name
Test status
Simulation time 118326500 ps
CPU time 1.13 seconds
Started Jan 10 12:29:56 PM PST 24
Finished Jan 10 12:30:36 PM PST 24
Peak memory 198560 kb
Host smart-7f4710b1-3fac-45d4-b4c8-0050a5579de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525674463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.1525674463
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.3722732945
Short name T107
Test name
Test status
Simulation time 5402372631 ps
CPU time 23.61 seconds
Started Jan 10 12:27:15 PM PST 24
Finished Jan 10 12:27:44 PM PST 24
Peak memory 199488 kb
Host smart-8b5255c2-c33c-49dd-80e6-bac55cadc473
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722732945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.3722732945
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.116447895
Short name T265
Test name
Test status
Simulation time 124579925 ps
CPU time 1.57 seconds
Started Jan 10 12:27:05 PM PST 24
Finished Jan 10 12:27:13 PM PST 24
Peak memory 199208 kb
Host smart-1d800ebf-a9dc-4852-8af4-a4cda1375b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116447895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.116447895
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.3986192554
Short name T415
Test name
Test status
Simulation time 178357870 ps
CPU time 1.16 seconds
Started Jan 10 12:30:37 PM PST 24
Finished Jan 10 12:31:21 PM PST 24
Peak memory 199072 kb
Host smart-7d881c8e-77f8-4f34-bd0a-28e586bf9779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986192554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.3986192554
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.1414540051
Short name T588
Test name
Test status
Simulation time 73440353 ps
CPU time 0.85 seconds
Started Jan 10 12:27:28 PM PST 24
Finished Jan 10 12:27:34 PM PST 24
Peak memory 199068 kb
Host smart-f1e54271-c092-4a79-8682-c2075a0f9dc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414540051 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.1414540051
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.2878504688
Short name T439
Test name
Test status
Simulation time 1873839496 ps
CPU time 6.75 seconds
Started Jan 10 12:28:09 PM PST 24
Finished Jan 10 12:28:31 PM PST 24
Peak memory 216160 kb
Host smart-88014b0a-7ef8-4ee5-b820-db8c3c7dfea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878504688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.2878504688
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.444339194
Short name T260
Test name
Test status
Simulation time 244570357 ps
CPU time 1.09 seconds
Started Jan 10 12:28:00 PM PST 24
Finished Jan 10 12:28:15 PM PST 24
Peak memory 216392 kb
Host smart-d04f5583-d839-4381-8484-17f0ac00f927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444339194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.444339194
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.2037673624
Short name T340
Test name
Test status
Simulation time 180078310 ps
CPU time 0.83 seconds
Started Jan 10 12:28:04 PM PST 24
Finished Jan 10 12:28:20 PM PST 24
Peak memory 199032 kb
Host smart-978afd27-2974-4cb4-ac2b-ebde1fa146fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037673624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.2037673624
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.4087117363
Short name T252
Test name
Test status
Simulation time 1760303085 ps
CPU time 6.39 seconds
Started Jan 10 12:27:44 PM PST 24
Finished Jan 10 12:28:04 PM PST 24
Peak memory 199352 kb
Host smart-b942c0fa-579a-4b6e-a984-38450903444c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087117363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.4087117363
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.689196139
Short name T604
Test name
Test status
Simulation time 105360007 ps
CPU time 1 seconds
Started Jan 10 12:27:28 PM PST 24
Finished Jan 10 12:27:34 PM PST 24
Peak memory 199284 kb
Host smart-e29426a1-eba6-4cfd-8252-2759c257f93e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689196139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.689196139
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.1225467214
Short name T374
Test name
Test status
Simulation time 200064940 ps
CPU time 1.22 seconds
Started Jan 10 12:29:52 PM PST 24
Finished Jan 10 12:30:29 PM PST 24
Peak memory 199112 kb
Host smart-a1e617c4-1a08-42dc-94d6-36612d760143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225467214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.1225467214
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.2048059627
Short name T50
Test name
Test status
Simulation time 3549602504 ps
CPU time 14.67 seconds
Started Jan 10 12:29:57 PM PST 24
Finished Jan 10 12:30:51 PM PST 24
Peak memory 199176 kb
Host smart-ee11f60c-5bba-445b-8821-2742819dae22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048059627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.2048059627
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.526145749
Short name T93
Test name
Test status
Simulation time 445822129 ps
CPU time 2.17 seconds
Started Jan 10 12:29:56 PM PST 24
Finished Jan 10 12:30:36 PM PST 24
Peak memory 198992 kb
Host smart-d7dfb78e-5228-4233-bf3f-b32ff1275692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526145749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.526145749
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.2026773887
Short name T147
Test name
Test status
Simulation time 96861299 ps
CPU time 0.84 seconds
Started Jan 10 12:31:54 PM PST 24
Finished Jan 10 12:32:41 PM PST 24
Peak memory 199060 kb
Host smart-81e7a77e-6e64-4dd9-adb4-f5a74d2c5eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026773887 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.2026773887
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.3510174571
Short name T318
Test name
Test status
Simulation time 62150653 ps
CPU time 0.68 seconds
Started Jan 10 12:30:45 PM PST 24
Finished Jan 10 12:31:31 PM PST 24
Peak memory 198832 kb
Host smart-e4a9595b-fed8-4851-b106-b2cb23666176
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510174571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.3510174571
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.411268202
Short name T483
Test name
Test status
Simulation time 1892840962 ps
CPU time 8.22 seconds
Started Jan 10 12:27:20 PM PST 24
Finished Jan 10 12:27:34 PM PST 24
Peak memory 216540 kb
Host smart-732b9d78-93ca-4051-96c2-bb39fb7a5547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411268202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.411268202
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.3949215719
Short name T307
Test name
Test status
Simulation time 245537863 ps
CPU time 1.05 seconds
Started Jan 10 12:30:32 PM PST 24
Finished Jan 10 12:31:16 PM PST 24
Peak memory 216080 kb
Host smart-976bae19-417e-4c71-bbe2-df83ad3e872f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949215719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.3949215719
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.1366515406
Short name T435
Test name
Test status
Simulation time 86703974 ps
CPU time 0.7 seconds
Started Jan 10 12:27:59 PM PST 24
Finished Jan 10 12:28:15 PM PST 24
Peak memory 199040 kb
Host smart-987b5774-674f-4e31-9d0d-3d98f0c96411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366515406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.1366515406
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.2731057194
Short name T106
Test name
Test status
Simulation time 1804291018 ps
CPU time 6.59 seconds
Started Jan 10 12:28:09 PM PST 24
Finished Jan 10 12:28:31 PM PST 24
Peak memory 199432 kb
Host smart-d95dbd15-9ad5-4657-9596-1166eb648e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731057194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.2731057194
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.3445145363
Short name T602
Test name
Test status
Simulation time 185447925 ps
CPU time 1.15 seconds
Started Jan 10 12:28:04 PM PST 24
Finished Jan 10 12:28:20 PM PST 24
Peak memory 198424 kb
Host smart-280fa80a-bfaf-473f-9b54-b5382322400f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445145363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.3445145363
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.955433261
Short name T254
Test name
Test status
Simulation time 252789785 ps
CPU time 1.42 seconds
Started Jan 10 12:29:34 PM PST 24
Finished Jan 10 12:30:03 PM PST 24
Peak memory 198204 kb
Host smart-845e6048-2052-438b-bda0-49c0bad21496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955433261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.955433261
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.4189698046
Short name T417
Test name
Test status
Simulation time 1953171442 ps
CPU time 8.73 seconds
Started Jan 10 12:30:29 PM PST 24
Finished Jan 10 12:31:19 PM PST 24
Peak memory 198580 kb
Host smart-220c6204-bb60-4981-bac2-623a9a7447c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189698046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.4189698046
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.1434164805
Short name T357
Test name
Test status
Simulation time 128230526 ps
CPU time 1.55 seconds
Started Jan 10 12:28:04 PM PST 24
Finished Jan 10 12:28:21 PM PST 24
Peak memory 199180 kb
Host smart-2009806a-38d5-4a69-a3bf-3490197bde6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434164805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.1434164805
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.1446017327
Short name T434
Test name
Test status
Simulation time 140942884 ps
CPU time 1.18 seconds
Started Jan 10 12:29:34 PM PST 24
Finished Jan 10 12:30:03 PM PST 24
Peak memory 197860 kb
Host smart-3e260644-3ca1-427a-b13d-2a5771ac84c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446017327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.1446017327
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.903583096
Short name T309
Test name
Test status
Simulation time 64201520 ps
CPU time 0.68 seconds
Started Jan 10 12:31:10 PM PST 24
Finished Jan 10 12:31:57 PM PST 24
Peak memory 198880 kb
Host smart-d8bb1737-fb81-4f26-a48d-a747e000cb22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903583096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.903583096
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.4199749466
Short name T608
Test name
Test status
Simulation time 2365139243 ps
CPU time 8.23 seconds
Started Jan 10 12:30:06 PM PST 24
Finished Jan 10 12:30:55 PM PST 24
Peak memory 215316 kb
Host smart-02cc680a-ba79-485a-927c-bc92d37f2717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199749466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.4199749466
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.1161504928
Short name T566
Test name
Test status
Simulation time 252617329 ps
CPU time 1.03 seconds
Started Jan 10 12:31:20 PM PST 24
Finished Jan 10 12:32:07 PM PST 24
Peak memory 216292 kb
Host smart-632abac8-4da7-4d29-9ad2-05a567d070ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161504928 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.1161504928
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.2383177089
Short name T371
Test name
Test status
Simulation time 118787331 ps
CPU time 0.74 seconds
Started Jan 10 12:30:43 PM PST 24
Finished Jan 10 12:31:28 PM PST 24
Peak memory 198780 kb
Host smart-c27c7c98-187b-4a59-b24e-f71bc29f8eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383177089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.2383177089
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.389990178
Short name T527
Test name
Test status
Simulation time 1047955614 ps
CPU time 4.64 seconds
Started Jan 10 12:27:28 PM PST 24
Finished Jan 10 12:27:37 PM PST 24
Peak memory 199332 kb
Host smart-de4ab947-a536-4fdc-96a7-aa67d5e42909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389990178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.389990178
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.588627209
Short name T270
Test name
Test status
Simulation time 168487321 ps
CPU time 1.13 seconds
Started Jan 10 12:30:59 PM PST 24
Finished Jan 10 12:31:48 PM PST 24
Peak memory 198032 kb
Host smart-c08ee7e6-eaed-4774-a2d6-5160e380e90e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588627209 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.588627209
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.3002758542
Short name T528
Test name
Test status
Simulation time 125445950 ps
CPU time 1.12 seconds
Started Jan 10 12:31:20 PM PST 24
Finished Jan 10 12:32:07 PM PST 24
Peak memory 199172 kb
Host smart-ada53215-aa0b-44e6-aea7-7bbc5c2bbb41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002758542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.3002758542
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.3793913800
Short name T288
Test name
Test status
Simulation time 8656885396 ps
CPU time 28.37 seconds
Started Jan 10 12:30:33 PM PST 24
Finished Jan 10 12:31:51 PM PST 24
Peak memory 199192 kb
Host smart-5e6d1fce-8471-46b6-a560-796fce0176d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793913800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.3793913800
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.2615596882
Short name T48
Test name
Test status
Simulation time 137569063 ps
CPU time 1.59 seconds
Started Jan 10 12:30:26 PM PST 24
Finished Jan 10 12:31:08 PM PST 24
Peak memory 198980 kb
Host smart-dd9d118a-ea5c-4749-baa9-12a33af3f021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615596882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.2615596882
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.2519337715
Short name T401
Test name
Test status
Simulation time 93358789 ps
CPU time 0.92 seconds
Started Jan 10 12:30:03 PM PST 24
Finished Jan 10 12:30:45 PM PST 24
Peak memory 198168 kb
Host smart-52a57798-a2d7-4d41-bcc6-5e67d763f604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519337715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.2519337715
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.2776075004
Short name T79
Test name
Test status
Simulation time 147743614 ps
CPU time 0.86 seconds
Started Jan 10 12:30:44 PM PST 24
Finished Jan 10 12:31:29 PM PST 24
Peak memory 198928 kb
Host smart-7b096d60-f2c2-4a34-a366-34b05353bb72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776075004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.2776075004
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.851626371
Short name T606
Test name
Test status
Simulation time 1901288203 ps
CPU time 6.39 seconds
Started Jan 10 12:31:17 PM PST 24
Finished Jan 10 12:32:09 PM PST 24
Peak memory 217424 kb
Host smart-ef69fba4-68a6-4e4b-8419-31e0e78334f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851626371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.851626371
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.3265069710
Short name T489
Test name
Test status
Simulation time 243660584 ps
CPU time 1.13 seconds
Started Jan 10 12:27:28 PM PST 24
Finished Jan 10 12:27:34 PM PST 24
Peak memory 216384 kb
Host smart-84f1fe8e-eb6a-4f05-8fbf-86d59ff505c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265069710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.3265069710
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.3336416460
Short name T382
Test name
Test status
Simulation time 185826205 ps
CPU time 0.83 seconds
Started Jan 10 12:30:30 PM PST 24
Finished Jan 10 12:31:19 PM PST 24
Peak memory 198680 kb
Host smart-69152f94-63ea-49a2-a1a2-36b9e9a2f777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336416460 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.3336416460
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.4198397165
Short name T146
Test name
Test status
Simulation time 1754958149 ps
CPU time 6.12 seconds
Started Jan 10 12:30:48 PM PST 24
Finished Jan 10 12:31:39 PM PST 24
Peak memory 199128 kb
Host smart-36d54e39-b1a8-4387-b41e-91910118e65f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198397165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.4198397165
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.15766429
Short name T88
Test name
Test status
Simulation time 248823482 ps
CPU time 1.34 seconds
Started Jan 10 12:31:17 PM PST 24
Finished Jan 10 12:32:04 PM PST 24
Peak memory 199128 kb
Host smart-de78f592-ea0b-489e-80b1-21688dff8fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15766429 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.15766429
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.3678892781
Short name T546
Test name
Test status
Simulation time 11293322313 ps
CPU time 34.14 seconds
Started Jan 10 12:31:14 PM PST 24
Finished Jan 10 12:32:34 PM PST 24
Peak memory 199172 kb
Host smart-54b2bf16-e460-416f-a679-d93782722e0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678892781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.3678892781
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.3558574372
Short name T571
Test name
Test status
Simulation time 126065652 ps
CPU time 1.44 seconds
Started Jan 10 12:30:19 PM PST 24
Finished Jan 10 12:31:00 PM PST 24
Peak memory 198968 kb
Host smart-a8502b7e-1b99-4766-80a1-5ffc94deb8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558574372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.3558574372
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.1701523323
Short name T445
Test name
Test status
Simulation time 125247206 ps
CPU time 0.98 seconds
Started Jan 10 12:30:43 PM PST 24
Finished Jan 10 12:31:28 PM PST 24
Peak memory 198984 kb
Host smart-b9e89b5b-b67e-49d7-a701-cc5f12b1b525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701523323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.1701523323
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.1708890347
Short name T532
Test name
Test status
Simulation time 69447938 ps
CPU time 0.69 seconds
Started Jan 10 12:29:48 PM PST 24
Finished Jan 10 12:30:22 PM PST 24
Peak memory 198820 kb
Host smart-539f5070-701b-4c26-92e1-8027f9dfeffe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708890347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.1708890347
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.1487098198
Short name T33
Test name
Test status
Simulation time 1223788621 ps
CPU time 5.44 seconds
Started Jan 10 12:28:01 PM PST 24
Finished Jan 10 12:28:21 PM PST 24
Peak memory 221232 kb
Host smart-f53169ea-d335-49c2-ad3b-beed2a76f067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487098198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.1487098198
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.3439894943
Short name T377
Test name
Test status
Simulation time 245122384 ps
CPU time 0.99 seconds
Started Jan 10 12:30:46 PM PST 24
Finished Jan 10 12:31:32 PM PST 24
Peak memory 216300 kb
Host smart-7f20252b-0332-400d-a4f0-7e7477ddc574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439894943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.3439894943
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.500106633
Short name T313
Test name
Test status
Simulation time 73490757 ps
CPU time 0.71 seconds
Started Jan 10 12:30:59 PM PST 24
Finished Jan 10 12:31:47 PM PST 24
Peak memory 197960 kb
Host smart-246b44e4-6e6e-4a98-a6ff-b9b5c4b7422c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500106633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.500106633
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.4129862821
Short name T242
Test name
Test status
Simulation time 1590625893 ps
CPU time 5.83 seconds
Started Jan 10 12:30:35 PM PST 24
Finished Jan 10 12:31:23 PM PST 24
Peak memory 199232 kb
Host smart-b567af0b-8ee9-4b8f-acaa-c4b6560bda96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129862821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.4129862821
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.1758958437
Short name T296
Test name
Test status
Simulation time 157616913 ps
CPU time 1.17 seconds
Started Jan 10 12:27:54 PM PST 24
Finished Jan 10 12:28:08 PM PST 24
Peak memory 199172 kb
Host smart-328a4ed6-4e36-46ee-a81e-3de615df6fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758958437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.1758958437
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.3205997675
Short name T614
Test name
Test status
Simulation time 114317784 ps
CPU time 1.08 seconds
Started Jan 10 12:31:15 PM PST 24
Finished Jan 10 12:32:01 PM PST 24
Peak memory 199104 kb
Host smart-f34f8554-5e34-432d-ac96-bc293b5b7800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205997675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.3205997675
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.867307372
Short name T339
Test name
Test status
Simulation time 142453910 ps
CPU time 1.62 seconds
Started Jan 10 12:27:59 PM PST 24
Finished Jan 10 12:28:15 PM PST 24
Peak memory 199204 kb
Host smart-cd3567fc-7a98-4e33-aec6-57f305d945fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867307372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.867307372
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.1724903930
Short name T493
Test name
Test status
Simulation time 215113519 ps
CPU time 1.21 seconds
Started Jan 10 12:30:44 PM PST 24
Finished Jan 10 12:31:29 PM PST 24
Peak memory 198980 kb
Host smart-4aa079c1-6ace-4b34-b5f4-3e926d7e673f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724903930 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.1724903930
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.1527630535
Short name T365
Test name
Test status
Simulation time 69694169 ps
CPU time 0.77 seconds
Started Jan 10 12:27:51 PM PST 24
Finished Jan 10 12:28:07 PM PST 24
Peak memory 199060 kb
Host smart-dd11b601-0d1e-42fe-b609-2b9517e12d1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527630535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.1527630535
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.4135133656
Short name T32
Test name
Test status
Simulation time 1220866850 ps
CPU time 5.99 seconds
Started Jan 10 12:28:27 PM PST 24
Finished Jan 10 12:28:44 PM PST 24
Peak memory 217136 kb
Host smart-9a2c3869-e452-4b85-8cf3-4fc2464cea9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135133656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.4135133656
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.2990381045
Short name T62
Test name
Test status
Simulation time 243786920 ps
CPU time 1.09 seconds
Started Jan 10 12:28:06 PM PST 24
Finished Jan 10 12:28:23 PM PST 24
Peak memory 216436 kb
Host smart-46d66dc1-03c8-43cd-ac5c-0401eed48d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990381045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.2990381045
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.1158512580
Short name T519
Test name
Test status
Simulation time 160529086 ps
CPU time 0.81 seconds
Started Jan 10 12:30:01 PM PST 24
Finished Jan 10 12:30:44 PM PST 24
Peak memory 198200 kb
Host smart-1d550593-61ba-4af3-b401-b415d411fd3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158512580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.1158512580
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.3225527911
Short name T478
Test name
Test status
Simulation time 1738794341 ps
CPU time 6.02 seconds
Started Jan 10 12:27:53 PM PST 24
Finished Jan 10 12:28:12 PM PST 24
Peak memory 199372 kb
Host smart-312af237-155b-4c77-916e-ce77aa52164f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225527911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.3225527911
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.2620646768
Short name T392
Test name
Test status
Simulation time 107780082 ps
CPU time 0.94 seconds
Started Jan 10 12:30:01 PM PST 24
Finished Jan 10 12:30:44 PM PST 24
Peak memory 199044 kb
Host smart-ae3ea84e-4c1e-4772-ab83-2bf6baf561b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620646768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.2620646768
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.3541245223
Short name T529
Test name
Test status
Simulation time 112482761 ps
CPU time 1.12 seconds
Started Jan 10 12:27:59 PM PST 24
Finished Jan 10 12:28:14 PM PST 24
Peak memory 199388 kb
Host smart-be61b85f-cd15-4def-b7a6-029b2832a44b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541245223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.3541245223
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.3998639263
Short name T420
Test name
Test status
Simulation time 2040124904 ps
CPU time 7.04 seconds
Started Jan 10 12:29:31 PM PST 24
Finished Jan 10 12:30:04 PM PST 24
Peak memory 198368 kb
Host smart-bd912a49-330c-49a2-b9cf-79f542f0281f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998639263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.3998639263
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.2152222644
Short name T94
Test name
Test status
Simulation time 260032694 ps
CPU time 1.81 seconds
Started Jan 10 12:28:00 PM PST 24
Finished Jan 10 12:28:16 PM PST 24
Peak memory 199184 kb
Host smart-de19e837-0fbf-4564-ba13-fcfa3102085d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152222644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.2152222644
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.3781490768
Short name T334
Test name
Test status
Simulation time 85745129 ps
CPU time 0.83 seconds
Started Jan 10 12:29:49 PM PST 24
Finished Jan 10 12:30:24 PM PST 24
Peak memory 198996 kb
Host smart-e6c44405-5c15-4a2a-a807-9c9421665652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781490768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.3781490768
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.3504907967
Short name T349
Test name
Test status
Simulation time 127158243 ps
CPU time 0.86 seconds
Started Jan 10 12:43:07 PM PST 24
Finished Jan 10 12:44:21 PM PST 24
Peak memory 199152 kb
Host smart-16d01bda-c94c-4d4d-be2c-8525250c26ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504907967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.3504907967
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.1653727812
Short name T261
Test name
Test status
Simulation time 2371217240 ps
CPU time 7.71 seconds
Started Jan 10 12:44:36 PM PST 24
Finished Jan 10 12:46:01 PM PST 24
Peak memory 217348 kb
Host smart-1c301f68-7dd3-40bb-93e1-3c3b2f0d2b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653727812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.1653727812
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.3264419896
Short name T409
Test name
Test status
Simulation time 246164024 ps
CPU time 1.08 seconds
Started Jan 10 12:36:04 PM PST 24
Finished Jan 10 12:36:30 PM PST 24
Peak memory 216740 kb
Host smart-f4e139b1-11f5-4d22-9eb9-39c11bdf3886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264419896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.3264419896
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.470478827
Short name T22
Test name
Test status
Simulation time 214657601 ps
CPU time 0.86 seconds
Started Jan 10 01:09:47 PM PST 24
Finished Jan 10 01:10:54 PM PST 24
Peak memory 199168 kb
Host smart-7b68a3a1-55ec-4f3a-8b64-0a89ba9a2902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470478827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.470478827
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.785426433
Short name T90
Test name
Test status
Simulation time 863296055 ps
CPU time 4.42 seconds
Started Jan 10 01:28:20 PM PST 24
Finished Jan 10 01:29:09 PM PST 24
Peak memory 199660 kb
Host smart-08f48740-509c-440c-bc11-f216739ed7fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785426433 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.785426433
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.291207297
Short name T363
Test name
Test status
Simulation time 109734590 ps
CPU time 0.96 seconds
Started Jan 10 12:35:22 PM PST 24
Finished Jan 10 12:35:52 PM PST 24
Peak memory 199344 kb
Host smart-604773ee-7e98-4f5c-a366-920dcd9db33f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291207297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.291207297
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.696900395
Short name T368
Test name
Test status
Simulation time 257441104 ps
CPU time 1.38 seconds
Started Jan 10 12:51:00 PM PST 24
Finished Jan 10 12:52:28 PM PST 24
Peak memory 199400 kb
Host smart-13ec92b6-ba6c-412b-814c-444d756bae39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696900395 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.696900395
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.1602022461
Short name T449
Test name
Test status
Simulation time 11459865288 ps
CPU time 44.82 seconds
Started Jan 10 12:49:55 PM PST 24
Finished Jan 10 12:52:20 PM PST 24
Peak memory 199540 kb
Host smart-0254d46e-dff1-49d6-9934-31729194430e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602022461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.1602022461
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.3530613792
Short name T6
Test name
Test status
Simulation time 159915587 ps
CPU time 1.76 seconds
Started Jan 10 12:59:18 PM PST 24
Finished Jan 10 01:00:54 PM PST 24
Peak memory 198324 kb
Host smart-ced6e215-4728-4fd7-94eb-9bca6411173e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530613792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.3530613792
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.3620102310
Short name T428
Test name
Test status
Simulation time 117320633 ps
CPU time 0.94 seconds
Started Jan 10 12:31:40 PM PST 24
Finished Jan 10 12:32:32 PM PST 24
Peak memory 198988 kb
Host smart-ab05dc9e-ec72-4227-a73e-c062439191cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620102310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.3620102310
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.3588973109
Short name T387
Test name
Test status
Simulation time 59165362 ps
CPU time 0.7 seconds
Started Jan 10 12:37:43 PM PST 24
Finished Jan 10 12:38:19 PM PST 24
Peak memory 199116 kb
Host smart-5e9b13ed-97a2-4753-85aa-41a90ccd832a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588973109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.3588973109
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.1269061237
Short name T275
Test name
Test status
Simulation time 1222491723 ps
CPU time 5.69 seconds
Started Jan 10 12:40:27 PM PST 24
Finished Jan 10 12:41:19 PM PST 24
Peak memory 221216 kb
Host smart-02b1d40d-6610-4ded-858b-55f2940231ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269061237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.1269061237
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.3553709818
Short name T343
Test name
Test status
Simulation time 244108769 ps
CPU time 1.03 seconds
Started Jan 10 01:07:15 PM PST 24
Finished Jan 10 01:08:37 PM PST 24
Peak memory 216480 kb
Host smart-0989b6be-dc47-44c5-90f2-5c13e91d1b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553709818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.3553709818
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.2135194257
Short name T253
Test name
Test status
Simulation time 96483930 ps
CPU time 0.7 seconds
Started Jan 10 12:47:12 PM PST 24
Finished Jan 10 12:48:38 PM PST 24
Peak memory 199048 kb
Host smart-de709efa-5867-4181-a9fc-1abbdc35baf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135194257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.2135194257
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.2429271725
Short name T453
Test name
Test status
Simulation time 1334077584 ps
CPU time 4.73 seconds
Started Jan 10 12:34:31 PM PST 24
Finished Jan 10 12:35:15 PM PST 24
Peak memory 199424 kb
Host smart-47cca60e-2cf7-4e71-9e74-53b1ec470c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429271725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.2429271725
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.804376615
Short name T436
Test name
Test status
Simulation time 114572029 ps
CPU time 0.95 seconds
Started Jan 10 12:34:57 PM PST 24
Finished Jan 10 12:35:38 PM PST 24
Peak memory 199268 kb
Host smart-15d530dd-55af-42af-ac13-3681541a3fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804376615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.804376615
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.769772463
Short name T12
Test name
Test status
Simulation time 119489480 ps
CPU time 1.14 seconds
Started Jan 10 12:51:25 PM PST 24
Finished Jan 10 12:52:47 PM PST 24
Peak memory 199452 kb
Host smart-ad4586ad-ad37-4f29-8c10-b6e3d1eea227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769772463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.769772463
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.1806245347
Short name T433
Test name
Test status
Simulation time 5016451731 ps
CPU time 17.55 seconds
Started Jan 10 12:39:52 PM PST 24
Finished Jan 10 12:40:45 PM PST 24
Peak memory 199540 kb
Host smart-2ac3750d-cc7a-4064-9e6a-ceeb39093631
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806245347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.1806245347
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.363235443
Short name T452
Test name
Test status
Simulation time 336039738 ps
CPU time 1.98 seconds
Started Jan 10 12:48:48 PM PST 24
Finished Jan 10 12:50:18 PM PST 24
Peak memory 199256 kb
Host smart-0bac2e9e-fae7-4f01-aa16-30cd65f7dbb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363235443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.363235443
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.236794644
Short name T475
Test name
Test status
Simulation time 66286002 ps
CPU time 0.77 seconds
Started Jan 10 12:44:09 PM PST 24
Finished Jan 10 12:45:25 PM PST 24
Peak memory 199304 kb
Host smart-c1159d3d-d258-473a-9a49-da49d19e29c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236794644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.236794644
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.3238973351
Short name T525
Test name
Test status
Simulation time 70278450 ps
CPU time 0.72 seconds
Started Jan 10 12:45:08 PM PST 24
Finished Jan 10 12:46:35 PM PST 24
Peak memory 199184 kb
Host smart-20281d0b-6c03-4ad9-90e0-13974ef023f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238973351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.3238973351
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.3513365724
Short name T542
Test name
Test status
Simulation time 1227748447 ps
CPU time 5.56 seconds
Started Jan 10 12:46:29 PM PST 24
Finished Jan 10 12:48:09 PM PST 24
Peak memory 216724 kb
Host smart-62a849a3-cc50-47eb-b60d-12e17aa21bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513365724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.3513365724
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.747750527
Short name T269
Test name
Test status
Simulation time 244152951 ps
CPU time 1.08 seconds
Started Jan 10 12:53:17 PM PST 24
Finished Jan 10 12:54:31 PM PST 24
Peak memory 216556 kb
Host smart-1c90416a-1bde-42c4-885e-7227403d6fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747750527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.747750527
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.510947041
Short name T342
Test name
Test status
Simulation time 247831578 ps
CPU time 0.93 seconds
Started Jan 10 12:43:00 PM PST 24
Finished Jan 10 12:44:15 PM PST 24
Peak memory 199140 kb
Host smart-7a347bbd-48af-4ca2-b323-e40c775b5fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510947041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.510947041
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.171569612
Short name T239
Test name
Test status
Simulation time 1487784000 ps
CPU time 5.58 seconds
Started Jan 10 12:50:14 PM PST 24
Finished Jan 10 12:51:56 PM PST 24
Peak memory 199472 kb
Host smart-3d0d7d1e-4753-471d-a58c-c4def3ac7b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171569612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.171569612
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.884384629
Short name T154
Test name
Test status
Simulation time 160313879 ps
CPU time 1.05 seconds
Started Jan 10 01:08:40 PM PST 24
Finished Jan 10 01:09:56 PM PST 24
Peak memory 199348 kb
Host smart-6b3b32e2-ec4b-4109-87b6-5063e359f341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884384629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.884384629
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.4194575284
Short name T466
Test name
Test status
Simulation time 114822296 ps
CPU time 1.11 seconds
Started Jan 10 12:45:34 PM PST 24
Finished Jan 10 12:46:53 PM PST 24
Peak memory 199404 kb
Host smart-fb43b448-3183-4f17-8299-84081b4c7806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194575284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.4194575284
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.838537060
Short name T388
Test name
Test status
Simulation time 2846308024 ps
CPU time 9.48 seconds
Started Jan 10 12:34:14 PM PST 24
Finished Jan 10 12:34:54 PM PST 24
Peak memory 199456 kb
Host smart-7fd13000-34dc-4237-a103-6a69c0cf6517
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838537060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.838537060
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.898459982
Short name T271
Test name
Test status
Simulation time 324109169 ps
CPU time 2.06 seconds
Started Jan 10 01:10:56 PM PST 24
Finished Jan 10 01:12:26 PM PST 24
Peak memory 199376 kb
Host smart-e4d5c73e-cd61-4083-b41c-0145c6ec076d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898459982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.898459982
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.2462509074
Short name T455
Test name
Test status
Simulation time 108201801 ps
CPU time 0.96 seconds
Started Jan 10 12:29:32 PM PST 24
Finished Jan 10 12:29:58 PM PST 24
Peak memory 199292 kb
Host smart-9eebf9a0-fbfb-4710-8945-195c0ce4e93b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462509074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.2462509074
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.2381462449
Short name T488
Test name
Test status
Simulation time 84564790 ps
CPU time 0.76 seconds
Started Jan 10 12:43:08 PM PST 24
Finished Jan 10 12:44:22 PM PST 24
Peak memory 199160 kb
Host smart-76b09272-153a-437d-b39e-e9d4a42bc08d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381462449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.2381462449
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.2442765049
Short name T508
Test name
Test status
Simulation time 1223333868 ps
CPU time 5.41 seconds
Started Jan 10 12:37:29 PM PST 24
Finished Jan 10 12:38:10 PM PST 24
Peak memory 220300 kb
Host smart-c9410e77-df5c-4fbf-a2f6-101d29c481bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442765049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.2442765049
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.2677681670
Short name T282
Test name
Test status
Simulation time 245566003 ps
CPU time 1.05 seconds
Started Jan 10 12:34:27 PM PST 24
Finished Jan 10 12:35:06 PM PST 24
Peak memory 216324 kb
Host smart-e34eab6d-78bb-4ed6-8708-d5b2bc55aa49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677681670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.2677681670
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.1820628440
Short name T157
Test name
Test status
Simulation time 155120168 ps
CPU time 0.78 seconds
Started Jan 10 12:46:32 PM PST 24
Finished Jan 10 12:47:47 PM PST 24
Peak memory 199084 kb
Host smart-bea86526-fbed-45a0-9c31-38e285dc7b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820628440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.1820628440
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.2284074558
Short name T319
Test name
Test status
Simulation time 2083679687 ps
CPU time 6.8 seconds
Started Jan 10 12:44:02 PM PST 24
Finished Jan 10 12:45:25 PM PST 24
Peak memory 199440 kb
Host smart-82d60cfe-bf93-42c7-af69-8ba71d61f520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284074558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.2284074558
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.3041526770
Short name T300
Test name
Test status
Simulation time 187162214 ps
CPU time 1.16 seconds
Started Jan 10 12:30:40 PM PST 24
Finished Jan 10 12:31:24 PM PST 24
Peak memory 198176 kb
Host smart-b00b4e3d-ac2d-46c7-b8af-55234984fa43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041526770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.3041526770
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.1597523559
Short name T480
Test name
Test status
Simulation time 111457647 ps
CPU time 1.12 seconds
Started Jan 10 12:44:05 PM PST 24
Finished Jan 10 12:45:21 PM PST 24
Peak memory 199480 kb
Host smart-5545fc21-3894-43c8-83a4-99cc50a57ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597523559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.1597523559
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.1114603877
Short name T267
Test name
Test status
Simulation time 2358635776 ps
CPU time 11.02 seconds
Started Jan 10 12:35:50 PM PST 24
Finished Jan 10 12:36:25 PM PST 24
Peak memory 199576 kb
Host smart-c2380ff8-2aa6-4ac6-b78e-10e4737ec502
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114603877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.1114603877
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.590033923
Short name T458
Test name
Test status
Simulation time 264737415 ps
CPU time 1.74 seconds
Started Jan 10 12:37:28 PM PST 24
Finished Jan 10 12:38:05 PM PST 24
Peak memory 199276 kb
Host smart-91e40de6-6ced-4e9c-9925-9466c7793ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590033923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.590033923
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.3747264422
Short name T241
Test name
Test status
Simulation time 113273802 ps
CPU time 0.94 seconds
Started Jan 10 12:38:42 PM PST 24
Finished Jan 10 12:39:16 PM PST 24
Peak memory 199352 kb
Host smart-12d56fe3-4257-4e33-9e6e-3177e0fba903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747264422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.3747264422
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.1089754167
Short name T407
Test name
Test status
Simulation time 126859723 ps
CPU time 0.88 seconds
Started Jan 10 12:31:41 PM PST 24
Finished Jan 10 12:32:32 PM PST 24
Peak memory 197500 kb
Host smart-7fd22336-6da7-45af-a295-1268778c5fcb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089754167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.1089754167
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.3152987961
Short name T36
Test name
Test status
Simulation time 1230869813 ps
CPU time 5.47 seconds
Started Jan 10 12:35:30 PM PST 24
Finished Jan 10 12:36:02 PM PST 24
Peak memory 217232 kb
Host smart-8be895ff-6c1d-46e8-95c5-7a05637a803c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152987961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.3152987961
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.3298087892
Short name T246
Test name
Test status
Simulation time 244733842 ps
CPU time 1.01 seconds
Started Jan 10 12:43:03 PM PST 24
Finished Jan 10 12:44:26 PM PST 24
Peak memory 216416 kb
Host smart-7e502d42-fc93-4e8c-b208-0bf34251af09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298087892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.3298087892
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.1989921290
Short name T545
Test name
Test status
Simulation time 126487199 ps
CPU time 0.8 seconds
Started Jan 10 12:54:15 PM PST 24
Finished Jan 10 12:55:22 PM PST 24
Peak memory 199072 kb
Host smart-4d5b2ef5-c513-48f3-b4c9-489d3eb21873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989921290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.1989921290
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.3248985088
Short name T108
Test name
Test status
Simulation time 1453167966 ps
CPU time 5.87 seconds
Started Jan 10 12:30:15 PM PST 24
Finished Jan 10 12:31:00 PM PST 24
Peak memory 199200 kb
Host smart-2a9ed6e6-6d6b-4641-b764-c60f2999baa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248985088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.3248985088
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.1984560013
Short name T562
Test name
Test status
Simulation time 161820548 ps
CPU time 1.15 seconds
Started Jan 10 12:52:55 PM PST 24
Finished Jan 10 12:54:10 PM PST 24
Peak memory 199292 kb
Host smart-1c9f44d2-5f33-493f-9337-0dd0427a33ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984560013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.1984560013
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.1132092067
Short name T44
Test name
Test status
Simulation time 249284880 ps
CPU time 1.5 seconds
Started Jan 10 12:46:15 PM PST 24
Finished Jan 10 12:47:34 PM PST 24
Peak memory 199520 kb
Host smart-463a4c37-8b2d-473e-9144-9147354ffc09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132092067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.1132092067
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.3356228972
Short name T410
Test name
Test status
Simulation time 8653391282 ps
CPU time 28.77 seconds
Started Jan 10 12:28:51 PM PST 24
Finished Jan 10 12:29:36 PM PST 24
Peak memory 199460 kb
Host smart-e51894d5-ff4e-446d-ace9-f5bf9c2a76fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356228972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.3356228972
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.813717299
Short name T517
Test name
Test status
Simulation time 269277792 ps
CPU time 1.75 seconds
Started Jan 10 12:27:47 PM PST 24
Finished Jan 10 12:28:01 PM PST 24
Peak memory 199212 kb
Host smart-f8ae8177-fdf3-466f-bb55-e5138f638f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813717299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.813717299
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.2965845042
Short name T281
Test name
Test status
Simulation time 211330392 ps
CPU time 1.24 seconds
Started Jan 10 12:38:54 PM PST 24
Finished Jan 10 12:39:27 PM PST 24
Peak memory 199272 kb
Host smart-d6228eb0-e8f3-471e-97f3-e3069e2f21f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965845042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.2965845042
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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