Summary for Variable enable
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1600 |
1 |
|
|
T62 |
32 |
|
T54 |
32 |
|
T67 |
32 |
auto[1] |
4759 |
1 |
|
|
T2 |
17 |
|
T3 |
65 |
|
T5 |
23 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1600 |
1 |
|
|
T62 |
32 |
|
T54 |
32 |
|
T67 |
32 |
auto[1] |
4759 |
1 |
|
|
T2 |
17 |
|
T3 |
65 |
|
T5 |
23 |
Summary for Variable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1823 |
1 |
|
|
T2 |
3 |
|
T3 |
28 |
|
T5 |
2 |
auto[1] |
4536 |
1 |
|
|
T2 |
14 |
|
T3 |
37 |
|
T5 |
21 |
Summary for Variable rst_n_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1823 |
1 |
|
|
T2 |
3 |
|
T3 |
28 |
|
T5 |
2 |
auto[1] |
4536 |
1 |
|
|
T2 |
14 |
|
T3 |
37 |
|
T5 |
21 |
Summary for Cross sw_rst_cross
Samples crossed: enable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for sw_rst_cross
Bins
enable | rst_n | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
400 |
1 |
|
|
T62 |
8 |
|
T54 |
8 |
|
T67 |
8 |
auto[0] |
auto[1] |
1200 |
1 |
|
|
T62 |
24 |
|
T54 |
24 |
|
T67 |
24 |
auto[1] |
auto[0] |
1423 |
1 |
|
|
T2 |
3 |
|
T3 |
28 |
|
T5 |
2 |
auto[1] |
auto[1] |
3336 |
1 |
|
|
T2 |
14 |
|
T3 |
37 |
|
T5 |
21 |
Summary for Variable enable
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1472 |
1 |
|
|
T62 |
28 |
|
T54 |
28 |
|
T63 |
3 |
auto[1] |
4683 |
1 |
|
|
T2 |
11 |
|
T3 |
65 |
|
T5 |
17 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1472 |
1 |
|
|
T62 |
28 |
|
T54 |
28 |
|
T63 |
3 |
auto[1] |
4683 |
1 |
|
|
T2 |
11 |
|
T3 |
65 |
|
T5 |
17 |
Summary for Variable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1786 |
1 |
|
|
T3 |
17 |
|
T7 |
3 |
|
T62 |
13 |
auto[1] |
4369 |
1 |
|
|
T2 |
11 |
|
T3 |
48 |
|
T5 |
17 |
Summary for Variable rst_n_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1786 |
1 |
|
|
T3 |
17 |
|
T7 |
3 |
|
T62 |
13 |
auto[1] |
4369 |
1 |
|
|
T2 |
11 |
|
T3 |
48 |
|
T5 |
17 |
Summary for Cross sw_rst_cross
Samples crossed: enable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for sw_rst_cross
Bins
enable | rst_n | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
386 |
1 |
|
|
T62 |
7 |
|
T54 |
7 |
|
T63 |
2 |
auto[0] |
auto[1] |
1086 |
1 |
|
|
T62 |
21 |
|
T54 |
21 |
|
T63 |
1 |
auto[1] |
auto[0] |
1400 |
1 |
|
|
T3 |
17 |
|
T7 |
3 |
|
T62 |
6 |
auto[1] |
auto[1] |
3283 |
1 |
|
|
T2 |
11 |
|
T3 |
48 |
|
T5 |
17 |
Summary for Variable enable
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1293 |
1 |
|
|
T61 |
3 |
|
T62 |
24 |
|
T56 |
3 |
auto[1] |
4788 |
1 |
|
|
T2 |
11 |
|
T3 |
65 |
|
T5 |
17 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1293 |
1 |
|
|
T61 |
3 |
|
T62 |
24 |
|
T56 |
3 |
auto[1] |
4788 |
1 |
|
|
T2 |
11 |
|
T3 |
65 |
|
T5 |
17 |
Summary for Variable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1725 |
1 |
|
|
T3 |
23 |
|
T9 |
1 |
|
T61 |
1 |
auto[1] |
4356 |
1 |
|
|
T2 |
11 |
|
T3 |
42 |
|
T5 |
17 |
Summary for Variable rst_n_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1725 |
1 |
|
|
T3 |
23 |
|
T9 |
1 |
|
T61 |
1 |
auto[1] |
4356 |
1 |
|
|
T2 |
11 |
|
T3 |
42 |
|
T5 |
17 |
Summary for Cross sw_rst_cross
Samples crossed: enable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for sw_rst_cross
Bins
enable | rst_n | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
344 |
1 |
|
|
T61 |
1 |
|
T62 |
6 |
|
T56 |
2 |
auto[0] |
auto[1] |
949 |
1 |
|
|
T61 |
2 |
|
T62 |
18 |
|
T56 |
1 |
auto[1] |
auto[0] |
1381 |
1 |
|
|
T3 |
23 |
|
T9 |
1 |
|
T62 |
6 |
auto[1] |
auto[1] |
3407 |
1 |
|
|
T2 |
11 |
|
T3 |
42 |
|
T5 |
17 |
Summary for Variable enable
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1078 |
1 |
|
|
T62 |
20 |
|
T56 |
3 |
|
T54 |
20 |
auto[1] |
4992 |
1 |
|
|
T2 |
11 |
|
T3 |
65 |
|
T5 |
17 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1078 |
1 |
|
|
T62 |
20 |
|
T56 |
3 |
|
T54 |
20 |
auto[1] |
4992 |
1 |
|
|
T2 |
11 |
|
T3 |
65 |
|
T5 |
17 |
Summary for Variable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1749 |
1 |
|
|
T3 |
18 |
|
T9 |
1 |
|
T61 |
1 |
auto[1] |
4321 |
1 |
|
|
T2 |
11 |
|
T3 |
47 |
|
T5 |
17 |
Summary for Variable rst_n_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1749 |
1 |
|
|
T3 |
18 |
|
T9 |
1 |
|
T61 |
1 |
auto[1] |
4321 |
1 |
|
|
T2 |
11 |
|
T3 |
47 |
|
T5 |
17 |
Summary for Cross sw_rst_cross
Samples crossed: enable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for sw_rst_cross
Bins
enable | rst_n | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
289 |
1 |
|
|
T62 |
5 |
|
T56 |
1 |
|
T54 |
5 |
auto[0] |
auto[1] |
789 |
1 |
|
|
T62 |
15 |
|
T56 |
2 |
|
T54 |
15 |
auto[1] |
auto[0] |
1460 |
1 |
|
|
T3 |
18 |
|
T9 |
1 |
|
T61 |
1 |
auto[1] |
auto[1] |
3532 |
1 |
|
|
T2 |
11 |
|
T3 |
47 |
|
T5 |
17 |
Summary for Variable enable
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
857 |
1 |
|
|
T62 |
16 |
|
T55 |
3 |
|
T54 |
16 |
auto[1] |
5213 |
1 |
|
|
T2 |
11 |
|
T3 |
65 |
|
T5 |
17 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
857 |
1 |
|
|
T62 |
16 |
|
T55 |
3 |
|
T54 |
16 |
auto[1] |
5213 |
1 |
|
|
T2 |
11 |
|
T3 |
65 |
|
T5 |
17 |
Summary for Variable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1747 |
1 |
|
|
T3 |
21 |
|
T9 |
1 |
|
T61 |
1 |
auto[1] |
4323 |
1 |
|
|
T2 |
11 |
|
T3 |
44 |
|
T5 |
17 |
Summary for Variable rst_n_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1747 |
1 |
|
|
T3 |
21 |
|
T9 |
1 |
|
T61 |
1 |
auto[1] |
4323 |
1 |
|
|
T2 |
11 |
|
T3 |
44 |
|
T5 |
17 |
Summary for Cross sw_rst_cross
Samples crossed: enable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for sw_rst_cross
Bins
enable | rst_n | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
229 |
1 |
|
|
T62 |
4 |
|
T55 |
2 |
|
T54 |
4 |
auto[0] |
auto[1] |
628 |
1 |
|
|
T62 |
12 |
|
T55 |
1 |
|
T54 |
12 |
auto[1] |
auto[0] |
1518 |
1 |
|
|
T3 |
21 |
|
T9 |
1 |
|
T61 |
1 |
auto[1] |
auto[1] |
3695 |
1 |
|
|
T2 |
11 |
|
T3 |
44 |
|
T5 |
17 |
Summary for Variable enable
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
690 |
1 |
|
|
T61 |
3 |
|
T62 |
12 |
|
T56 |
3 |
auto[1] |
5380 |
1 |
|
|
T2 |
11 |
|
T3 |
65 |
|
T5 |
17 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
690 |
1 |
|
|
T61 |
3 |
|
T62 |
12 |
|
T56 |
3 |
auto[1] |
5380 |
1 |
|
|
T2 |
11 |
|
T3 |
65 |
|
T5 |
17 |
Summary for Variable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1732 |
1 |
|
|
T3 |
22 |
|
T61 |
2 |
|
T62 |
15 |
auto[1] |
4338 |
1 |
|
|
T2 |
11 |
|
T3 |
43 |
|
T5 |
17 |
Summary for Variable rst_n_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1732 |
1 |
|
|
T3 |
22 |
|
T61 |
2 |
|
T62 |
15 |
auto[1] |
4338 |
1 |
|
|
T2 |
11 |
|
T3 |
43 |
|
T5 |
17 |
Summary for Cross sw_rst_cross
Samples crossed: enable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for sw_rst_cross
Bins
enable | rst_n | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
196 |
1 |
|
|
T61 |
2 |
|
T62 |
3 |
|
T56 |
2 |
auto[0] |
auto[1] |
494 |
1 |
|
|
T61 |
1 |
|
T62 |
9 |
|
T56 |
1 |
auto[1] |
auto[0] |
1536 |
1 |
|
|
T3 |
22 |
|
T62 |
12 |
|
T55 |
1 |
auto[1] |
auto[1] |
3844 |
1 |
|
|
T2 |
11 |
|
T3 |
43 |
|
T5 |
17 |
Summary for Variable enable
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
478 |
1 |
|
|
T62 |
8 |
|
T55 |
3 |
|
T54 |
8 |
auto[1] |
5592 |
1 |
|
|
T2 |
11 |
|
T3 |
65 |
|
T5 |
17 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
478 |
1 |
|
|
T62 |
8 |
|
T55 |
3 |
|
T54 |
8 |
auto[1] |
5592 |
1 |
|
|
T2 |
11 |
|
T3 |
65 |
|
T5 |
17 |
Summary for Variable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1741 |
1 |
|
|
T3 |
25 |
|
T61 |
1 |
|
T62 |
9 |
auto[1] |
4329 |
1 |
|
|
T2 |
11 |
|
T3 |
40 |
|
T5 |
17 |
Summary for Variable rst_n_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1741 |
1 |
|
|
T3 |
25 |
|
T61 |
1 |
|
T62 |
9 |
auto[1] |
4329 |
1 |
|
|
T2 |
11 |
|
T3 |
40 |
|
T5 |
17 |
Summary for Cross sw_rst_cross
Samples crossed: enable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for sw_rst_cross
Bins
enable | rst_n | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
136 |
1 |
|
|
T62 |
2 |
|
T55 |
1 |
|
T54 |
2 |
auto[0] |
auto[1] |
342 |
1 |
|
|
T62 |
6 |
|
T55 |
2 |
|
T54 |
6 |
auto[1] |
auto[0] |
1605 |
1 |
|
|
T3 |
25 |
|
T61 |
1 |
|
T62 |
7 |
auto[1] |
auto[1] |
3987 |
1 |
|
|
T2 |
11 |
|
T3 |
40 |
|
T5 |
17 |
Summary for Variable enable
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
281 |
1 |
|
|
T9 |
3 |
|
T62 |
4 |
|
T56 |
3 |
auto[1] |
5789 |
1 |
|
|
T2 |
11 |
|
T3 |
65 |
|
T5 |
17 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
281 |
1 |
|
|
T9 |
3 |
|
T62 |
4 |
|
T56 |
3 |
auto[1] |
5789 |
1 |
|
|
T2 |
11 |
|
T3 |
65 |
|
T5 |
17 |
Summary for Variable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1763 |
1 |
|
|
T3 |
22 |
|
T9 |
1 |
|
T62 |
16 |
auto[1] |
4307 |
1 |
|
|
T2 |
11 |
|
T3 |
43 |
|
T5 |
17 |
Summary for Variable rst_n_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for rst_n_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1763 |
1 |
|
|
T3 |
22 |
|
T9 |
1 |
|
T62 |
16 |
auto[1] |
4307 |
1 |
|
|
T2 |
11 |
|
T3 |
43 |
|
T5 |
17 |
Summary for Cross sw_rst_cross
Samples crossed: enable rst_n
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for sw_rst_cross
Bins
enable | rst_n | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
91 |
1 |
|
|
T9 |
1 |
|
T62 |
1 |
|
T56 |
2 |
auto[0] |
auto[1] |
190 |
1 |
|
|
T9 |
2 |
|
T62 |
3 |
|
T56 |
1 |
auto[1] |
auto[0] |
1672 |
1 |
|
|
T3 |
22 |
|
T62 |
15 |
|
T55 |
1 |
auto[1] |
auto[1] |
4117 |
1 |
|
|
T2 |
11 |
|
T3 |
43 |
|
T5 |
17 |