Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	629609	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

379454

1

T1

928

T2

65

T3

7287

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	538804	1			T1	1505		T2	99		T3	10868
values[0x0]	235351	1			T1	569		T2	46		T3	4383
values[0x1]	234908	1			T1	612		T2	58		T3	4406

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	528329	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

480734

1

T1

1214

T2

90

T3

9342

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3953	1			T1	12		T6	7		T8	3
valid_sources[0x01]	3076	1			T1	15		T6	9		T8	6
valid_sources[0x02]	3136	1			T1	14		T6	8		T8	16
valid_sources[0x03]	6271	1			T1	9		T3	5		T6	5
valid_sources[0x04]	3462	1			T1	8		T3	60		T6	7
valid_sources[0x05]	4826	1			T1	11		T5	311		T6	9
valid_sources[0x06]	3253	1			T1	13		T3	12		T6	16
valid_sources[0x07]	3423	1			T1	5		T3	9		T6	9
valid_sources[0x08]	4795	1			T1	18		T6	8		T8	5
valid_sources[0x09]	3901	1			T1	9		T3	211		T6	6
valid_sources[0x0a]	3205	1			T1	20		T3	103		T6	6
valid_sources[0x0b]	7562	1			T1	13		T3	100		T6	11
valid_sources[0x0c]	5004	1			T1	15		T6	8		T8	28
valid_sources[0x0d]	3313	1			T1	6		T3	2		T6	8
valid_sources[0x0e]	3083	1			T1	11		T3	9		T6	10
valid_sources[0x0f]	3052	1			T1	10		T6	17		T8	7
valid_sources[0x10]	3131	1			T1	6		T6	16		T8	3
valid_sources[0x11]	5169	1			T1	13		T3	4		T6	6
valid_sources[0x12]	3867	1			T1	7		T6	10		T8	16
valid_sources[0x13]	5836	1			T1	9		T3	206		T6	7
valid_sources[0x14]	3392	1			T1	16		T3	205		T6	14
valid_sources[0x15]	3433	1			T1	12		T3	10		T6	11
valid_sources[0x16]	3454	1			T1	12		T3	472		T6	10
valid_sources[0x17]	4004	1			T1	11		T6	10		T8	8
valid_sources[0x18]	3057	1			T1	19		T6	15		T8	10
valid_sources[0x19]	4527	1			T1	12		T6	8		T8	9
valid_sources[0x1a]	3221	1			T1	10		T3	142		T6	7
valid_sources[0x1b]	3440	1			T1	8		T6	14		T8	2
valid_sources[0x1c]	3568	1			T1	11		T6	9		T8	5
valid_sources[0x1d]	2902	1			T1	14		T3	12		T6	17
valid_sources[0x1e]	3697	1			T1	5		T6	7		T8	20
valid_sources[0x1f]	3071	1			T1	7		T6	7		T9	2
valid_sources[0x20]	3529	1			T1	15		T3	2		T6	7
valid_sources[0x21]	3603	1			T1	10		T6	9		T8	8
valid_sources[0x22]	6883	1			T1	13		T3	156		T6	5
valid_sources[0x23]	3701	1			T1	13		T3	2		T6	10
valid_sources[0x24]	3600	1			T1	10		T6	3		T8	9
valid_sources[0x25]	3664	1			T1	9		T3	210		T6	7
valid_sources[0x26]	3930	1			T1	12		T3	9		T6	10
valid_sources[0x27]	3455	1			T1	9		T3	113		T6	13
valid_sources[0x28]	3964	1			T1	19		T3	662		T6	6
valid_sources[0x29]	3501	1			T1	12		T3	105		T6	7
valid_sources[0x2a]	4196	1			T1	9		T3	3		T6	7
valid_sources[0x2b]	7047	1			T1	8		T3	197		T6	7
valid_sources[0x2c]	4491	1			T1	10		T3	7		T6	10
valid_sources[0x2d]	3225	1			T1	15		T6	13		T8	6
valid_sources[0x2e]	3914	1			T1	10		T3	57		T6	4
valid_sources[0x2f]	3463	1			T1	14		T6	10		T8	7
valid_sources[0x30]	4959	1			T1	8		T6	10		T8	12
valid_sources[0x31]	4106	1			T1	14		T3	53		T6	11
valid_sources[0x32]	5299	1			T1	16		T3	1213		T6	6
valid_sources[0x33]	6887	1			T1	13		T3	170		T6	12
valid_sources[0x34]	4055	1			T1	15		T6	10		T8	13
valid_sources[0x35]	4081	1			T1	10		T6	9		T8	22
valid_sources[0x36]	3454	1			T1	14		T6	3		T8	13
valid_sources[0x37]	3946	1			T1	9		T6	6		T8	2
valid_sources[0x38]	3921	1			T1	3		T3	13		T6	11
valid_sources[0x39]	6469	1			T1	12		T6	10		T8	11
valid_sources[0x3a]	4049	1			T1	6		T3	592		T6	8
valid_sources[0x3b]	3639	1			T1	17		T6	12		T8	7
valid_sources[0x3c]	3370	1			T1	6		T3	5		T6	10
valid_sources[0x3d]	3081	1			T1	10		T6	8		T8	16
valid_sources[0x3e]	2929	1			T1	10		T6	10		T8	7
valid_sources[0x3f]	3828	1			T1	10		T6	12		T9	2
valid_sources[0x40]	4155	1			T1	5		T6	10		T8	2
valid_sources[0x41]	4699	1			T1	19		T6	11		T8	9
valid_sources[0x42]	4202	1			T1	8		T6	7		T8	10
valid_sources[0x43]	3351	1			T1	10		T3	240		T6	9
valid_sources[0x44]	3243	1			T1	12		T3	14		T6	8
valid_sources[0x45]	4216	1			T1	8		T3	10		T6	17
valid_sources[0x46]	7930	1			T1	12		T6	7		T8	1
valid_sources[0x47]	3097	1			T1	6		T6	14		T8	15
valid_sources[0x48]	2851	1			T1	9		T6	10		T8	18
valid_sources[0x49]	4846	1			T1	9		T3	185		T6	14
valid_sources[0x4a]	4355	1			T1	10		T3	198		T6	8
valid_sources[0x4b]	3395	1			T1	14		T3	112		T6	4
valid_sources[0x4c]	3052	1			T1	11		T3	14		T6	10
valid_sources[0x4d]	3315	1			T1	10		T6	11		T8	1
valid_sources[0x4e]	3837	1			T1	8		T3	82		T6	9
valid_sources[0x4f]	3086	1			T1	6		T3	6		T6	5
valid_sources[0x50]	3561	1			T1	9		T3	183		T6	3
valid_sources[0x51]	3094	1			T1	13		T6	10		T8	2
valid_sources[0x52]	3589	1			T1	10		T3	60		T6	15
valid_sources[0x53]	3336	1			T1	12		T3	141		T6	7
valid_sources[0x54]	3182	1			T1	15		T6	9		T8	6
valid_sources[0x55]	3061	1			T1	8		T3	103		T6	7
valid_sources[0x56]	4065	1			T1	9		T3	235		T6	8
valid_sources[0x57]	4365	1			T1	3		T3	155		T6	8
valid_sources[0x58]	3869	1			T1	5		T3	4		T6	10
valid_sources[0x59]	4153	1			T1	23		T3	116		T6	11
valid_sources[0x5a]	3304	1			T1	10		T6	12		T8	7
valid_sources[0x5b]	3448	1			T1	10		T6	12		T8	9
valid_sources[0x5c]	3333	1			T1	9		T6	10		T11	15
valid_sources[0x5d]	3694	1			T1	9		T3	70		T6	10
valid_sources[0x5e]	3508	1			T1	12		T3	59		T6	6
valid_sources[0x5f]	3996	1			T1	6		T2	203		T3	10
valid_sources[0x60]	3176	1			T1	11		T6	9		T8	7
valid_sources[0x61]	3854	1			T1	7		T6	11		T8	40
valid_sources[0x62]	3268	1			T1	8		T3	1		T6	10
valid_sources[0x63]	4444	1			T1	18		T6	11		T8	16
valid_sources[0x64]	3023	1			T1	6		T6	8		T8	1
valid_sources[0x65]	3521	1			T1	9		T3	231		T6	12
valid_sources[0x66]	4014	1			T1	13		T3	155		T6	5
valid_sources[0x67]	3592	1			T1	11		T3	155		T6	10
valid_sources[0x68]	4348	1			T1	7		T6	13		T8	22
valid_sources[0x69]	3766	1			T1	8		T3	11		T6	14
valid_sources[0x6a]	4970	1			T1	20		T6	5		T8	30
valid_sources[0x6b]	3386	1			T1	13		T3	61		T6	10
valid_sources[0x6c]	3072	1			T1	8		T3	6		T6	10
valid_sources[0x6d]	3282	1			T1	8		T6	5		T8	8
valid_sources[0x6e]	2957	1			T1	11		T6	8		T8	1
valid_sources[0x6f]	3525	1			T1	11		T3	14		T6	11
valid_sources[0x70]	3905	1			T1	11		T6	15		T11	12
valid_sources[0x71]	3314	1			T1	8		T6	13		T8	37
valid_sources[0x72]	3801	1			T1	9		T6	11		T8	42
valid_sources[0x73]	3509	1			T1	11		T6	8		T8	1
valid_sources[0x74]	3863	1			T1	10		T3	421		T6	6
valid_sources[0x75]	3809	1			T1	13		T3	283		T6	8
valid_sources[0x76]	3053	1			T1	9		T3	7		T6	8
valid_sources[0x77]	4100	1			T1	9		T3	148		T6	7
valid_sources[0x78]	3312	1			T1	5		T3	1		T6	5
valid_sources[0x79]	3486	1			T1	14		T3	62		T6	9
valid_sources[0x7a]	4276	1			T1	14		T6	12		T8	13
valid_sources[0x7b]	3017	1			T1	12		T6	16		T8	7
valid_sources[0x7c]	3268	1			T1	6		T6	13		T8	12
valid_sources[0x7d]	3244	1			T1	8		T6	14		T8	9
valid_sources[0x7e]	4205	1			T1	12		T3	5		T6	11
valid_sources[0x7f]	3682	1			T1	5		T6	8		T8	8
valid_sources[0x80]	4647	1			T1	10		T3	117		T6	12

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

253157

1

T1

664

T2

46

T3

5092

values[0x0]

all_enables

biggest_size

82388

1

T1

177

T2

13

T3

1512

values[0x1]

all_enables

biggest_size

43909

1

T1

87

T2

6

T3

683